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Merge "ARM: dts: msm: Adding all CoreTech DT Changes to Mainline 5.4"

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This commit is contained in:
qctecmdr 2020-12-22 07:07:14 -08:00 • committed by Gerrit - the friendly Code Review server
commit f82800debd
10 changed files with 2538 additions and 127 deletions
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30
qcom/sa8155-adp-common.dtsi
View file

@ -3,6 +3,10 @@
#include "sa8155-pmic-overlay.dtsi"
&qupv3_3 {
status = "ok"
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4";
@ -27,3 +31,29 @@
status = "ok"
};
&pcie1 {
qcom,boot-option = <0x0>;
};
&sdhc_2 {
vdd-supply = <&pm8150_1_l17>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <200 800000>;
vdd-io-supply = <&pm8150_2_l13>;
qcom,vdd-io-voltage-level = <1808000 2960000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&pm8150_1_gpios 4 GPIO_ACTIVE_LOW>;
status = "ok"
};
&qupv3_se12_2uart {
status = "ok"
};

248
qcom/sa8155-v2.dtsi
View file

@ -7,6 +7,254 @@
qcom,msm-id = <362 0x20000>;
};
&pcie0 {
qcom,pcie-phy-ver = <2114>;
qcom,phy-sequence = <0x0840 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xb9 0x0
0x01b8 0x18 0x0
0x01b4 0x94 0x0
0x0050 0x07 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x029c 0x12 0x0
0x0284 0x35 0x0
0x0288 0x82 0x0
0x023c 0x11 0x0
0x051c 0x03 0x0
0x0518 0x1c 0x0
0x0524 0x1e 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x05b4 0x04 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x0510 0x17 0x0
0x04d4 0x04 0x0
0x04d8 0x07 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x3b 0x0
0x05a8 0x31 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x3b 0x0
0x0594 0x36 0x0
0x0570 0xff 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0x7f 0x0
0x0580 0x66 0x0
0x04fc 0x00 0x0
0x04f8 0xc0 0x0
0x0460 0x30 0x0
0x0464 0x00 0x0
0x05bc 0x0c 0x0
0x04dc 0x0d 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x09a4 0x01 0x0
0x0c90 0x00 0x0
0x0c40 0x01 0x0
0x0c48 0x01 0x0
0x0c50 0x00 0x0
0x0cb4 0x33 0x0
0x0cbc 0x00 0x0
0x0ce0 0x58 0x0
0x0ca4 0x0f 0x0
0x0048 0x90 0x0
0x0c1c 0xc1 0x0
0x0988 0x88 0x0
0x0998 0x0b 0x0
0x08dc 0x0d 0x0
0x09ec 0x12 0x0
0x0800 0x00 0x0
0x0844 0x03 0x0>;
};
&pcie1 {
qcom,pcie-phy-ver = <2111>;
qcom,phy-sequence = <0x0a40 0x03 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x023c 0x11 0x0
0x0284 0x35 0x0
0x0288 0x82 0x0
0x029c 0x12 0x0
0x0304 0x02 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x0460 0x30 0x0
0x0464 0x00 0x0
0x04d4 0x04 0x0
0x04d8 0x07 0x0
0x04dc 0x0d 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x04f8 0xc0 0x0
0x04fc 0x00 0x0
0x0510 0x17 0x0
0x0518 0x1c 0x0
0x051c 0x03 0x0
0x0524 0x1e 0x0
0x0570 0xff 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0x7f 0x0
0x0580 0x66 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x3b 0x0
0x0594 0x36 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x3b 0x0
0x05a8 0x31 0x0
0x05bc 0x0c 0x0
0x063c 0x11 0x0
0x0684 0x35 0x0
0x0688 0x82 0x0
0x069c 0x12 0x0
0x0704 0x20 0x0
0x0808 0x0c 0x0
0x0814 0x03 0x0
0x0834 0x7f 0x0
0x0844 0x70 0x0
0x0860 0x30 0x0
0x0864 0x00 0x0
0x08d4 0x04 0x0
0x08d8 0x07 0x0
0x08dc 0x0d 0x0
0x08e8 0x00 0x0
0x08ec 0x0e 0x0
0x08f0 0x4a 0x0
0x08f4 0x0f 0x0
0x08f8 0xc0 0x0
0x08fc 0x00 0x0
0x0910 0x17 0x0
0x0918 0x1c 0x0
0x091c 0x03 0x0
0x0924 0x1e 0x0
0x0970 0xff 0x0
0x0974 0xff 0x0
0x0978 0xff 0x0
0x097c 0x7f 0x0
0x0980 0x66 0x0
0x0984 0x24 0x0
0x0988 0xe4 0x0
0x098c 0xec 0x0
0x0990 0x3b 0x0
0x0994 0x36 0x0
0x0998 0xd4 0x0
0x099c 0x54 0x0
0x09a0 0xdb 0x0
0x09a4 0x3b 0x0
0x09a8 0x31 0x0
0x09bc 0x0c 0x0
0x0adc 0x05 0x0
0x0b88 0x88 0x0
0x0b98 0x0b 0x0
0x0ba4 0x01 0x0
0x0bec 0x12 0x0
0x0e0c 0x0d 0x0
0x0e14 0x07 0x0
0x0e1c 0xc1 0x0
0x0e40 0x01 0x0
0x0e48 0x01 0x0
0x0e90 0x00 0x0
0x0eb4 0x33 0x0
0x0ebc 0x00 0x0
0x0ee0 0x58 0x0
0x0ea4 0x0f 0x0
0x0a00 0x00 0x0
0x0a44 0x03 0x0>;
};
&scc {
compatible = "qcom,sa8155-scc-v2", "syscon";
};

32
qcom/sa8155.dtsi
View file

@ -53,9 +53,41 @@
status = "ok"
};
&usb2_phy0 {
vdd-supply = <&pm8150_1_l5>;
vdda18-supply = <&pm8150_1_l12>;
vdda33-supply = <&pm8150_1_l2>;
};
&usb2_phy1 {
vdd-supply = <&pm8150_1_l5>;
vdda18-supply = <&pm8150_1_l12>;
vdda33-supply = <&pm8150_1_l2>;
};
&usb_qmp_phy {
vdd-supply = <&pm8150_1_l5>;
core-supply = <&pm8150_2_l8>;
};
/* Add regulator nodes specific to SA8155 */
#include "sa8155-regulator.dtsi"
&pcie0 {
vreg-1p8-supply = <&pm8150_2_l8>;
vreg-0p9-supply = <&pm8150_2_l18>;
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
qcom,core-preset = <0x77777777>;
};
&pcie1 {
vreg-1p8-supply = <&pm8150_2_l8>;
vreg-0p9-supply = <&pm8150_2_l18>;
qcom,core-preset = <0x77777777>;
};
&gpucc {
compatible = "qcom,sa8155-gpucc", "syscon";
};

593
qcom/sm8150-pcie.dtsi Normal file
View file

@ -0,0 +1,593 @@
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
cell-index = <0>;
reg = <0x1c00000 0x4000>,
<0x1c04000 0x1000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x60200000 0x100000>,
<0x60300000 0x3d00000>;
reg-names = "parf", "phy", "dm_core", "elbi",
"iatu", "conf", "io", "bars";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
qcom,phy-sequence = <0x0840 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xb9 0x0
0x01b8 0x18 0x0
0x01b4 0x94 0x0
0x0050 0x07 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x029c 0x12 0x0
0x0284 0x05 0x0
0x0c38 0x03 0x0
0x0518 0x1c 0x0
0x0524 0x14 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x05b4 0x04 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x0510 0x17 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x39 0x0
0x05a8 0x31 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x39 0x0
0x0594 0x37 0x0
0x0570 0x7f 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0xdb 0x0
0x0580 0x75 0x0
0x04fc 0x00 0x0
0x04f8 0xc0 0x0
0x0414 0x04 0x0
0x09a4 0x01 0x0
0x0c90 0x00 0x0
0x0c40 0x01 0x0
0x0c48 0x01 0x0
0x0c50 0x00 0x0
0x0048 0x90 0x0
0x0c1c 0xc1 0x0
0x0988 0x66 0x0
0x0998 0x08 0x0
0x08dc 0x0d 0x0
0x09ec 0x01 0x0
0x04b4 0x02 0x0
0x04b8 0x02 0x0
0x04bc 0xaa 0x0
0x04c0 0x00 0x0
0x04d4 0x54 0x0
0x04d8 0x07 0x0
0x0460 0xa0 0x0
0x05c4 0x0c 0x0
0x0464 0x00 0x0
0x05c0 0x10 0x0
0x04dc 0x05 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x0800 0x00 0x0
0x0844 0x03 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_clkreq_default
&pcie0_perst_default
&pcie0_wake_default>;
perst-gpio = <&tlmm 35 0>;
wake-gpio = <&tlmm 37 0>;
gdsc-vdd-supply = <&pcie_0_gdsc>;
vreg-1p8-supply = <&pm8150l_l3>;
vreg-0p9-supply = <&pm8150_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;
qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
RPMH_REGULATOR_LEVEL_NOM 100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
msi-parent = <&pcie0_msi>;
qcom,no-l0s-supported;
qcom,ep-latency = <10>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,phy-status-offset = <0x814>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x840>;
qcom,boot-option = <0x1>;
linux,pci-domain = <0>;
qcom,pcie-phy-ver = <0x40>;
qcom,use-19p2mhz-aux-clk;
qcom,smmu-sid-base = <0x1d80>;
dma-coherent;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>,
<0x200 &apps_smmu 0x1d82 0x1>,
<0x300 &apps_smmu 0x1d83 0x1>,
<0x400 &apps_smmu 0x1d84 0x1>,
<0x500 &apps_smmu 0x1d85 0x1>,
<0x600 &apps_smmu 0x1d86 0x1>,
<0x700 &apps_smmu 0x1d87 0x1>,
<0x800 &apps_smmu 0x1d88 0x1>,
<0x900 &apps_smmu 0x1d89 0x1>,
<0xa00 &apps_smmu 0x1d8a 0x1>,
<0xb00 &apps_smmu 0x1d8b 0x1>,
<0xc00 &apps_smmu 0x1d8c 0x1>,
<0xd00 &apps_smmu 0x1d8d 0x1>,
<0xe00 &apps_smmu 0x1d8e 0x1>,
<0xf00 &apps_smmu 0x1d8f 0x1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_PHY_AUX_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_phy_aux_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
pcie_rc0: pcie_rc0 {
#address-cells = <5>;
#size-cells = <0>;
reg = <0 0 0 0 0>;
pci-ids = "17cb:0108";
};
};
pcie0_msi: qcom,pcie0_msi@17a00040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17a00040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
};
pcie1: qcom,pcie@1c08000 {
compatible = "qcom,pci-msm";
cell-index = <1>;
reg = <0x1c08000 0x4000>,
<0x1c0c000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>,
<0x40200000 0x100000>,
<0x40300000 0x1fd00000>;
reg-names = "parf", "phy", "dm_core", "elbi",
"iatu", "conf", "io", "bars";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
interrupt-parent = <&pcie1>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
qcom,phy-sequence = <0x0a40 0x03 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0050 0x07 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x32 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x01 0x0
0x0284 0x05 0x0
0x029c 0x12 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x04d8 0x01 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x04f8 0xc0 0x0
0x04fc 0x00 0x0
0x0510 0x17 0x0
0x0518 0x1c 0x0
0x051c 0x03 0x0
0x0524 0x14 0x0
0x0570 0x7f 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0xdb 0x0
0x0580 0x75 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x39 0x0
0x0594 0x36 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x39 0x0
0x05a8 0x31 0x0
0x05b4 0x04 0x0
0x04b4 0x02 0x0
0x04b8 0x02 0x0
0x04bc 0xaa 0x0
0x04c0 0x00 0x0
0x04d4 0x54 0x0
0x04d8 0x07 0x0
0x0460 0xa0 0x0
0x05c4 0x0c 0x0
0x0464 0x00 0x0
0x05c0 0x10 0x0
0x04dc 0x05 0x0
0x0684 0x05 0x0
0x069c 0x12 0x0
0x0808 0x0c 0x0
0x0814 0x03 0x0
0x0834 0x7f 0x0
0x0844 0x70 0x0
0x08d8 0x01 0x0
0x08e8 0x00 0x0
0x08ec 0x0e 0x0
0x08f0 0x4a 0x0
0x08f4 0x0f 0x0
0x08f8 0xc0 0x0
0x08fc 0x00 0x0
0x0910 0x17 0x0
0x0918 0x1c 0x0
0x091c 0x03 0x0
0x0924 0x14 0x0
0x0970 0x7f 0x0
0x0974 0xff 0x0
0x0978 0xff 0x0
0x097c 0xdb 0x0
0x0980 0x75 0x0
0x0984 0x24 0x0
0x0988 0xe4 0x0
0x098c 0xec 0x0
0x0990 0x3a 0x0
0x0994 0x36 0x0
0x0998 0xd4 0x0
0x099c 0x54 0x0
0x09a0 0xdb 0x0
0x09a4 0x39 0x0
0x09a8 0x31 0x0
0x09b4 0x04 0x0
0x08b4 0x02 0x0
0x08b8 0x02 0x0
0x08bc 0xaa 0x0
0x08c0 0x00 0x0
0x08d4 0x54 0x0
0x08d8 0x07 0x0
0x0860 0xa0 0x0
0x09c4 0x0c 0x0
0x0864 0x00 0x0
0x09c0 0x10 0x0
0x08dc 0x05 0x0
0x0a98 0x01 0x0
0x0abc 0x56 0x0
0x0adc 0x0d 0x0
0x0b88 0x66 0x0
0x0ba4 0x01 0x0
0x0b98 0x08 0x0
0x0e14 0x07 0x0
0x0e1c 0xc1 0x0
0x0e40 0x01 0x0
0x0e48 0x01 0x0
0x0e78 0x50 0x0
0x0e90 0x00 0x0
0x0ea0 0x11 0x0
0x0e38 0x03 0x0
0x0e50 0x00 0x0
0x0e20 0x01 0x0
0x0a00 0x00 0x0
0x0a44 0x03 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_default
&pcie1_perst_default
&pcie1_wake_default>;
perst-gpio = <&tlmm 102 0>;
wake-gpio = <&tlmm 104 0>;
gdsc-vdd-supply = <&pcie_1_gdsc>;
vreg-1p8-supply = <&pm8150l_l3>;
vreg-0p9-supply = <&pm8150_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>;
qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
RPMH_REGULATOR_LEVEL_NOM 100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
msi-parent = <&pcie1_msi>;
qcom,no-l0s-supported;
qcom,ep-latency = <10>;
qcom,slv-addr-space-size = <0x20000000>;
qcom,phy-status-offset = <0xa14>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0xa40>;
qcom,boot-option = <0x1>;
linux,pci-domain = <1>;
qcom,pcie-phy-ver = <0x40>;
qcom,use-19p2mhz-aux-clk;
qcom,smmu-sid-base = <0x1e00>;
dma-coherent;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>,
<0x200 &apps_smmu 0x1e02 0x1>,
<0x300 &apps_smmu 0x1e03 0x1>,
<0x400 &apps_smmu 0x1e04 0x1>,
<0x500 &apps_smmu 0x1e05 0x1>,
<0x600 &apps_smmu 0x1e06 0x1>,
<0x700 &apps_smmu 0x1e07 0x1>,
<0x800 &apps_smmu 0x1e08 0x1>,
<0x900 &apps_smmu 0x1e09 0x1>,
<0xa00 &apps_smmu 0x1e0a 0x1>,
<0xb00 &apps_smmu 0x1e0b 0x1>,
<0xc00 &apps_smmu 0x1e0c 0x1>,
<0xd00 &apps_smmu 0x1e0d 0x1>,
<0xe00 &apps_smmu 0x1e0e 0x1>,
<0xf00 &apps_smmu 0x1e0f 0x1>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_PHY_AUX_CLK>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
"pcie_tbu_clk", "pcie_phy_refgen_clk",
"pcie_phy_aux_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "pcie_1_core_reset",
"pcie_1_phy_reset";
pcie_rc1: pcie_rc1 {
#address-cells = <5>;
#size-cells = <0>;
reg = <0 0 0 0 0>;
pci-ids = "17cb:0108";
};
};
pcie1_msi: qcom,pcie1_msi@17a00040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17a00040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
};
};

157
qcom/sm8150-pinctrl.dtsi
View file

@ -68,160 +68,55 @@
};
};
storage_cd: storage_cd {
mux {
pins = "gpio96";
function = "gpio";
sdc2_on: sdc2_on {
clk {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
config {
cmd {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
data {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
sd-cd {
pins = "gpio96";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_clk_on: sdc2_clk_on {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_clk_off: sdc2_clk_off {
config {
sdc2_off: sdc2_off {
clk {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_off: sdc2_cmd_off {
config {
cmd {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_off: sdc2_data_off {
config {
data {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
sd-cd {
pins = "gpio96";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};

829
qcom/sm8150-qupv3.dtsi Normal file
View file

@ -0,0 +1,829 @@
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
&soc {
/* QUPv3 South Instances
* South 0 : SE 0
* South 1 : SE 1
* South 2 : SE 2
* South 3 : SE 3
* South 4 : SE 4
* South 5 : SE 5
* South 6 : SE 6
* South 7 : SE 7
*
* QUPv3 North & East Instances
* North 0 : SE 8
* North 1 : SE 9
* North 2 : SE 10
* North 3 : SE 11
* North 4 : SE 12
* North 5 : SE 16
* East 0 : SE 17
* East 1 : SE 18
* East 2 : SE 19
* East 3 : SE 13
* East 4 : SE 14
* East 5 : SE 15
*/
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x8c0000 0x6000>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_QUP_0 SLAVE_EBI1>;
iommus = <&apps_smmu 0xc3 0x0>;
qcom,iommu-dma = "fastmap";
status = "ok"
};
/* I2C */
qupv3_se0_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se1_i2c: i2c@884000 {
compatible = "qcom,i2c-geni";
reg = <0x884000 0x4000>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se2_i2c: i2c@888000 {
compatible = "qcom,i2c-geni";
reg = <0x888000 0x4000>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se3_i2c: i2c@88c000 {
compatible = "qcom,i2c-geni";
reg = <0x88c000 0x4000>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se4_i2c: i2c@890000 {
compatible = "qcom,i2c-geni";
reg = <0x890000 0x4000>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se5_i2c: i2c@894000 {
compatible = "qcom,i2c-geni";
reg = <0x894000 0x4000>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se6_i2c: i2c@898000 {
compatible = "qcom,i2c-geni";
reg = <0x898000 0x4000>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se7_i2c: i2c@89c000 {
compatible = "qcom,i2c-geni";
reg = <0x89c000 0x4000>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
/* SPI */
qupv3_se0_spi: spi@880000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x880000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se1_spi: spi@884000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x884000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se2_spi: spi@888000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x888000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se3_spi: spi@88c000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x88c000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep &qupv3_se3_spi_miso_sleep>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se4_spi: spi@890000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x890000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se5_spi: spi@894000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x894000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se6_spi: spi@898000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x898000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_se7_spi: spi@89c000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x89c000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_active>;
pinctrl-1 = <&qupv3_se7_spi_sleep>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0xac0000 0x6000>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_QUP_1 SLAVE_EBI1>;
iommus = <&apps_smmu 0x603 0x0>;
qcom,iommu-dma = "fastmap";
status = "ok"
};
/* Debug UART Instance for CDP/MTP platform */
qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
compatible = "qcom,msm-geni-console";
reg = <0xa90000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_2uart_active>;
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
/* 4-wire UART */
qupv3_se13_4uart: qcom,qup_uart@0xc8c000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xc8c000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "active", "sleep";
pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,
<&qupv3_se13_default_tx>;
pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
<&qupv3_se13_tx>;
pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
<&qupv3_se13_tx>;
interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 46 0>;
qcom,wrapper-core = <&qupv3_2>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
/* I2C */
qupv3_se8_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se9_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se10_i2c: i2c@a88000 {
compatible = "qcom,i2c-geni";
reg = <0xa88000 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se11_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_i2c_active>;
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se12_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_i2c_active>;
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
/* SPI */
qupv3_se8_spi: spi@a80000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa80000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_active>;
pinctrl-1 = <&qupv3_se8_spi_active>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se9_spi: spi@a84000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se10_spi: spi@a88000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa88000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_spi_active>;
pinctrl-1 = <&qupv3_se10_spi_sleep>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se11_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa8c000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_spi_active>;
pinctrl-1 = <&qupv3_se11_spi_sleep>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se12_spi: spi@a90000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa90000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_spi_active>;
pinctrl-1 = <&qupv3_se12_spi_sleep>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
/* QUPv3 East Instances */
qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0xcc0000 0x6000>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_QUP_2 SLAVE_EBI1>;
iommus = <&apps_smmu 0x7a3 0x0>;
qcom,iommu-dma = "fastmap";
status = "ok"
};
/* I2C */
qupv3_se13_i2c: i2c@c8c000 {
compatible = "qcom,i2c-geni";
reg = <0xc8c000 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_i2c_active>;
pinctrl-1 = <&qupv3_se13_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se14_i2c: i2c@0xc90000 {
compatible = "qcom,i2c-geni";
reg = <0xc90000 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_i2c_active>;
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se15_i2c: i2c@0xc94000 {
compatible = "qcom,i2c-geni";
reg = <0xc94000 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se16_i2c: i2c@0xa94000 {
compatible = "qcom,i2c-geni";
reg = <0xa94000 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se16_i2c_active>;
pinctrl-1 = <&qupv3_se16_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se17_i2c: i2c@0xc80000 {
compatible = "qcom,i2c-geni";
reg = <0xc80000 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se17_i2c_active>;
pinctrl-1 = <&qupv3_se17_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se18_i2c: i2c@0xc84000 {
compatible = "qcom,i2c-geni";
reg = <0xc84000 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se18_i2c_active>;
pinctrl-1 = <&qupv3_se18_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se19_i2c: i2c@0xc88000 {
compatible = "qcom,i2c-geni";
reg = <0xc88000 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se19_i2c_active>;
pinctrl-1 = <&qupv3_se19_i2c_sleep>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
/* SPI */
qupv3_se13_spi: spi@c8c000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc8c000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_spi_active>;
pinctrl-1 = <&qupv3_se13_spi_sleep>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se14_spi: spi@c90000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc90000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_spi_active>;
pinctrl-1 = <&qupv3_se14_spi_sleep>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se15_spi: spi@c94000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc94000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_spi_active>;
pinctrl-1 = <&qupv3_se15_spi_sleep>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se16_spi: spi@a94000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se16_spi_active>;
pinctrl-1 = <&qupv3_se16_spi_sleep>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se17_spi: spi@c80000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc80000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se17_spi_active>;
pinctrl-1 = <&qupv3_se17_spi_sleep>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se18_spi: spi@c84000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se18_spi_active>;
pinctrl-1 = <&qupv3_se18_spi_sleep>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
qupv3_se19_spi: spi@c88000 {
compatible = "qcom,spi-geni";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc88000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se19_spi_active>;
pinctrl-1 = <&qupv3_se19_spi_sleep>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_2>;
status = "disabled";
};
};

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#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/clock/qcom,scc-sm8150.h>
&soc {
/* QUPv3 SSC Instance */
qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x26c0000 0x6000>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_SENSORS_AHB SLAVE_EBI1>;
iommus = <&apps_smmu 0x4e3 0x0>;
qcom,iommu-dma = "fastmap";
status = "disabled";
};
/* I2C*/
qupv3_se20_i2c: i2c@2680000 {
compatible = "qcom,i2c-geni";
reg = <0x2680000 0x4000>;
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&scc SCC_QUPV3_SE0_CLK>,
<&scc SCC_QUPV3_M_HCLK_CLK>,
<&scc SCC_QUPV3_S_HCLK_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se20_i2c_active>;
pinctrl-1 = <&qupv3_se20_i2c_sleep>;
qcom,wrapper-core = <&qupv3_3>;
status = "disabled";
};
qupv3_se21_i2c: i2c@2684000 {
compatible = "qcom,i2c-geni";
reg = <0x2684000 0x4000>;
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&scc SCC_QUPV3_SE1_CLK>,
<&scc SCC_QUPV3_M_HCLK_CLK>,
<&scc SCC_QUPV3_S_HCLK_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se21_i2c_active>;
pinctrl-1 = <&qupv3_se21_i2c_sleep>;
qcom,wrapper-core = <&qupv3_3>;
status = "disabled";
};
qupv3_se22_i2c: i2c@2688000 {
compatible = "qcom,i2c-geni";
reg = <0x2688000 0x4000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&scc SCC_QUPV3_SE2_CLK>,
<&scc SCC_QUPV3_M_HCLK_CLK>,
<&scc SCC_QUPV3_S_HCLK_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se22_i2c_active>;
pinctrl-1 = <&qupv3_se22_i2c_sleep>;
qcom,wrapper-core = <&qupv3_3>;
status = "disabled";
};
/* SPI */
qupv3_se21_spi: spi@2684000 {
compatible = "qcom,spi-geni";
reg = <0x2684000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&scc SCC_QUPV3_SE1_CLK>,
<&scc SCC_QUPV3_M_HCLK_CLK>,
<&scc SCC_QUPV3_S_HCLK_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se21_spi_active>;
pinctrl-1 = <&qupv3_se21_spi_sleep>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_3>;
qcom,disable-dma;
status = "disabled";
};
qupv3_se22_spi: spi@2688000 {
compatible = "qcom,spi-geni";
reg = <0x2688000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&scc SCC_QUPV3_SE2_CLK>,
<&scc SCC_QUPV3_M_HCLK_CLK>,
<&scc SCC_QUPV3_S_HCLK_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se22_spi_active>;
pinctrl-1 = <&qupv3_se22_spi_sleep>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_3>;
qcom,disable-dma;
status = "disabled";
};
};

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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
&soc {
/* Primary USB port related controller */
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x0a600000 0x100000>;
reg-names = "core_base";
iommus = <&apps_smmu 0x140 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges;
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
USB3_GDSC-supply = <&usb30_prim_gdsc>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
/*
* GCC_USB3_SEC_CLKREF_CLK provides ref_clk for both
* USB instances. Hence GCC_USB3_PRIM_CLKREF_CLK is not
* used here.
*/
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
qcom,ignore-wakeup-src-in-hostmode;
interconnect-names = "usb-ddr", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0x0a600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
maximum-speed = "high-speed";
dr_mode = "otg";
};
qcom,usbbam@a704000 {
compatible = "qcom,usb-bam-msm";
reg = <0xa704000 0x17000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
qcom,usb-bam-num-pipes = <4>;
qcom,disable-clk-gating;
qcom,usb-bam-override-threshold = <0x4001>;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,reset-bam-on-connect;
qcom,pipe0 {
label = "ssusb-qdss-in-0";
qcom,usb-bam-mem-type = <2>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <0>;
qcom,peer-bam-physical-address = <0x6064000>;
qcom,src-bam-pipe-index = <0>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x0>;
qcom,data-fifo-size = <0x1800>;
qcom,descriptor-fifo-offset = <0x1800>;
qcom,descriptor-fifo-size = <0x800>;
};
};
};
/* Primary USB port related High Speed PHY */
usb2_phy0: hsphy@88e2000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e2000 0x110>,
<0x007801f8 0x4>;
reg-names = "hsusb_phy_base",
"phy_rcal_reg";
vdd-supply = <&pm8150_l5>;
vdda18-supply = <&pm8150_l12>;
vdda33-supply = <&pm8150_l2>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
qcom,param-override-seq = <0x43 0x70
0x01 0xb0>;
qcom,rcal-mask = <0x1e00000>;
pinctrl-names = "default";
pinctrl-0 = <&usb2phy_ac_en1_default>;
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
/* Secondary USB port related controller */
usb1: ssusb@a800000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x0a800000 0x100000>;
reg-names = "core_base";
iommus = <&apps_smmu 0x160 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges;
interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
qcom,default-mode-host;
qcom,ignore-wakeup-src-in-hostmode;
USB3_GDSC-supply = <&usb30_sec_gdsc>;
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,ssp-u3-u0-quirk;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
tx-fifo-resize;
maximum-speed = "super-speed-plus";
dr_mode = "otg";
};
};
/* Secondary USB port related High Speed PHY */
usb2_phy1: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e3000 0x110>,
<0x007801f8 0x4>;
reg-names = "hsusb_phy_base",
"phy_rcal_reg";
vdd-supply = <&pm8150_l5>;
vdda18-supply = <&pm8150_l12>;
vdda33-supply = <&pm8150_l2>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
reset-names = "phy_reset";
qcom,param-override-seq = <0x43 0x70
0x01 0xb0>;
qcom,rcal-mask = <0x1e00000>;
pinctrl-names = "default";
pinctrl-0 = <&usb2phy_ac_en2_default>;
};
/* Secondary USB port related QMP PHY */
usb_qmp_phy: ssphy@88eb000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x88eb000 0x1000>,
<0x088eb88c 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&pm8150_l5>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&pm8150l_l3>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x08 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
0xffffffff 0xffffffff 0x00>;
qcom,qmp-phy-reg-offset =
<USB3_UNI_PCS_PCS_STATUS1
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_UNI_PCS_POWER_DOWN_CONTROL
USB3_UNI_PCS_SW_RESET
USB3_UNI_PCS_START_CONTROL>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
};
};

261
qcom/sm8150-v2.dtsi
View file

@ -35,3 +35,264 @@
};
#include "msm-arm-smmu-sm8150-v2.dtsi"
&pcie0 {
reg = <0x1c00000 0x4000>,
<0x1c06000 0x1000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x60200000 0x100000>,
<0x60300000 0x3d00000>;
qcom,pcie-phy-ver = <2110>;
qcom,phy-sequence = <0x0840 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xb9 0x0
0x01b8 0x18 0x0
0x01b4 0x94 0x0
0x0050 0x07 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x029c 0x12 0x0
0x0284 0x35 0x0
0x023c 0x11 0x0
0x051c 0x03 0x0
0x0518 0x1c 0x0
0x0524 0x1e 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x05b4 0x04 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x0510 0x17 0x0
0x04d4 0x54 0x0
0x04d8 0x07 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x3b 0x0
0x05a8 0x31 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x3b 0x0
0x0594 0x36 0x0
0x0570 0xff 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0x7f 0x0
0x0580 0x66 0x0
0x04fc 0x00 0x0
0x04f8 0xc0 0x0
0x0460 0x30 0x0
0x0464 0xc0 0x0
0x05bc 0x0c 0x0
0x04dc 0x0d 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x09a4 0x01 0x0
0x0c90 0x00 0x0
0x0c40 0x01 0x0
0x0c48 0x01 0x0
0x0c50 0x00 0x0
0x0cbc 0x00 0x0
0x0ce0 0x58 0x0
0x0048 0x90 0x0
0x0c1c 0xc1 0x0
0x0988 0x88 0x0
0x0998 0x0b 0x0
0x08dc 0x0d 0x0
0x09ec 0x01 0x0
0x0800 0x00 0x0
0x0844 0x03 0x0>;
};
&pcie1 {
reg = <0x1c08000 0x4000>,
<0x1c0e000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>,
<0x40200000 0x100000>,
<0x40300000 0x1fd00000>;
qcom,pcie-phy-ver = <2109>;
qcom,phy-sequence = <0x0a40 0x03 0x0
0x0010 0x00 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0048 0x90 0x0
0x0058 0x0f 0x0
0x0074 0x06 0x0
0x0078 0x06 0x0
0x007c 0x16 0x0
0x0080 0x16 0x0
0x0084 0x36 0x0
0x0088 0x36 0x0
0x0094 0x08 0x0
0x00a4 0x42 0x0
0x00ac 0x0a 0x0
0x00b0 0x1a 0x0
0x00b4 0x14 0x0
0x00b8 0x34 0x0
0x00bc 0x82 0x0
0x00c4 0x68 0x0
0x00cc 0x55 0x0
0x00d0 0x55 0x0
0x00d4 0x03 0x0
0x00d8 0xab 0x0
0x00dc 0xaa 0x0
0x00e0 0x02 0x0
0x010c 0x02 0x0
0x0110 0x24 0x0
0x0118 0xb4 0x0
0x011c 0x03 0x0
0x0154 0x34 0x0
0x0158 0x01 0x0
0x016c 0x08 0x0
0x01ac 0xb9 0x0
0x01b0 0x1e 0x0
0x01b4 0x94 0x0
0x01b8 0x18 0x0
0x01bc 0x11 0x0
0x023c 0x11 0x0
0x0284 0x35 0x0
0x029c 0x12 0x0
0x0304 0x02 0x0
0x0408 0x0c 0x0
0x0414 0x03 0x0
0x0434 0x7f 0x0
0x0444 0x70 0x0
0x0460 0x30 0x0
0x0464 0x00 0x0
0x04d4 0x04 0x0
0x04d8 0x07 0x0
0x04dc 0x0d 0x0
0x04e8 0x00 0x0
0x04ec 0x0e 0x0
0x04f0 0x4a 0x0
0x04f4 0x0f 0x0
0x04f8 0xc0 0x0
0x04fc 0x00 0x0
0x0510 0x17 0x0
0x0518 0x1c 0x0
0x051c 0x03 0x0
0x0524 0x1e 0x0
0x0570 0xff 0x0
0x0574 0xff 0x0
0x0578 0xff 0x0
0x057c 0x7f 0x0
0x0580 0x66 0x0
0x0584 0x24 0x0
0x0588 0xe4 0x0
0x058c 0xec 0x0
0x0590 0x3b 0x0
0x0594 0x36 0x0
0x0598 0xd4 0x0
0x059c 0x54 0x0
0x05a0 0xdb 0x0
0x05a4 0x3b 0x0
0x05a8 0x31 0x0
0x05bc 0x0c 0x0
0x063c 0x11 0x0
0x0684 0x35 0x0
0x069c 0x12 0x0
0x0704 0x20 0x0
0x0808 0x0c 0x0
0x0814 0x03 0x0
0x0834 0x7f 0x0
0x0844 0x70 0x0
0x0860 0x30 0x0
0x0864 0x00 0x0
0x08d4 0x04 0x0
0x08d8 0x07 0x0
0x08dc 0x0d 0x0
0x08e8 0x00 0x0
0x08ec 0x0e 0x0
0x08f0 0x4a 0x0
0x08f4 0x0f 0x0
0x08f8 0xc0 0x0
0x08fc 0x00 0x0
0x0910 0x17 0x0
0x0918 0x1c 0x0
0x091c 0x03 0x0
0x0924 0x1e 0x0
0x0970 0xff 0x0
0x0974 0xff 0x0
0x0978 0xff 0x0
0x097c 0x7f 0x0
0x0980 0x66 0x0
0x0984 0x24 0x0
0x0988 0xe4 0x0
0x098c 0xec 0x0
0x0990 0x3b 0x0
0x0994 0x36 0x0
0x0998 0xd4 0x0
0x099c 0x54 0x0
0x09a0 0xdb 0x0
0x09a4 0x3b 0x0
0x09a8 0x31 0x0
0x09bc 0x0c 0x0
0x0adc 0x05 0x0
0x0b88 0x88 0x0
0x0b98 0x0b 0x0
0x0ba4 0x01 0x0
0x0bec 0x12 0x0
0x0e0c 0x0d 0x0
0x0e14 0x07 0x0
0x0e1c 0xc1 0x0
0x0e40 0x01 0x0
0x0e48 0x01 0x0
0x0e90 0x00 0x0
0x0eb4 0x33 0x0
0x0ebc 0x00 0x0
0x0ee0 0x58 0x0
0x0ea4 0x0f 0x0
0x0a00 0x00 0x0
0x0a44 0x03 0x0>;
};

67
qcom/sm8150.dtsi
View file

@ -29,7 +29,11 @@
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
serial0 = &uart2;
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
pci-domain0 = &pcie0; /* PCIe0 domain */
pci-domain1 = &pcie1; /* PCIe1 domain */
serial0 = &qupv3_se12_2uart;
hsuart0 = &qupv3_se13_4uart;
};
cpus {
@ -1574,6 +1578,63 @@
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x8804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
qcom,restore-after-cx-collapse;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <6>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No vote */
<0 0>, <0 0>,
/* 25 MB/s */
<65360 100000>,<100000 100000>,
/* 50 MB/s */
<130718 200000>,<133320 133320>,
/* 100 MB/s */
<261438 200000>,<150000 150000>,
/* 200 MB/s */
<261438 400000>,<300000 300000>,
/* Max. bandwidth */
<1338562 4096000>,<1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 25000000 50000000 100750000
200000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 201500000>;
status = "disabled";
qos0 {
mask = <0x3f>;
vote = <44>;
};
qos1 {
mask = <0xc0>;
vote = <44>;
};
};
};
&firmware {
@ -1586,7 +1647,9 @@
#include "sm8150-pinctrl.dtsi"
#include "sm8150-regulator.dtsi"
#include "sm8150-pm.dtsi"
#include "sm8150-qupv3.dtsi"
#include "sm8150-slpi-pinctrl.dtsi"
#include "sm8150-ssc-qupv3.dtsi"
#include "sm8150-smp2p.dtsi"
#include "sm8150-gdsc.dtsi"
#include "msm-arm-smmu-sm8150.dtsi"
@ -1745,3 +1808,5 @@
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
status = "ok"
};
#include "sm8150-pcie.dtsi"
#include "sm8150-usb.dtsi"