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power: qpnp-qg: Add the SDAM flash-ocv offset
On PM2250 the PBS sequence expects the battery-OCV to output the right flash-boost output voltage. Provide the same in a SDAM offset. Change-Id: I9d43375d96de5a199c6a87c55e5c1079549b23ee Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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4 changed files with 14 additions and 0 deletions
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@ -128,6 +128,7 @@
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#define QG_SDAM_ESR_DISCHARGE_SF_OFFSET 0x74 /* 2-byte 0x74-0x75 */
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#define QG_SDAM_BATT_AGE_LEVEL_OFFSET 0x76 /* 1-byte 0x76 */
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#define QG_SDAM_MAGIC_OFFSET 0x80 /* 4-byte 0x80-0x83 */
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#define QG_SDAM_FLASH_OCV_OFFSET 0x84 /* 1-byte 0x84 */
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#define QG_SDAM_MAX_OFFSET 0xA4
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/* Below offset is used by PBS */
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@ -91,6 +91,11 @@ static struct qg_sdam_info sdam_info[] = {
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.offset = QG_SDAM_MAGIC_OFFSET,
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.length = 4,
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},
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[SDAM_FLASH_OCV] = {
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.name = "SDAM_FLASH_OCV_OFFSET",
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.offset = QG_SDAM_FLASH_OCV_OFFSET,
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.length = 1,
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},
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};
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int qg_sdam_write(u8 param, u32 data)
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@ -25,6 +25,7 @@ enum qg_sdam_param {
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SDAM_ESR_DISCHARGE_SF,
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SDAM_MAGIC,
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SDAM_BATT_AGE_LEVEL,
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SDAM_FLASH_OCV,
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SDAM_MAX,
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};
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@ -321,6 +321,7 @@ static int qg_store_soc_params(struct qpnp_qg *chip)
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{
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int rc, batt_temp = 0, i;
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unsigned long rtc_sec = 0;
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u32 flash_ocv = 0;
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rc = get_rtc_time(&rtc_sec);
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if (rc < 0)
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@ -340,6 +341,12 @@ static int qg_store_soc_params(struct qpnp_qg *chip)
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i, chip->sdam_data[i]);
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}
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/* store the SDAM OCV */
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flash_ocv = chip->sdam_data[SDAM_OCV_UV] / 20000;
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rc = qg_sdam_write(SDAM_FLASH_OCV, flash_ocv);
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if (rc < 0)
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pr_err("Failed to update flash-ocv rc=%d\n", rc);
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return rc;
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}
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