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clk: qcom: clk-alpha-pll: Update the steps to slew the Lucid PLL

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When PLL HW_UPDATE_LOGIC_BYPASS bit is not set then PLL can be
updated dynamically by setting the PLL_UPDATE bit in mode register
and hardware would clear the PLL_UPDATE automatically when
PLL_ACK_LATCH is asserted.

Change-Id: I1c568c9fdd37a554d71fc5c3d840a71e983baf60
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2021-07-08 09:12:22 +05:30 • committed by Gerrit - the friendly Code Review server
commit fd141c2398
1 changed files with 6 additions and 1 deletions
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7
drivers/clk/qcom/clk-alpha-pll.c
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@ -2895,7 +2895,12 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
/* Wait for 2 reference cycles before checking the ACK bit. */
udelay(1);
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
if (!(regval & ALPHA_PLL_ACK_LATCH)) {
if (!(regval & PLL_UPDATE_BYPASS)) {
ret = wait_for_pll_update(pll);
if (ret)
WARN_CLK(&pll->clkr.hw, 1, "PLL Update clear failed\n");
return ret;
} else if (!(regval & ALPHA_PLL_ACK_LATCH)) {
WARN_CLK(&pll->clkr.hw, 1,
"PLL latch failed. Output may be unstable!\n");
return -EINVAL;