Add and remove headers which are missing and additionally added
to resolve compilation issues.
Change-Id: I2bdc34a33c13f84916d4e7570c579bfc2b1e9c98
Signed-off-by: Venkata Rao Kakani <vkakani@codeaurora.org>
The current register write to DBM_GEN_CFG to update the current speed
is overwriting the entire register. Avoid this, as this also
disables ZLT support on DBM. During validation of QDSS, a QDSS data
stall was seen, as the QDSS BAM generated a ZLT, while DBM did not
enable it. DBM ZLT support is recommended to be enabled in the HPG.
Change-Id: Ieef4a42d3ac6f2a836a5c25530492c95669047b0
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Free QDSS memory on every SSR and allocate it again
when QDSS trace memory indication is received from FW.
Change-Id: I1f4ed9dbfc597407992d2484deaf3767ce0d6c3c
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
Enable QSEECOM,QRNG,smcinvoke config as modules.
Also enable the QTI crpto tz driver config, needed to enable
QTI inline encryption and disable HWKM as this is not
supported on HW.
1.CONFIG_QSEECOM=m
2.CONFIG_HW_RANDOM_MSM_LEGACY=m
3.CONFIG_QCOM_SMCINVOKE=m
4.CONFIG_QTI_CRYPTO_TZ=m.
Change-Id: Ie8730f1ab025d75ecbaf7c6937323e12b9438530
Signed-off-by: Santosh Dronamraju <sdronamr@codeaurora.org>
Some of the SoCs may not have support "rmb_general_purpose" register,
So handle the error path to load the firmware from kernel.
Change-Id: Id64c8e531bb6fe79ea40e6fa34b20aa2e1891ad8
Signed-off-by: Santosh Dronamraju <sdronamr@codeaurora.org>
DWC3 XMIT_DEV command is timing out for USB function wakeup functionality
with current 500 iterations (i.e. timeout comes around 300us). USB DWC3
controller shall take more time to process this particular command. Hence
increase retry count from 500 to 3000 iterations (i.e same as dwc3 endpoint
command timeout value) to have sucessful USB function wakeup functionality.
Change-Id: I1b5a9dd64a01ad9592a04c275beef77eaee523be
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Set parent of touch device so that sysfs path to be
used by TUI App is proper.
Change-Id: Ibb714151a2dcb6789428fdb0a9759a86568cd135
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Some devices which support disable cpu0 can not disable cpu0,
so add psci_cpu_can_disable() function to make all cpus can
disable.
Change-Id: Iaed4129abfc1283c6371bc11bbe5ae4e66317280
Signed-off-by: Teng Fei Fan <tengfei@codeaurora.org>
Add the MIDR part number info for the Arm Cortex-A78.
Change-Id: I0ce8b2d01f95318ce7a2fc4c389a17400f74d36e
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Add the MIDR part number info for the Arm Cortex-A77.
Change-Id: I874c4e94bfe26c0623215b329332536f5dc064ff
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20201028182839.166037-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 8a6b88e66233f5f1779b0a1342aa9dc030dddcd5
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
This patch will enable the PCIe, USB, Storage and Buses
on SM6150 target.
Change-Id: Ic15062dccb3a5f0a6e437432ee7f60dd38f297ba
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
During server arrive icnss driver exchanges qmi
messages with wlan fw. When any qmi message failure is
happening, icnss driver is releasing qmi handle and
registering it. This qmi un-registration is leading to
a server exit event get scheduled. Ideally, when
fw goes down, server exit should come from qmi side.
So, with this change avoid calling qmi handle release
if any qmi message send fail happens.
Change-Id: I003b10f312b071f516bdb135a287d5516f4ab52a
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
