Commit graph

878,439 commits

Author SHA1 Message Date
Raghavendra Rao Ananta
1b9b399796 Revert "pinctrl: msm: Configure interrupts as input and gpio mode"
This reverts commit fe2731211e.

By default the commit muxes the pin to a GPIO upon a request_irq()
call from the client driver. This is incorrect as the client driver
could have muxed the pin already for a different purpose. Hence,
revert this default behavior to not enforce this on the clients.

Change-Id: Ib2500f57cf7e49a7bffd3309801e42166b748db9
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-02-14 16:31:56 -08:00
Merugu Tharun Kumar
1c22c901ac msm: adsprpc: Cache flush operation optimization
Instead of flushing whole buffer use partial cache maintenance apis
to flush only for length user passed. Introducing offset based flush,
when buffers have partial or full overlap, avoiding flush for overlap.

Change-Id: Ifcdcaab112522ee3abf842e9e305665f9a7ddd7e
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Signed-off-by: Merugu Tharun Kumar <mtharu@codeaurora.org>
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
2020-02-14 16:20:51 -08:00
Isaac J. Manjarres
a8663ed475 arm64: defconfig: Enable the mem-buf driver on Lahaina QGKI
Enable the mem-buf driver on Lahaina for QGKI configurations.

Change-Id: I97fd90588130d0b18efba946ece5e72926904e20
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-14 14:17:46 -08:00
Isaac J. Manjarres
60456261ad soc: qcom: mem-buf: Add support for inter-VM memory sharing
Add the initial support required to share memory buffers
between VMs. This driver exposes an interface to userspace
clients to request memory to be allocated from another VM,
and added to the current VM. The VMs communicate with each
other via the use of the hypervisor message queues, as well
as utilize various facilities offered by the Haven resource
manager to manage memory that is transferred from one VM
to another.

Change-Id: I3181a1b14e61db30ed6b86752750722e24fd62e0
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-14 14:17:39 -08:00
Urvashi Agrawal
b3c1aa056e msm: kgsl: Do not mark all buffers as iocoherent
Add a check to mark only cached buffers as iocoherent.
We can't enable io-coherency for uncached buffers because
of situations where hardware might snoop the cpu caches
which can have stale data.This happens primarily due to the
limitations of dma caching APIs available on arm64.

Change-Id: Iafad086d38559139cb45f6a290071ec6d58ad3a3
Signed-off-by: Urvashi Agrawal <urvaagra@codeaurora.org>
2020-02-14 13:48:14 -08:00
Prakruthi Deepak Heragu
b1c1968aa9 arm64: defconfig: Enable CONFIG_PANIC_ON_OOPS
Enable the flag so that kernel panics on oops.

Change-Id: I92378f74edcfa6e6ddd1c72b387c7cf059141e13
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
2020-02-14 12:48:20 -08:00
Raghavendra Rao Ananta
c100d2459f arm64: defconfig: Add LOCALVERSION strings for Lahaina
Add the LOCALVERSION strings for qgki, and qgki-debug
variants of Lahaina platform.

Change-Id: I95af815e9de3b906f6740b10ce4bd41de015b80d
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-02-14 12:03:25 -08:00
Vivek Aknurwar
361f9c82fe clk: qcom: Cache vdd vote if clk is unprepared
When set_rate is called on unprepared clocks new vdd_level
requirement is not cached, which leads to incorrect votes
when later clk_prepare is called. Clocks may not be prepared
when clk pre change rate is called for set_rate change request,
thus cache vdd level and only apply vote during clk prepare.

Change-Id: I54d9a3c75034cd9e67e683c3f71088f2c7cd3db1
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
2020-02-14 11:59:24 -08:00
Raghavendra Rao Ananta
f0804db8e0 arm64: defconfig: Enable QCOM watchdog for Lahaina
Enable QCOM watchdog for Lahaina platform.

Change-Id: I06b1167cfcf355774d09934a521e5eab91bfbe7b
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-02-14 10:44:32 -08:00
qctecmdr
776e6bfb94 Merge "kernel_headers: Fix headers not detected in incremental builds" 2020-02-14 08:25:43 -08:00
qctecmdr
a5984a227e Merge "dma-mapping-fast: Align memory allocation to dma_alloc_attrs expectations" 2020-02-14 08:25:43 -08:00
qctecmdr
97b74a2c32 Merge "defconfig: lahaina: enable FSA driver on Lahaina" 2020-02-14 08:25:43 -08:00
qctecmdr
7d3eb3102b Merge "leds: qti-flash: Add individual APIs to enable and disable switch" 2020-02-14 08:25:42 -08:00
qctecmdr
8af9292135 Merge "msm: adsprpc: Add force no flush and invalidate flag" 2020-02-14 08:25:42 -08:00
qctecmdr
737f2f1603 Merge "msm: adsprpc: Remove remote mappings after PD is up" 2020-02-14 08:25:42 -08:00
qctecmdr
c11ae948db Merge "adsprpc: use uint for counters and maintain consistency in datatypes" 2020-02-14 08:25:41 -08:00
qctecmdr
6ef5c2e0e3 Merge "msm: adsprpc: Add error handling checks" 2020-02-14 08:25:41 -08:00
qctecmdr
b59b6f92d1 Merge "msm: adsprpc: Remove output buffers from cache flush logic" 2020-02-14 08:25:40 -08:00
qctecmdr
4883cd2129 Merge "i3c: i3c-master-msm-geni: Support for 3.4 Mhz,400 Khz" 2020-02-14 04:31:24 -08:00
qctecmdr
d83a937da4 Merge "haven: Add support for MEM_NOTIFY" 2020-02-14 04:31:23 -08:00
qctecmdr
06547e6f05 Merge "sched: Provide stub definitions for WALT" 2020-02-14 04:31:23 -08:00
himta ram
af10871fea radio: RTC6226: fill device capabilities in video_device
The device_caps field must be set for all but subdevs.
Fill rtc6226 device capabilities in video_device.

CRs-Fixed: 2622236
Change-Id: I3645e22dcc2f8d740385f3d661af2603fc594c2f
Signed-off-by: himta ram <hram@codeaurora.org>
2020-02-14 16:06:18 +05:30
Jishnu Prakash
d090ce3098 thermal: adc-tm: Correct a macro expression for PMIC7 ADC_TM
Correct expression in macro ADC_TM_UPPER_MASK. Correct
calculation of value written to ADC_TM measurement enable
register.

Change-Id: I14a6f585bb0cee678aa6eee749ba3e983ba47173
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2020-02-14 15:09:19 +05:30
Tharun Kumar Merugu
2296a3a971 msm: adsprpc: Remove output buffers from cache flush logic
Flush only input buffers during cache maintenance, removing output
buffers from flush logic, helpful when target or buffer is
non-coherent.

Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Change-Id: If84c5bcc0a136d2943ab96c137d0561b8ef8d47d
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2020-02-13 22:01:01 -08:00
Tharun Kumar Merugu
b7d4c9a38a msm: adsprpc: Add error handling checks
Add null pointer check and VERIFY statement for error handling.

Change-Id: Ie51fddd4e279de0246b3b45fe0a947fe5ebb96c3
Acked-by: Maitreyi Gupta <maitreyi@qti.qualcomm.com>
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2020-02-13 21:56:46 -08:00
Tharun Kumar Merugu
668385da4e msm: adsprpc: Add force no flush and invalidate flag
Adding force no flush and invalidate flag for rpcmem_alloc
and respective attributes for remote_register_buf_attr.
Skip flush and invalidate if corresponding flag is set.

Change-Id: I5b872d1f22b082716a1fe715375c66a212fedbac
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2020-02-13 21:50:39 -08:00
Tharun Kumar Merugu
2013a57488 adsprpc: use uint for counters and maintain consistency in datatypes
Use unsigned int for counters and maintain consistency when using
in the datatypes.

Change-Id: Ib4f15d3e0a5971da1beaeb57dc1b827e60c94d0a
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2020-02-13 21:46:31 -08:00
Tharun Kumar Merugu
95aed7d580 msm: adsprpc: Remove remote mappings after PD is up
Currently before staticPD on QDSP is up, remote mappings are
being removed. Instead, remove the mappings after staticPD is up.

Change-Id: I10a37b4c840dbd830f7b8897aabbf8681329b74c
Acked-by: Vishnu Karthik D <vikarthi@qti.qualcomm.com>
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2020-02-13 21:37:27 -08:00
qctecmdr
0a928fdb82 Merge "leds: qti-flash: Update interrupt names" 2020-02-13 21:01:40 -08:00
qctecmdr
f460c8c173 Merge "arm64: defconfig: Enable QCOM EUD driver" 2020-02-13 21:01:39 -08:00
qctecmdr
6cf8d75aca Merge "coresight-etm4x: Don't set LPOVERRIDE bit when tupwr-disable is true" 2020-02-13 21:01:39 -08:00
qctecmdr
efe21f4215 Merge "msm: kgsl: Always boot GMU with default CM3 config" 2020-02-13 21:01:39 -08:00
qctecmdr
b63310f0cf Merge "usb: ep0: complete the pending control request before soft-disconnect" 2020-02-13 21:01:38 -08:00
qctecmdr
460b75a424 Merge "sound: usb: Add snapshot for usb audio qmi driver" 2020-02-13 21:01:38 -08:00
qctecmdr
c457c4b2b7 Merge "msm: kgsl: Add rgmu_init() for firmware loading" 2020-02-13 21:01:38 -08:00
qctecmdr
b074d379c5 Merge "ASoC: Update the widgets power up/down sequence" 2020-02-13 21:01:38 -08:00
qctecmdr
6b986520ed Merge "msm: cvp: Enable CVP auto PIL" 2020-02-13 21:01:37 -08:00
qctecmdr
bf0c0917a2 Merge "ion: msm: Add support for secure allocations for the Trusted UI(TUI) VMID" 2020-02-13 21:01:37 -08:00
qctecmdr
3d240c26b7 Merge "haven: Add the memparcel handle as a well known haven type" 2020-02-13 21:01:37 -08:00
qctecmdr
9eadcfc557 Merge "drivers: firmware: psci: Register with kernel restart handler" 2020-02-13 21:01:36 -08:00
Vivek Aknurwar
900c6f9885 clk: qcom: gcc-lahaina: Enable gpu_memnoc_gfx and gpu_snoc_dvm_gfx always
SMMU hw voting did not tie these 2 clocks. Although these
clocks are default enabled on boot, SW needs to explicitly
make sure to keep them always enabled to keep smmu access.
These clks will automatically turn on/off along with
CX_GDSC so no power hit.

Change-Id: I4fb82589f63c0a321465e249e54f94be7e5449a3
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
2020-02-13 20:50:35 -08:00
qctecmdr
453686cea6 Merge "crypto: msm: Rename qcrypto module" 2020-02-13 20:44:10 -08:00
Ruofei Ma
b55702b148 msm: cvp: buffer managerment optimization for Lahaina
Implemented a more efficient way of managering buffers in cvp driver
to help improve performance.

Change-Id: Ic6f9bc1bae74fc8daefdf55275239e4e6d334199
Signed-off-by: Ruofei Ma <ruofeim@codeaurora.org>
2020-02-13 19:01:14 -08:00
Prakruthi Deepak Heragu
9b5a973855 soc: qcom: Add forever loop after non-secure bite configuration
The core which induces the non-secure bite should not
proceed further. Non-secure bite is a secure interrupt
and one of the core handles and that may not be the same
core which configured the watchdog. Add forever loop
after non-secure bit programming, so that core do not
proceed further.

Change-Id: I5523ad00d47755df6eed2bfb9210b585ee22f4ed
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
2020-02-13 18:44:40 -08:00
Meng Wang
52846c3d83 defconfig: lahaina: enable FSA driver on Lahaina
Enable FSA driver on Lahaina to support analog type-c
headset.

Change-Id: Ia95383641030c9ff56300c975ffd35a96abcdac5
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-02-14 08:44:07 +08:00
Satya Durga Srinivasu Prabhala
f1214c569a sched: Provide stub definitions for WALT
When WALT and CFI are enabled, weak symbols which points to NULL
are causing issues like global structures becoming NULL due to
compiler/linker treatment of these symbols.

Provide proper stub definition for all such weak symbols to avoid
issues until compiler/linker gets fixed.

Change-Id: I3dce047393521681e663a0ad254b07e9769e0265
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-02-13 16:42:34 -08:00
Isaac J. Manjarres
aa7f44e9e2 haven: Add support for MEM_NOTIFY
MEM_NOTIFY is useful for sending VMs notifications about
memory that has been shared with them, as well as sending
owners of memory an indication that a VM has released memory
that they own, so add support for it.

Change-Id: I65bf0d000c8b3850f04c85eec70692728314b26d
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-13 16:26:18 -08:00
Isaac J. Manjarres
831fa9b6df haven: Add support for MEM_SHARE/MEM_LEND
Relying on hyp_assign for sharing memory is not sufficient,
as there are certain cases where hyp_assign is not applicable
for sharing memory (e.g. I/O memory). Add support for the MEM_SHARE
and MEM_LEND operations for sharing/lending memory with other
VMs respectively.

Change-Id: I7de502385a045f073540fa30c164b3410f6b5bd0
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-13 16:26:18 -08:00
Isaac J. Manjarres
ef8e696420 haven: Add support for the MEM_ACCEPT call
The MEM_ACCEPT call is required for VMs to map the
memory represented by a handle into their RM managed
page-tables, so add support for it.

Change-Id: I669ebd8298af405ca586a5721b26c4e19ffe39aa
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-13 16:26:18 -08:00
Isaac J. Manjarres
fbfc1adc6f haven: Add support for the MEM_RELEASE/MEM_RECLAIM calls
The MEM_RELEASE/MEM_RECLAIM RM calls are required to unmap memory
from the RM managed page-tables of VMs, as well as for VMs that
own memory to reclaim it respectively, so add support for it.

Change-Id: I6b8025cb08067331deb9cc89ec1d36c94c959c59
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-02-13 16:26:18 -08:00