[ Upstream commit cb11ea56f37a36288cdd0a4799a983ee3aa437dd ]
DWC3 must not issue CLEAR_STALL command to control endpoints. The
controller automatically clears the STALL when it receives the SETUP
token. Also, when the driver receives ClearFeature(halt_ep), DWC3 must
stop any active transfer from the endpoint and give back all the
requests to the function drivers.
Change-Id: Iccf1e148c74bbe194702e3e7a620f0fef5a9b183
Fixes: 72246da40f ("usb: Introduce DesignWare USB3 DRD Driver")
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Git-commit: 1bfa091472
Git-repo: https://android.googlesource.com/kernel/common/
Signed-off-by: Srinivasarao P <spathi@codeaurora.org>
Remove all the leading and trailing whitespaces in the string copied
from userspace.
Change-Id: I627416dcdb1155303ad6a8ed172910a8653dd67b
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
On certain platforms, due to a HW issue, the SSPHY keeps
transitioning in and out of p3 whenever we perform any HS
transfers. This leads to a storm of PWR_EVNT irgs.
Fix this by disabling SSPHY autosuspend on such platforms.
Autosuspend will be enabled as part of dwc3_msm_prepare_suspend
so that SSPHY gets a chance to go into P3.
Change-Id: I4e674f780a72a8c4abcb3e6c9f083f23b1faa196
Signed-off-by: Aniket Randive <arandive@codeaurora.org>
In line with the sequence for primary port, update proper fields
of DWC3_GUSB2PHYCFG and DWC3_GUSB3PIPECTL registers for the
second port of the dual port controller. Update other registers
as required.
While at it, also avoid enabling SSPHY autosuspend if
dis_u3_susphy_quirk is set.
Change-Id: Ib79dba4c6d854fa2bf33a1b7cecf06f988250662
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
Certain targets may have a dual port capable host controller.
Add support for the PHY IRQs for the second port. Since the SSPHY
autosuspend will be disabled for such controllers, remove the
support of pwr_evnt_irq as a mandatory IRQ and allow SSPHY to go
into P3 as a part of suspend sequence. Handle the logic
gracefully to maintain single port controllers.
Change-Id: I5a53d6e23f64bec7ae940d23923df310309a28da
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
Add 2 new PHY instances (HS and SS) in dwc3 and dwc3-msm
structures. Probe and initialize them when the controller is
dual port capable. This capability is advertised by cores
supporting only host mode using the DT flag 'qcom,dual-port'.
Update PHY1 flags wherever applicable while maintaining single
port controller support.
Avoid workaround of SSPHY powerdown as a part of HS device
connect because of the known HW issue of the other SSPHY going in
and out of P3 when data transfers are being done.
Change-Id: If52fd6383cc2da8b763c774d2ad688448f90aea0
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
Enable TLMM pincontrol as module for Direwolf target.
Change-Id: I5a82c4ea55b8f34b931cb45eab81927924052521
Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Add initial driver to support pin configuration with
pinctrl framework for Direwolf SoC.
Change-Id: I7fd92e716eec71fc0cbdced54902f2ddfadedcc0
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Add snapshot of vm power off driver as of msm-4.14
'commit 77a20e0a50e1
("power: reset: cache flush before VM restart")'.
Change-Id: I380b16f46429711284bb6717847a1eef5d8ee9b1
Signed-off-by: Ping Jiang <scottjiang@codeaurora.org>
In this case, CONFIG_SMP and CONFIG_LPAE are both not enabled,
CONFIG_ENABLE_VMALLOC_SAVING is enabled. The paddr|size|addr
satisfies PMD_SIZE alignment, will create section mapping not
page mapping, non-LPAE arm32 uses 2-level page table, including
pgd and pte, before remapping it will do unmapping which clears
init_mm->pgd of corresponding addr and memcpy into [VMALLOC_START,
VMALLOC_END) part of current->active_mm->pgd, but this memcpy misses
to sync other vmalloc areas outside [VMALLC_START, VMALLOC_END) with
vmalloc saving feature, the pgd part of addr in other vmalloc
areas is not synced and still holds the stale mappings, if request
addrs fall into other vmalloc areas, then page fault happens for them.
So need to consider other vmalloc areas outside [VMALLOC_START,
VMALLOC_END) with vmalloc saving feature, change into [PAGE_OFFSET,
VMALLOC_END) to include all vmalloc areas, then all pgds of vmalloc
addrs in current->active_mm->pgd will be synced on unmapping, the
pgds of request addrs are cleared, then do_traslation_fault will
be called for zero pgd value, it calls copy_pmd to sync the pgds
from init_mm->pgd to current->active_mm->pgd for request addrs on
remapping.
Change-Id: Ia283d409a20c8fc9951434078332a3badf0f9ed0
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
Add ebi2 support to GPIO 89 and 90 and add an ebi2_a function.
Change-Id: I1854aea3011b1d1cf67ebfebddb1c6b60a34a1b1
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
QCA6390 requires synchronization between BT and WLAN enable gpio
to avoid power up issue. Add support for QCA6390 in gpio sync
code.
Change-Id: Id2183ff324c9c3059ea81e9137fa49c803feb183
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, etc.
Change-Id: I7a3c4494b5c2e6545821491e1aee8bf6c4ac3345
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, HMP, etc.
Change-Id: I0b4efd6e2127771be65c754fa35770ba359576bd
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Build the qcom_edac driver as a module. This is to load the driver
as a first stage module, which is needed in order to bypass a build
system limitation.
Change-Id: I14abd0dac5c018ef6d9366711b80c34e1af12bf4
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add support for Micrel PHY interrupt.
This is required to support Micrel PHY on stmmac driver.
Change-Id: Ic49924199a0e1d2dd95ae3335c079e3d230bc201
Acked-by: Nagarjuna Chaganti <nchagant@qti.qualcomm.com>
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
Currently only one argument is being passed in scm_call to update
LVL_SHIFTER register, but tz side expects two arguments to be
passed. This is leading to scm call failure. So fix this by adding
another argument and initializing it to zero which has no operation
to perform.
Change-Id: Ibe5b4a1635d58102b747926db65677251186ccba
Signed-off-by: Rohith Kollalsi <rkollals@codeaurora.org>
