Configure the IPCC summary IRQ as wakeup capable interrupt.
IPCC interrupt needs to wake up the device from low power
modes when wakeup capable event is generated from remote
subsystem.
Change-Id: Iaffefc6ef68743c7de11062c39e2b1453c58b9a1
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
[eberman@codeaurora.org: Resolve merge conflicts]
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
Add check of trace unit power property to enable/disable that
keep the trace unit powered.
Change-Id: I66dbfee16df63480c9309092e61ee39b8b0cd6e8
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
For RSCs that have sleep & wake TCS but no dedicated active TCS, wake
TCS can be re-purposed to send active requests. Once the active requests
are sent and response is received, the active mode configuration needs
to be cleared so that controller can use wake TCS for sending wake
requests in 'solver' state while executing low power modes.
Change-Id: I0d15c290db48d08158fdbff2cd91505563dc3fd5
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
When triggering a TCS to send its contents, reading back the trigger
value may return an incorrect value. That is because, writing the
trigger may raise an interrupt which could be handled immediately and
the trigger value could be reset in the interrupt handler.
A write_tcs_reg_sync() would read back the value that is written and try
to match it to the value written to ensure that the value is written,
but if that value is different, we are stuck in loop forever.
Change-Id: I54866b9b9d85fa79c8df84aecd502764b9f9158a
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Add new RCG clock ops specific for the DP clock source.
Change-Id: I2ec5ddcfd47af8362f76d76d153e30d4e2f45370
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some RCGs could have sources with dynamic frequencies and fixed sources
where if the RCG has the flag of CLK_SET_RATE_PARENT set, it would try to
propagate the clock rate to the fixed source PLLs too. To identify sources
of the RCGs where the rate should propagate to parent PLL, add a member in
freq_tbl to represent source frequency. This would be used by the
_freq_tbl_determine_rate to set its parent frequency on the PLL.
Change-Id: I7f1c0d9d84607821893a1e5d17934dae5acef5f4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, it is desirable for an RCG to be turned on
explicitly instead of just relying on the enable signal from
its branch clock(s). Add support for this.
Change-Id: I2b0b81bddfe7cc7543c313e4ed13a332fb1a0fcb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, an RCG might be prone to being enabled even
though the overlying software thinks that it disabled the RCG.
In order to avoid letting the RCG go into an invalid state, support
parking it at a safe frequency during clk_disable() and deferring
all the RCG configuration updates to be done during clk_enable(),
if a scaling request comes in whilst the clock is disabled.
Change-Id: I55f1d1d346182a2b480127c57d6659fc9a63331b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The sequence for alpha_pll_lucid_prepare is checking an incorrect bit
to determine whether or not a lucid PLL has calibrated successfully.
The bit in the status register is not observable unless pll_test_ctl[69]
is set and user_ctl[43:37] is 0 which should only be used as a fallback
option. Use the correct PCAL_DONE bit from the mode register to properly
determine PLL calibration status.
Change-Id: If952c30cacacd68c07e8d7dfd622069dbb70c909
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some instances of the Zonda PLL do not lock correctly
in high L-VAL regions. In such cases, CFA mode
can be configured via test_ctl_val to use an alternative
locking mechanism. Add support for CFA mode by
polling FREQ_LOCK_DET instead of PLL_DET_LOCK
whenever CFA mode has been configured.
Change-Id: Ief31592250ea9f329a34ffdbc4b17cfce431677d
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
There are different configurations of display panels which may
or may not enable display PLLs before the display driver probes. Due to
continuous splash use cases, we may trample over existing PLL
configuration and cause the PLL to reset while it's in use. Prevent that
scenario by skipping the PLL configuration step if it's enabled.
Change-Id: I61f69c67ca57f18cbc6b551884ea199212ed4e9d
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Under some circumstances, such as during subsystem restart, the
registers for a clock controller may be reset to hardware default
values. Add support to reconfigure a Lucid PLL during clk_prepare
in the case that the CAL_L_VAL is found to be 0 before performing
calibration.
Change-Id: Idef3c42dfb32748ec40f89a9dab9f6ab86e293f6
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for configuring custom target-specific registers
during PLL initialization.
Change-Id: Id296ae904d1b74e7c2f90027bd557bdc62b1d362
Signed-off-by: David Collins <collinsd@codeaurora.org>
Remove reconfiguration of PLLs as configuration is expected
to be one time that is during probe.
Change-Id: I90f8ed553016ab32786beae0873424579ead564d
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Zonda PLL is high frequency PLL clock generator. It supports
fine control of the digital controlled oscillator (DCO)
and clocked on rising edge of the reference.
Change-Id: I2a9726a0acbffcee1a52f5172b197bf125e60030
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support to configure test_ctl, user_ctl and cal_l fields for PLLs.
Change-Id: Ib5a7a74aecd8d9885e0a3034f097c13cda4d2268
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Add programming sequence support for managing the Lucid
PLLs.
Change-Id: Ia63067d88bd1f309d190b1ec5b0f272b40209a71
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
While rmnet_data driver itself is not required, some of the
definitions are used by modules such as mhi and ipa.
Change-Id: I892c2ff51819262632769b3da32a1c2adf6b3543
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
SLPI (sensor low power island) uses Qualcomm Technologies, Inc
Digital Signal Processor for all sensors connected via SPI/I2C.
Firmware is required to be loaded to enable these sensors and
algorithms to execute on DSP. This change adds driver to load
the firmware.
This snapshot is taken as of msm-4.19 'commit
<db92782eadcfd7e8186f6f7487194ebbf8c31c19> (Merge "icnss:
Reduce the shutdown timeout from 50sec to 15sec")'.
In addition change copyrights, type and description in KConfig
and directory change from sensors to soc/qcom.
Change-Id: I15350924e7febe287dc9d7e21885b2e11426a2cc
Signed-off-by: Jun-Hyung Kwon <junhyung@codeaurora.org>
Enable RSC controller driver to be compiled as modules. Since RPMH
communication is need for enabling/disabling critical clocks and busses
needed for the application processor, it is better to keep this module
enabled. Hence declare the driver as a builtin platform driver.
Change-Id: I41a657c0d618efb7c3460833ffb8eb5d445885a0
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Add support to dump command DB data via debugfs. This allows drivers to
lookup data resource information without a resource ID.
Updated to use leXX_to_cpu() functions when reading cmdDB memory.
Change-Id: I04e7466f76ceea00d762752e0c0123edfabe0f64
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
llcc supports 2 memory controllers in backend on certain systems.
This patch adds support for dual memory controllers. Also fixed
filter related changes in LLCC. Cleaned up the code for better
code walk.
Change-Id: Ie054d9182b20ec0811f117c2289aa857f0384baf
Signed-off-by: Avinash Philip <avinashp@codeaurora.org>
This is snapshot of the llcc_perfmon driver from msm-4.14
'commit c9961d61d6d8 ("drivers: soc: llcc_perfmon: Add llcc_perfmon
support")'
This LLCC perfmon driver provides Sysfs interfaces for the clients to
monitor the events. Driver support for monitor events from LLCC sub blocks.
Also updated driver to handle opcode & cache alloc filters.
Change-Id: Ic711fdbc774d2da1938feff5c0d7888e5cf8495a
Signed-off-by: Sankaran Nampoothiri <snampoot@codeaurora.org>
Signed-off-by: Avinash Philip <avinashp@codeaurora.org>
This is a snapshot of cnss_prealloc driver and associated files as of
msm-4.19 commit 94d53f998edd
("cnss_prealloc: Update prealloc memory table").
Change-Id: Ic6e853bf651e2a0e2b672bc68d42929c3b55ef93
CRs-Fixed: 2500800
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
