Commit graph

892,285 commits

Author SHA1 Message Date
qctecmdr
2f8aed210e Merge "msm: msm-geni-se: Add proxy votes to fix earlycon crash" 2020-11-17 17:05:47 -08:00
qctecmdr
49b2e4a13c Merge "f_fs: fix scheduling while atomic issue of ffs_epfile_io()" 2020-11-17 13:29:01 -08:00
qctecmdr
55b65a4d60 Merge "defconfig: sdxlemur: Allow writing to regmap only on debug builds" 2020-11-17 13:29:01 -08:00
qctecmdr
4c48eb3326 Merge "icnss2: Avoid sending qdss_trace_mem_info to fw if it is down" 2020-11-17 13:29:00 -08:00
qctecmdr
003a1824ff Merge "msm: kgsl: Properly set fault bit in adreno_set_gpu_fault" 2020-11-17 13:29:00 -08:00
qctecmdr
2129bf638c Merge "cfg80211: Add support to calculate and report 4096-QAM HE rates" 2020-11-17 13:29:00 -08:00
qctecmdr
f6b4905d47 Merge "input: touchscreen: mxt: remove disable_irq" 2020-11-17 13:28:59 -08:00
qctecmdr
9a71644291 Merge "i2c: i2c-msm-geni: Wait for abort command completion" 2020-11-17 13:28:59 -08:00
qctecmdr
e915fc5948 Merge "msm: kgsl: Add a Kconfig setting for GPU idle timeout" 2020-11-17 05:57:29 -08:00
qctecmdr
c496ba6c04 Merge "arm: defconfig: Enable QRTR MHI for sdxlemur" 2020-11-17 05:57:29 -08:00
qctecmdr
fee2b06454 Merge "icc: dt-bindings: add endpoint IDs for interconnects for SM8150" 2020-11-17 05:57:29 -08:00
qctecmdr
704966b60e Merge "cnss2: Avoid suspending PCIe after QMI send get is called" 2020-11-17 05:57:29 -08:00
qctecmdr
e2f18ef14c Merge "defconfig: Enable relay fs for lahaina" 2020-11-17 05:57:28 -08:00
qctecmdr
75d5a41f25 Merge "usb: misc: nb7vpq904m: disable chip when boot up without cable" 2020-11-17 05:57:28 -08:00
qctecmdr
8c62bda756 Merge "msm: pcie: correct PCIe target link speed mask macro" 2020-11-17 05:57:28 -08:00
qctecmdr
bba465d5c1 Merge "Add support for EMMC storage type" 2020-11-17 05:57:27 -08:00
qctecmdr
5f551b3328 Merge "Kconfig: have ENABLE_VMALLOC_SAVING depend on QGKI" 2020-11-16 19:15:08 -08:00
qctecmdr
4104c0f498 Merge "input: touchscreen: focaltech: toggle reset gpio during error" 2020-11-16 19:15:08 -08:00
qctecmdr
8b249d7cb9 Merge "Merge android11-5.4.61+ (dc2d5a0) into msm-5.4" 2020-11-16 19:15:08 -08:00
Guru Das Srinagesh
6c3524dd68 defconfig: sdxlemur: Allow writing to regmap only on debug builds
For security reasons, allow modifying register values via the regmap
debugfs interface only on debug builds.

Change-Id: Ie22dbb2ff72da2072d46ab1116fb9623fe2185ff
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
2020-11-16 09:07:35 -08:00
Veera Vegivada
48bfd0d68c icc: dt-bindings: add endpoint IDs for interconnects for SM8150
Add master and slave ID constants for all Qualcomm Technologies, Inc.
SM8150 interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: Ie3d92159bf34e2cd57873cd3cd85c75e6a62638a
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-11-16 11:45:30 +05:30
Vamsi Krishna
5301754193 cfg80211: Add support to calculate and report 4096-QAM HE rates
Drivers supporting 4096-QAM rates as a vendor extension in HE mode need
to update the correct rate info to userspace while using 4096-QAM (MCS12
and MCS13) in HE mode. Add support to calculate bitrates of HE-MCS12 and
HE-MCS13 which represent the 4096-QAM modulation schemes. The MCS12 and
MCS13 bitrates are defined in IEEE P802.11be/D0.1.

In addition, scale up the bitrates by 3*2048 in order to accommodate
calculations for the new MCS12 and MCS13 rates without losing fraction
values.

CRs-Fixed: 2796770
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
Signed-off-by: Jouni Malinen <jouni@codeaurora.org>
Link: https://lore.kernel.org/r/20201029183457.7005-1-jouni@codeaurora.org
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: 9c97c88d2f4b221d99491c3196da42004c195fb5
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
Change-Id: I44f71f40a57b57703bbbe138e690d6f92369d0ec
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
2020-11-16 11:08:52 +05:30
qctecmdr
58329ca148 Merge "clk: qcom: Add the debug mux information for SM8150" 2020-11-15 17:44:56 -08:00
qctecmdr
b8bfad925d Merge "exfat: add super block operations" 2020-11-15 08:04:36 -08:00
qctecmdr
5869c90e4f Merge "soc: qcom: qmi_interface: Parse all control packets" 2020-11-15 08:04:35 -08:00
qctecmdr
3de3dfe933 Merge "net: neuron: channel: Check buffer boundaries" 2020-11-15 08:04:35 -08:00
qctecmdr
174db10e47 Merge "arm: qcom: Add initial platform for Monaco and Scuba" 2020-11-15 04:36:26 -08:00
qctecmdr
5ca720a4d8 Merge "power: supply: qcom: Add module dependency on TYPEC" 2020-11-15 04:36:25 -08:00
qctecmdr
aad412cb4f Merge "soc: qcom: minidump: Change the way to locate log_buf" 2020-11-15 04:36:25 -08:00
qctecmdr
1843c1a799 Merge "staging: exfat: remove staging version of exfat filesystem" 2020-11-15 04:36:25 -08:00
qctecmdr
f94ed13be9 Merge "exfat: add in-memory and on-disk structures and headers" 2020-11-15 04:36:25 -08:00
qctecmdr
7f23279eb1 Merge "dt-bindings: iio: Add scale function for PM2250 S3 die temp" 2020-11-15 01:08:07 -08:00
qctecmdr
8ff49d4085 Merge "defconfig: Enable required defconfigs for sdxlemur target" 2020-11-15 01:08:06 -08:00
qctecmdr
1bee375fee Merge "clk: qcom: lahaina: Fix providers left active in suspend" 2020-11-15 01:08:06 -08:00
qctecmdr
a4b6932845 Merge "input: touchscreen: st: cancel pending firmware update" 2020-11-15 01:08:05 -08:00
qctecmdr
d35e872fd1 Merge "clk: qcom: alpha-pll: Export required symbols from alpla-pll" 2020-11-14 21:07:20 -08:00
qctecmdr
b7a4fe5073 Merge "pci: msm: Move rpmsg lock after command completion" 2020-11-14 17:35:49 -08:00
qctecmdr
723156f03e Merge "mhi: uci: Add channel mutex lock for read and write file ops" 2020-11-14 17:35:48 -08:00
qctecmdr
04dd99b363 Merge "icnss2: Avoid sending modem shutdown indication to fw if it is down" 2020-11-14 17:35:48 -08:00
qctecmdr
17b81f1df7 Merge "msm: pcie: switch API for tuning EQ preset request vector configuration" 2020-11-14 17:35:47 -08:00
qctecmdr
da9ad9f15c Merge "msm: ipa_fwmk: Provide api for mhi driver to update state" 2020-11-14 17:35:46 -08:00
Wu Gao
e0e474a32e defconfig: Enable relay fs for lahaina
Required to enable CFR on lahaina, and CFR is based on relay file
system. So add the configure to enable relay fs.

Change-Id: Ic62be9a54a3ea38e9f8831ae7472390d6490f680
Signed-off-by: Wu Gao <wugao@codeaurora.org>
2020-11-14 21:33:58 +08:00
qctecmdr
761f457a49 Merge "soc: qcom: smp2p: Add memory barrier for irq_pending" 2020-11-14 01:35:45 -08:00
qctecmdr
a5b3c5962b Merge "power: qpnp-smb5: Update legacy cable detection logic in bootup" 2020-11-14 01:35:45 -08:00
qctecmdr
b28b8c7ed2 Merge "mmc: core: Enable force hw reset" 2020-11-14 01:35:44 -08:00
qctecmdr
5a842fda18 Merge "cfg80211: reg: Reset to upstream" 2020-11-14 01:35:44 -08:00
qctecmdr
9dd8c088c1 Merge "msm: kgsl: Increase GMU log size to 16 KB" 2020-11-14 01:35:44 -08:00
qctecmdr
5dcc7b616a Merge "mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk" 2020-11-14 01:35:44 -08:00
Vaibhav Agrawal
57ff131901 Add support for EMMC storage type
Add support for parsing EMMC specific address for hwkm
slave in cqhci crypto driver. Add similar support
in ufs crypto driver as well to get UFS specific address.
Remove support for parsing the hwkm slave address from dtsi
node from hwkm driver as it will be received as part of
hwkm_init(). Enable/disable cqhci crypto from cqhci_enable and
cqhci_disable instead of __cqhci_enable and __cqhci_disable.

Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
   multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.
6. Bootup wth qgki compiled build.
7. Bootup on holi and shima UFS device.
8. Setting encryption policy and read/write of data over multiple
   reboots, using fscryptctl tool.

Change-Id: I1f437ebf8a3f4cd008027d708ccacc02dfb14d07
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
2020-11-13 23:36:21 -08:00
Chris Lew
7f227a2cb2 arm: defconfig: Enable QRTR MHI for sdxlemur
Enable QMI communication to external chipsets with the QRTR MHI
transport driver.

Change-Id: Ia00917c75dd360afa387742ed9851ec66de6c667
Signed-off-by: Chris Lew <clew@codeaurora.org>
2020-11-13 10:33:53 -08:00