Commit graph

876,238 commits

Author SHA1 Message Date
qctecmdr
321ba0dbe8 Merge "msm: ipa: fix ipa_disable_apps_wan_cons_deaggr declaration" 2020-01-07 02:59:26 -08:00
qctecmdr
219108d0e3 Merge "msm: ipa3: IPA clock vote ioctl" 2020-01-07 02:11:20 -08:00
qctecmdr
c6ee0e7602 Merge "arm64: defconfig: Enable slimbus driver config for lahaina" 2020-01-07 01:33:51 -08:00
qctecmdr
1070f3fe7d Merge "defconfig: lahaina: Enable ADC drivers for lahaina" 2020-01-07 00:52:13 -08:00
qctecmdr
427a09ef8d Merge "arm64: defconfig: Enable all memory hotplug related configs on Lahaina" 2020-01-06 23:58:07 -08:00
qctecmdr
90c477596b Merge "msm: ipa3: IPA clock vote ioctl" 2020-01-06 23:22:09 -08:00
qctecmdr
00e3b2aa32 Merge "coresight: tmc: etr: Add sys interface for ETR" 2020-01-06 21:16:11 -08:00
qctecmdr
dbda2794b3 Merge "msm: cvp: remove additional checks in response_handler" 2020-01-06 20:39:03 -08:00
qctecmdr
33a38d88b2 Merge "thermal: adc-tm: Add support for PMIC7 ADC_TM" 2020-01-06 20:00:20 -08:00
qctecmdr
68af8c2603 Merge "thermal: adc-tm: Add ADC_TM driver snapshot" 2020-01-06 19:18:35 -08:00
qctecmdr
f305d3b58f Merge "arm64: defconfig: Enable WALT for Lahaina" 2020-01-06 17:44:01 -08:00
Jia Ding
35a816d085 msm: ipa: fix ipa_disable_apps_wan_cons_deaggr declaration
ipa_disable_apps_wan_cons_deaggr() has different declarations when
CONFIG_IPA or CONFIG_IPA3 are not set. Thus fix the declaration to
align with CONFIG_IPA or CONFIG_IPA3 enabled one.

Change-Id: Ic09cac2484c9cfbcd0833583c05c6fc19a3c2aed
Signed-off-by: Jia Ding <jiad@codeaurora.org>
2020-01-06 13:34:53 -08:00
Perry Randise
4183cb329b msm: ipa3: IPA clock vote ioctl
The ability to vote IPA clock from user space is now required.  Given
this, voting for IPA clock can now be done via an ioctl. These changes
implement the ioctl.

Change-Id: Id7e02678e96da98f2a17f35e7f6736fba39ca990
CRs-Fixed: 2592003
Signed-off-by: Perry Randise <prandise@codeaurora.org>
2020-01-06 11:25:01 -05:00
qctecmdr
90ae165d38 Merge "msm: IPA: add the missing iounmap handle" 2020-01-06 07:34:15 -08:00
Perry Randise
6674562cc7 msm: ipa3: IPA clock vote ioctl
The ability to vote IPA clock from user space is now required. Given
this, voting for IPA clock can now be done via an ioctl. This header
file supports the ioctl and can be independently propagated.

Change-Id: I742a7950f9fc53f17cb6f210f2b7f06ade842011
CRs-Fixed: 2592003
Signed-off-by: Perry Randise <prandise@codeaurora.org>
2020-01-06 05:34:25 -08:00
qctecmdr
f7a35f03cb Merge "soc: qcom: mem-offline: Clear page-table entries after offline" 2020-01-06 03:42:34 -08:00
qctecmdr
a526f6ca07 Merge "soc: qcom: mem-offline: Set offlinable region based on minimum DDR sizes" 2020-01-06 01:09:30 -08:00
qctecmdr
7ffd447954 Merge "arm64: Update dram end address while randomizing base" 2020-01-06 00:24:54 -08:00
qctecmdr
81fcfc47cc Merge "arm64: mm/memblock: Update memory limit calculation" 2020-01-05 23:45:49 -08:00
qctecmdr
884823fbcf Merge "drivers: base: expose amount allocated per block" 2020-01-05 23:03:11 -08:00
Prudhvi Yarlagadda
ec5bc759f3 arm64: defconfig: Enable slimbus driver config for lahaina
Enable slimbus driver config for lahaina defconfig.

Change-Id: I22674ec93618ca7bf8d6de83d6cab2a2c7d2f29e
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
2020-01-06 12:00:37 +05:30
qctecmdr
51cdd0125f Merge "msm: ipa3: Fix to avoid memory out of bound access error" 2020-01-05 22:25:54 -08:00
suchawla
833bd8ca3c msm: cvp: remove additional checks in response_handler
possibility of OOB access on device->response_pkt in
__response_handler. for e.x if msg queue contains 1000
messages and all 1000 were read and queue is empty.
So __get_q_size api will return zero and _iface_msgq_read
will go in an infinite loop, even if packet_count
== max_packets.

Change-Id: I8e64ff70d5bcefb52d66bfea121f3febf4728384
Signed-off-by: suchawla <suchawla@codeaurora.org>
2020-01-05 22:16:50 -08:00
Jishnu Prakash
c1bad8b6d6 defconfig: lahaina: Enable ADC drivers for lahaina
Enable VADC and ADC_TM drivers for Lahaina.

Change-Id: I4d17fc113abcdcde2242befaa5fb0dd2fa8dcae1
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2020-01-06 09:42:30 +05:30
Mulu He
f45c086b44 coresight: tmc: etr: Add sys interface for ETR
Add usb streaming support to collect trace data externally.
Add support to enable USB mode for coresight devices.
Set memory as the default mode on ETR.

Change-Id: I3bd2bd92c676ff79a3ae5a045a54e7d1e867543d
Signed-off-by: Mulu He <muluhe@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingweiz@qti.qualcomm.com>
2020-01-06 10:40:58 +08:00
Jishnu Prakash
72f81217bf thermal: adc-tm: Add support for PMIC7 ADC_TM
Add support for PMIC7 ADC_TM peripheral in ADC_TM common driver files.
Add main ADC_TM driver file for PMIC7. As register offsets and SW flows
have changed significantly for ADC_TM due to ADC architecture change,
this new driver is required for ADC_TM on PMIC7.

Change-Id: I9c92ab0a93a1bf487cb9fa0e9640b3c4eaf2b21a
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2020-01-04 20:49:36 -08:00
Jishnu Prakash
8ba2de1121 thermal: adc-tm: Add ADC_TM driver snapshot
ADC_TM peripheral is used by client to set thresholds on channels
supported by VADC and send notification once set thresholds are
crossed. The driver registers thermistors used for thermal
mitigation with of_thermal to allow thermal driver to set
thresholds and receive notification through thermal sysfs.

This is a snapshot of the driver taken from msm-4.19 as of commit
f94ba33e3b90 ("Merge "usb: dwc3-msm: Fix GDSC collapse in host mode
bus suspend").

Change-Id: I9211552317955c503b7287876e11cd161c37f706
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2020-01-04 20:48:53 -08:00
Bojun Pan
fd0c830548 msm: IPA: add the missing iounmap handle
On uC debug stats, whenever uC provides the invalid protocol id,
we have to do the iounmap to prevent the leak.

Change-Id: I1360a04c5013657b5c9a051ee11d1a6cb5556915
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
2020-01-03 16:31:38 -08:00
Isaac J. Manjarres
15f586b2de arm64: defconfig: Enable all memory hotplug related configs on Lahaina
Enable all of the configuration options related to memory
hotplug for the Lahaina target.

Change-Id: I1f39c5ee7ecdca18746f09fb2ee58b4c2de63602
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:35 -08:00
Sudarshan Rajagopalan
fdee3b6ba8 soc: qcom: mem-offline: Clear page-table entries after offline
After a memory block is offlined, the page-table entries should be removed
in order to avoid any CPU speculative accesses happening on this region.
Clear off the entries at the leaf levels (PUD or PMD) on a block mapped
memory region. This only zeroes the entries and does not free the page
table memory. During online, we create mappings again for these regions.

Change-Id: I71091c33589645567c60457ba569dd393ddcab59
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>
[isaacm@codeaurora.org: resolve merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:35 -08:00
Liam Mark
1f1fb52ed2 soc: qcom: mem-offline: Set offlinable region based on minimum DDR sizes
Currently we use a percentage property value to determine the amount of
offlinable memory in the system.

However a percentage property doesn't support accurately configuring the
offlinable region sizes on targets with different amounts of DDR.
For example it is not possible to configure the system such that 4GB
targets won't have any offlinable region, 6GB targets will have a 1GB
offlinable region and 8GB targets having a 3GB offlinable region without
creating a separate DT files for each target.
Many customers want to be able to support different DDR sizes without
creating separate DT files for each target.

Replace the  mem-percent property with an offline-sizes property which
contains an array of offlinable memory region sizes to apply to targets
based on their DDR size.

Change-Id: I93210beec153ca0179c0087ce98afd4dfc22ea02
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:35 -08:00
Sudarshan Rajagopalan
1f5344a153 arm64: Update dram end address while randomizing base
Update the physical end address of available RAM in calculation
used for randomizing the memory base address base.

Change-Id: Id32260d5c15ec4363ab62755238a10cc4dfaabe8
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:34 -08:00
Sudarshan Rajagopalan
42be955907 arm64: mm/memblock: Update memory limit calculation
The system RAM region would not be ideally contiguous from
start to end of DRAM. Detect any offset/holes present in the
DDR region and update the memory limit being set, so that the
DRAM end address is aligned to the memory block size. This is
a requirement for mem-offline framework to work properly.

Change-Id: I97cb0cce70e7c414ae2d200a4a3f714d145c0e64
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:34 -08:00
Liam Mark
d05df014db drivers: base: expose amount allocated per block
Add a new sysfs node called allocated_bytes to each memory block which
reports the amount of memory currently allocated from that block.

Userspace can then use the allocated_byes node to better evaluate the
potential cost of offlining an individual block since all the allocated
memory in the block will need to be migrated when the block is offlined.

Change-Id: I520de2dd56e4562a65c48e38edb1236a8cbce5fd
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Signed-off-by: Swathi Sridhar <swatsrid@codeaurora.org>
[isaacm@codeaurora.org: resolve merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 15:44:34 -08:00
qctecmdr
7c6f0d6195 Merge "arm64: mm: Fix compilation when CONFIG_MEMORY_HOTPLUG is not enabled" 2020-01-03 14:21:49 -08:00
Isaac J. Manjarres
5386cc907b arm64: mm: Fix compilation when CONFIG_MEMORY_HOTPLUG is not enabled
remove_pagetable() should only be called when CONFIG_MEMORY_HOTPLUG
is enabled to clean up the page table entries created when memory
was hot-added.

Change-Id: I38cf42673a7637dac62d13a3083b0963c8a435b3
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-03 12:35:03 -08:00
qctecmdr
aa9193d870 Merge "defconfig: lahaina: Enable QRNG driver" 2020-01-03 12:10:31 -08:00
qctecmdr
ca53b773ed Merge "msm: IPA: uC debug stats for loadable modules" 2020-01-03 11:21:30 -08:00
qctecmdr
7bfb7b4733 Merge "mm, oom: Try to online memory block before killing" 2020-01-03 10:20:54 -08:00
qctecmdr
1f510928ba Merge "defconfig: Lahaina: Enable support for WLAN" 2020-01-03 09:06:48 -08:00
qctecmdr
1758058b4f Merge "arm64: Make section size configurable for memory hotplug" 2020-01-03 05:46:20 -08:00
qctecmdr
266944773a Merge "mm/memory_hotplug: Add hot-added memory blocks to ZONE_MOVABLE type" 2020-01-03 03:23:21 -08:00
qctecmdr
f984fe46b1 Merge "NFC: Add NFC I2C and I3C drivers for SNxxx" 2020-01-03 03:23:21 -08:00
qctecmdr
7effb8fd2b Merge "arm64: defconfig: Enable TSENS driver for lahaina" 2020-01-03 02:44:42 -08:00
qctecmdr
6e10762150 Merge "arm64: Override memory limit set by boot parameter" 2020-01-03 02:02:59 -08:00
qctecmdr
ba56951f33 Merge "dma-mapping-fast: Clean up common code" 2020-01-03 00:44:18 -08:00
qctecmdr
57f426091c Merge "arm64: defconfig: Enable EDAC driver support for QCOM SoCs" 2020-01-03 00:06:33 -08:00
qctecmdr
a7004306b1 Merge "kasan: Zero shadow memory on memory hotplug" 2020-01-03 00:06:33 -08:00
qctecmdr
e2131103f7 Merge "defconfig: Initial genericarmv8 defconfig" 2020-01-02 23:25:07 -08:00
Liam Mark
c5d41d1162 mm, oom: Try to online memory block before killing
Before killing a process first try to see if there are any offlined
memory blocks, if there are try to online one of them.

Change-Id: Ie97c8b69f0ba173c202a891a38a5c914869ddaae
Signed-off-by: Liam Mark <lmark@codeaurora.org>
[isaacm@codeaurora.org: Update walk_memory_range to walk_memory_blocks]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-01-02 22:15:25 -08:00