Commit graph

899,353 commits

Author SHA1 Message Date
Vijay Patil
550d642faa icnss2: Add Null check before dereferencing variables
Add Null check before dereferencing dev for set FW log mode,
force wake request & force wake response. Add ERR_OR_NULL check
for wpss load API gets called for wpss subsystem. Check for qdss
memory segment length.

Change-Id: Id4a43fa9ae332faa7f5741f338d985db8272d17a
Signed-off-by: Vijay Patil <vijaylil@codeaurora.org>
2021-07-07 14:46:46 +05:30
qctecmdr
0d384b92bf Merge "cnss2: Add code to notify mhi about link down" 2021-07-06 05:09:13 -07:00
qctecmdr
3f7b291018 Merge "coresight: fix etr pice mode issue" 2021-07-05 22:49:49 -07:00
qctecmdr
5b9483c75b Merge "msm: kgsl: Add inode info in kgsl mem dump" 2021-07-05 18:35:51 -07:00
qctecmdr
ebd7f8e1c0 Merge "taskstats: properly account NR_KERNEL_MISC_RECLAIMABLE" 2021-07-05 03:02:08 -07:00
qctecmdr
1e9f7380d5 Merge "pinctrl: qcs404: update gpio, function and group binding" 2021-07-05 03:02:08 -07:00
qctecmdr
67683b3310 Merge "soc: wdog: Ensure missing user watchdog pet can trigger bite" 2021-07-05 03:02:08 -07:00
qctecmdr
ee417bda82 Merge "defconfig: sdxlemur: Enable DRM and GKI_HIDDEN_DRM_CONFIGS on sdxlemur" 2021-07-05 03:02:08 -07:00
qctecmdr
72b140fb68 Merge "Merge android11-5.4.86+ (e399f16) into msm-5.4" 2021-07-05 03:02:07 -07:00
qctecmdr
34c4a7f112 Merge "usb: dwc3: Add support of disable L1 in HS mode" 2021-07-05 03:02:07 -07:00
qctecmdr
7f2cb0175f Merge "mhi: core: Notify all mhi client's for PCIe link down recovery" 2021-07-05 03:02:07 -07:00
qctecmdr
b21450113f Merge "spi: spi-msm-geni: Store the wrapper dev handle for LE VM also" 2021-07-05 03:02:06 -07:00
qctecmdr
15f150f081 Merge "dt-bindings: msm: Add bindings for flash type" 2021-07-05 03:02:06 -07:00
qctecmdr
91c528605e Merge "soc: qcom: eud: Add support for different interrupt masks" 2021-07-04 21:57:40 -07:00
qctecmdr
d832036bda Merge "defconfig: sdxlemur: Enable configs for minidump" 2021-07-04 21:57:40 -07:00
qctecmdr
dfcaefd71c Merge "msm: mhi_dev: Disabling Ch Db Intr during MHI INIT phase" 2021-07-04 21:57:38 -07:00
Abhinab Abhinab
eac435a0a2 msm: mhi_dev: Disabling Ch Db Intr during MHI INIT phase
In order to tackle the spurious interrupts coming from the host
on an invalid channel, the channel doorbell interrupts are
disabled during initialization phase. These are enabled after
receiving the start command for a particular channel.

Change-Id: I12bb315bcd249383ed442ad969e84c9eef25a324
Signed-off-by: Abhinab Abhinab <aabhinab@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:02 -07:00
Subramanian Ananthanarayanan
ec8cdae293 msm: mhi_dev: check for error during ring processing
The change is to check for error code from cmd processing in case
of db pending cases, to avoid rd_offset increment.

Change-Id: If213297fe02ec1087bfab572f5af97b1e7bb5791
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:02 -07:00
Nitesh Gupta
45edd7ec79 msm: mhi_dev: free allocated memory in reverse order of allocation
Freeing cmd_ctx before ereqs will result into NULL ptr
dereference. Freeing memory in proper order.

Change-Id: Ie999017685574e940685eee3b7c205ebe1672664
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:01 -07:00
Nitesh Gupta
e623db906d msm: mhi: Queue channel db only if channel is open
Channel interrupts are seen on device even before,
channel ring is initialized. Queuing pending work
without checking ring status can lead to processing
of spurious interrupts. Adding proper checks in place
before queuing channel doorbell.

Change-Id: I3ccd7302b535d2b8ef63eada9d7a1fe553dccdaa
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:01 -07:00
Subramanian Ananthanarayanan
ad22cfa30a msm: mhi_dev: Allocate ring element during M0
Device allocates ring memory during mmio initialization, this
causes 128 event ring elements to be created as MHICFG
register may not be updated by the host. This causes memory
to get exhausted leading to an MMIO init failure.

The Change is to allocate ring memory during M0, during which
MHICFG register is bound to be updated by the host.

Change-Id: I04a0e0ed79a46f16f96e2be4c5c68cba9ee2c99d
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:50:38 -07:00
Hemant Kumar
89d2d76a29 pci: msm: Get rid of msm pcie device table
Since pcidev_table is no longer used in the driver
get rid of the table entry from msm pcie device
structure. Also remove unused structure members
from msm_pcie_device_info. Since device table
is removed, rename msm_pcie_config_device_table
to msm_pcie_config_device_info.

Change-Id: I5359cc0f85d6b7f9f069f7decc3bc67105543abb
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-07-02 06:21:44 -07:00
Hemant Kumar
e9efafa35c pci: msm: Remove RC and EP config space shadow save and restore
All endpoints and bridge are performing their config space save
and restore. Hence root complex driver does not need to perform
the same on behalf of them. For root complex use PCI framework
provided APIs to perform RC config space save and restore. Save
golden copy of the RC config space upon enumeration and use it
to restore RC config space in case of link down. Get rid of all
custom APIs for saving, restoring and dumping of RC and EP config
space entries.

Change-Id: I466e26aaaee0ae317323aae0c535c3319f95e681
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-07-02 06:20:12 -07:00
Yuanfang Zhang
5de46e8161 coresight: fix etr pice mode issue
Only start the sw mode when pcie_path is configured as sw.

Change-Id: I3b9fb890008760b0a25827bb039cd378512f4efe
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-07-02 14:16:51 +08:00
Lei Chen
c2b3cdaad3 defconfig: sdxlemur: Enable DRM and GKI_HIDDEN_DRM_CONFIGS on sdxlemur
This change enables DRM and GKI_HIDDEN_DRM_CONFIGS for QPIC display
on sdxlemur.

Change-Id: I856d26e0dafcffd523eefc660f00612448a4529f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-07-02 13:49:37 +08:00
qctecmdr
f6eb60186e Merge "msm: ipa3: support dynamic IPPT SW-flt change" 2021-07-01 14:51:06 -07:00
Mohammed Siddiq
8a0fdd81d8 cnss2: Add code to notify mhi about link down
Add code to notify mhi about link down.In scenario of link down
recovery failure with SSR enabled, cnss-daemon posts a QMI req
during subsystem shutdown execution, the mhi layer tries to access
doorbell register to process the qmi msg but it leads to NOC error
as pci link is down. So added code to notify mhi about link down
to avoid NOC error.

Change-Id: I3ccc2cbda37e271f14f3821bb055db3107dac228
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
2021-07-01 19:12:10 +05:30
Charan Teja Reddy
04dbe55b1b taskstats: properly account NR_KERNEL_MISC_RECLAIMABLE
NR_KERNEL_MISC_RECLAIMABLE contains the info in pages but accounting is
done considering it as bytes. Fix it.

Change-Id: I99a3bd43b7b77f6b137e1cc4c1854392d4a47635
Fixes: 5a5b186dfb ("taskstats: add support for system stats")
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
2021-07-01 06:18:34 -07:00
Akshaya Bhat
897a8bec14 pinctrl: qcs404: update gpio, function and group binding
Modify the gpio, function and group binding to make driver
in sync with TLMM specification.

Change-Id: Ia9bec2e870983b6f59aa694592883c1a32da2304
Signed-off-by: Akshaya Bhat <akshayab@codeaurora.org>
2021-07-01 06:10:09 -07:00
Maria Yu
64fdb4fa1d soc: wdog: Ensure missing user watchdog pet can trigger bite
The user watchdog was waiting the hardware watchdog bite by
stop petting it. But in the cpu suspend scenarios, the auto petting
by hardware prevent the expected watchdog bite. So add a new user pet
timer to explicitly trigger the watchdog bite by software when the user
watchdog petting is not happenned before timeout.

Change-Id: I71b1139192baa960ae00f7a27c630aedaf5a3ffa
Signed-off-by: Maria Yu <aiquny@codeaurora.org>
2021-07-01 05:55:35 -07:00
Vivek Pernamitta
b8159e3b1a mhi: core: Notify all mhi client's for PCIe link down recovery
send early notification to all MHI clients devices on PCIe
linkdown recovery when device supports RDDM dumps. so all
client channels registered to MHI will receive completion event.

Change-Id: I3c25d69b7d43afe2701fe5fae705533faf6f4dd1
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
2021-07-01 05:30:12 -07:00
shiwgupt
22dc79eea8 dt-bindings: msm: Add bindings for flash type
Add binding support for flash type for khaje camera.

CRs-Fixed: 2938804
Change-Id: I844b59125bb08034b1937422ac29485d5a7a2746
Signed-off-by: shiwgupt <shiwgupt@codeaurora.org>
2021-07-01 01:47:19 -07:00
Udipto Goswami
c3de8d2179 usb: dwc3: Add support of disable L1 in HS mode
On some platforms, L1 in HS mode is not supported.
Add support to disable L1 in HS mode on those
platforms by default through dt.

Change-Id: I624bde1e091e6e864bf7f7af93804c3728374d0d
Signed-off-by: Udipto Goswami <ugoswami@codeaurora.org>
2021-07-01 01:33:30 -07:00
qctecmdr
9585c2cb84 Merge "net: tcp: check for NULL send head during MTU probe" 2021-06-30 20:51:42 -07:00
Skylar Chang
0f5310aa7d msm: ipa3: support dynamic IPPT SW-flt change
Add the support for user-space module to dynamically
enable or disable IPPT SW-flt lists based on ipv4 or
connection port number to decide traffic going to
ipa offload or not.

Change-Id: I2cfee479c7810a26746179de152281f336a3052d
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2021-06-30 11:04:19 -07:00
qctecmdr
d9d62284f5 Merge "Add support to vote for SMPS" 2021-06-30 05:37:34 -07:00
qctecmdr
26e5573f6c Merge "msm: mhi: Queue pending_ring WQ post channel DB check" 2021-06-30 01:37:50 -07:00
qctecmdr
dc8e61bd5a Merge "msm: pci : Avoid deadlock with recovery and enemurate lock" 2021-06-30 01:37:48 -07:00
qctecmdr
8694227de6 Merge "fuse: give wakeup hints to the scheduler" 2021-06-30 01:37:48 -07:00
qctecmdr
00e600676f Merge "mmc: sdhci-msm: Update TLMM_NORTH_SPARE register as per vdd_px2 supply" 2021-06-30 01:37:47 -07:00
Balakrishna Godavarthi
ef0d4d698c Add support to vote for SMPS
This change will add support to vote for SMPS node if regulator
handle is provided in DTS source.

Change-Id: Ib370fd2fecfe04585cd2ab643f597714ead18a93
Signed-off-by: Balakrishna Godavarthi <bgodavar@codeaurora.org>
2021-06-30 00:11:04 -07:00
qctecmdr
c568070453 Merge "input: touchscreen: focaltech: add a new property" 2021-06-29 21:37:02 -07:00
qctecmdr
a102e0a02d Merge "msm: ipa: macros to determine the structure mismatch" 2021-06-29 21:37:01 -07:00
qctecmdr
0e977f082b Merge "msm: mhi_dev: Check to prevent in_use_list access" 2021-06-29 21:37:00 -07:00
Melody Olvera
2d656cb336 soc: qcom: eud: Add support for different interrupt masks
The EUD driver defaults to using INT1 for its interrupt mask.
However, certain targets don't use that interrupt for signalling
the apps processor. To remedy this, look for the interrupt-mask
binding in the device tree entry, and, if present, use the offset
there instead of the default.

Change-Id: Ib2db82c64d21a650044163b7322bc66ffe159d36
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2021-06-29 13:15:11 -07:00
Fei Mao
29c674dd9c input: touchscreen: focaltech: add a new property
Add a new property to indicate power's state when sleep.

Change-Id: Ic54fbbd0adee8716ad0b2d892814f8ac38b683c5
Signed-off-by: Fei Mao <feim1@codeaurora.org>
2021-06-29 02:04:18 -07:00
Kaustubh Pandey
d2bdf73897 net: tcp: check for NULL send head during MTU probe
skb_peek() can return NULL when the socket write queue is empty. This
causes problems when using tcp_for_write_queue_from_safe(), as this
macro
resolves down to "for (tmp = skb->next; ...", causing a NULL
dereference.
Fix this by indicating that the tcp send queue head can not be coalesced
as there is nothing in it. This fixes the following:
Unable to handle kernel NULL pointer dereference
pc : tcp_write_xmit+0xe1c/0x1210
lr : tcp_write_xmit+0x38/0x1210
Call trace:
 tcp_write_xmit+0xe1c/0x1210
 tcp_tsq_write+0x110/0x140
 tcp_tasklet_func+0x120/0x170
 tasklet_action_common+0xec/0x128
 tasklet_action+0x20/0x28

By ending the MTU probe because of the empty send head.

Change-Id: I0c3283c37ee69a4941c8d9e88519e586c7905d25
Signed-off-by: Sean Tranchetti <stranche@codeaurora.org>
Signed-off-by: Kaustubh Pandey <kapandey@codeaurora.org>
2021-06-28 23:15:45 -07:00
Pradeep P V K
ac247e7425 fuse: give wakeup hints to the scheduler
Use synchronous wakeup interface to wakeup the userspace daemon. Scheduler
can make use of this hint to find a better CPU for the waker task.

Change-Id: I7d077235f9b8fe771869dd7e6fccee7d356d858b
Suggested-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Pradeep P V K <pragalla@codeaurora.org>
2021-06-28 22:59:55 -07:00
Pradeep P V K
45eba39e07 wait: add wake_up_sync()
The synchronous wakeup interface is available only for the interruptible
wakeup. Add it for normal wakeup.

Change-Id: Ia4460aa55690d14d203cdc843bd600c9e26c53f1
Suggested-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Pradeep P V K <pragalla@codeaurora.org>
2021-06-28 22:59:07 -07:00
Vivek Pernamitta
3bb65a0c8c msm: pci : Avoid deadlock with recovery and enemurate lock
Avoid deadlock scenario when wake interrupt arrives at enumeration
time and holds recovery lock and wake handler workqueue tries to
acquire enumeration lock. In parallel client driver can call
msm_pcie_pm_control for suspend where enumeration lock could
be successfully acquired by msm_pcie_pm_control instead by wake
handler and waiting for recovery lock which is currently acquired
by wake handler (which is currently waiting for enumertion lock)
which could leads to deadlock scenario.

msm_pcie_enumerate		wake handler		pm_control
	|			     |    	     (suspend thread)
	|			     |			   |
	|			     x acquired 	   |
	x acquired		     | recovery lock	   |
	| enumerate lock	     |  		   |
	|			     o waiting for	   |
  	|			       enumerate lock      |
	x released					   x acquired
	| enumerate lock			  	   | enumerate lock
							   |
							   o waiting for
							     recovery lock

we have fixed the order of locking in msm_pcie_pm_control to avoid
deadlock scenario.

Change-Id: Ifc72c643f7c0793cfa10a953723e953ce73a82b6
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
2021-06-28 21:11:12 -07:00