Instead of doing the adreno device setup at compile time with some ugly
macros, do it at the beginning of device probe. This allows us to retry
probe without having to worry about coming back through probe with a
partially modified data structure.
Change-Id: Ic0dedbad09fa37e2a1a8161e7d54c676d42151e8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Now that we are creating the OPP tables at runtime, we don't need a
platform device defined in the device tree just for the bwmon governor.
Instead, create a simple child device and use that.
Change-Id: Ic0dedbadbebc2dac4f9a1e05045a7462742aaefd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Instead of gloaming the boolean adreno sysfs functions onto the u32
functions give them their own dedicated functions that deal with native
booleans from top to bottom. This allows for a bit of code cleanup but
more importantly fixes the logical disconnect of switching back and forth
between u32 and bool.
Change-Id: Ic0dedbadc5b669b5131ff232d80d25ef5486b85e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
All a5xx and a6xx targets use the CP_SMMU_TABLE_UPDATE opcode to switch the
pagetable which handles all the needed locking but we've seen fit to add a
bunch more around it, including keeping a dummy NOP IB used for
synchronization on a3xx targets.
Stop the madness and remove all the extraneous locking and other baloney
and just do a straight up SMMU_TABLE_UPDATE without fanfare. And now
that the setstate is only valid for a3xx, only create it for a3xx thereby
removing another global buffer from the mix.
Change-Id: Ic0dedbad7694cad6d40fcee66b7864a454df1653
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
In the code the memory pools are generic. They are stored in global memory
and none of the APIs take a device handle, yet the device tree description
has traditionally been device specific and as such the pools were set up
at device initialization time.
This is not needed as we can safely look up the memory pools node from the
compatible string at any point. Make the memory pools completely generic
and initialize them with the rest of the KGSL core. This clears the way
to move the memory definitions out of the device and into the top level
soc in the device tree, but since we are using the compatible string
that isn't strictly necessary.
Change-Id: Ic0dedbad687b9581f0e40142644ed19ee069d54d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
After allocating and zeroing pages from system memory or the pool we need
to ensure that the cache is synchronized so that it doesn't cause problems
down the road. Use dma_sync_sg_for_device to make sure the allocated pages
are clean. This isn't the best way to handle this but we haven't yet come
up with a better way and this does the job.
Change-Id: Ic0dedbade48b700015bec172cf9b64e436364b4a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Do a bit of housekeeping with the device tree parsing for memory pools to
accommodate some future changes.
Change-Id: Ic0dedbadd12b23a958f398e6731ad9cf2d5a64db
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For reasons unknown while most of the pool code was properly living in
kgsl_pool.c, kgsl_pool_allocate_pages() was in kgsl_sharedmem.c and
depended on several other exported functions just to make it work. Move
the function and fix up the helper functions.
Change-Id: Ic0dedbad7a7c06adce4f87f7915853eb44a4151c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For some reason the legacy efuse code was taking struct adreno_device
but wasn't using it. Remove it so we can query the efuse before the
adreno_device even comes into being.
Change-Id: Ic0dedbad3d69757dcdf59501a6b97e2a98e0827e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The generic Adreno code was reaching into the a5xx specific code to
run the critical packets. This is mostly unnecessary because the
a5xx code is the one that calls into the generic code in the first
place so it is a useless round trip especially for such simple
code. Move the secure switch code into the target specific code.
Change-Id: Ic0dedbadf6d25a0740719cf8ac0ccf8802f4c33e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There isn't any need to allocate dynamic memory for the mailbox client.
Change-Id: Ic0dedbad5ecd1b0e5702d2731b1b834418e3399c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Move the preemption timer into the generic adreno code so we don't need
to destroy it in target specific code and generally get rid of a bunch
of static assumptions in the target specific code.
Change-Id: Ic0dedbad4fff2c85dcb9d5c1300c45ee659675bd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The RGMU powerlevels are an exact clone of the GPU powerlevels. There
is no need to save them separately.
Change-Id: Ic0dedbad0d6cb48ee88673ae6c7c3ab16fb4c508
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The zap shader is loaded the same way for both a5xx and a6xx targets so
consolidate the support in the generic Adreno code.
Change-Id: Ic0dedbad964eef9054b549d0df9ba7e84d653f62
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We only ever have two sub-devices for IOMMU, one device for the user
context and an optional entry for the secure context. Instead of
blindly querying for compatibles and try to match the string names,
explicitly search for the device names we need and set them up that
way.
This cleanup also lets us swap the behavior of the mmu.secured flag.
We assume it to be true and then clear it if the secure context is
not found rather than the other way around. This allows us to make
sure that the flag is set correctly during probe so we can skip
secure context setup.
Change-Id: Ic0dedbad540733a1eaf1729ddec0031f397d9e43
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
USB cable can be disconnected (function disable) and function
descriptors can be freed while userspace daemon requesting for
descriptors copy to userspace. Avoid stale pointer copy by always
copying only local copy of desctiptors.
Change-Id: I16c01d22058e7148546f1ffbc5017520402eda97
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
using debug prints instead of err prints
Change-Id: Iaf667ca33e47f867dbd118f4d839f2e8e955f557
Acked-by: Suhas Mallesh <smallesh@qti.qualcomm.com>
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
dwc3-msm driver is functionally dependent on the phy-generic,
phy-msm-snps-hs, and phy-msm-ssusb-qmp drivers. Hence, explicitly
add a soft-dependency on it to avoid unnecessary re-probes
when built as a module.
Change-Id: I16d3a3fb72a968b0ae7935df74cff86697a97c32
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add new macros in GSI driver to support 32-bit
architecture.
Change-Id: I7fd9867b19458ac962a87c03dfcf2ea570a4de69
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
Debug patch to capture GPI hardware status when a GSI General interrupt
is triggered.
Change-Id: I81a5d3858bd295383cd1079394fb161930d63913
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
Add support for HYP call to setup the sharedmem permissions
for the MPSS client.
Change-Id: I3b48ae962865d8d0a0ea6e3fbb8e21278b59c690
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
[riteshh@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Ankit Jain <jankit@codeaurora.org>
Signed-off-by: Richard Patrick <richardp@codeaurora.org>
This is a snapshot of the MSM sharedmem driver as of msm-3.14
commit:
commit <149717c0> ("uio: msm_sharedmem: Add custom mmap") +
sharedmem qmi logic is removed.
The following changes are included:
02d55287 uio: msm_sharedmem: Restrict debugfs write to root.
de961fc7 uio: msm_sharedmem: Return ENOMEM if the shared mem addr
is zero.
b974ce64 uio: msm_sharedmem: Add addtional information to debugfs
c46af547 uio: msm_sharedmem: Add support for dynamic shared memory
allocation
Change-Id: I49902f018bde1d59d41027b7e46268cc17231a3e
Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Ankit Jain <jankit@codeaurora.org>
Signed-off-by: Richard Patrick <richardp@codeaurora.org>
This commit adds new UART port to support UART available on Embedded
USB Debugger (EUD).
Change-Id: Ib2bcf15df04875e5d9eb7ce3dc30f1d187236279
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
Absence of traffic is guaranteed when the device sitting behind a devbw
device is suspended. In such cases, it is a waste of power to make non-zero
bandwidth votes or to scale the devbw device. So, provide APIs to
suspend/resume the devbw device as needed.
Change-Id: Id58072aec7a9710eb917f248d9b9bd08d3a1ec6a
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[avajid@codeaurora.org: renamed devbw to icc and made minor styling change]
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
Some devfreq devices using this governor might need suspend/resume support.
When suspended, those devices won't need any bandwidth votes and there is
no point in monitoring their bandwidth either.
Therefore, upon suspend, vote for zero bandwidth and stop the HW monitor.
Upon resume, vote for the previous bandwidth and start the HW monitor.
Change-Id: I318449995d714959f0ebfe91961bc23fa8edbd04
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[avajid@codeaurora.org: resolved trival merge conflicts and made minor styling changes]
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
The BIMC bwmon device supports monitoring read/write traffic from each BIMC
master port. It also has the capability to raise an IRQ when the traffic
count exceeds a programmable threshold. This allows for it to be used with
the bw_hwmon governor to scale the BW requests from each BIMC master.
Change-Id: Ie8a1471226411e23954ed556292186a5a864ddc1
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[avajid@codeaurora.org: made minor styling changes]
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
This driver registers itself as a devfreq device that allows devfreq
governors to make IB/AB bandwidth votes. This driver allows the governors
to be agnostic of the bandwidth voting APIs, the number of master ports or
slave ports, the actual port numbers, the system topology, the available
frequencies, etc.
Change-Id: If055ddd580afd41f9668b111e6c09a047488b2e0
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[avajid@codeaurora.org: moved to icc framework, renamed to devfreq_icc and made minor styling changes]
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
The CPUBW HW monitor devfreq governor uses the Krait L2 PM counters to
determine the bandwidth needed by the Krait CPU subsystem. This governor
can be used in conjunction with the CPUBW devfreq device to dynamically
scale the DDR frequency based on the demand/actual usage from the Krait CPU
subsystem. Since this governor uses the Krait L2 PM counters it can
conflict with certain profiling tools.
The Krait L2 performance monitor counters have the capability to count the
no. of read/write transactions going out the master ports. They also have
the capability to raise interrupts when they overflow. This driver uses
those counters to determine the true usage of DDR from the Krait processor
subsystem and then recommends CPU DDR BW votes based on the measured values
and the following tunable parameters.
The driver provides various tunables that allow it to be tuned more in
favor of power or performance:
- io_percent: The percentage of the CPU time that can be spent waiting on
memory I/O. Lower value is better performance and worse power.
- sample_ms: The sampling period in milliseconds. This only affects the
sampling period when DDR use is ramping down or is increasing very slowly
(See tolerance_percent).
- tolerance_percent: The minimum increase in DDR use, compared to previous
sample, that will trigger an IRQ to immediately bump up the bandwidth
vote. It's expressed as a percentage of the previous sampled DDR use.
- decay_rate: The parameter controls the rate at which the history is
forgotten when ramping down. This is expressed as a percentage of history
to be forgotten. So 100% means ignore history, 0% mean never forget the
historical max. The default 90% means forget 90% of history each time.
- guard_band_mbps: This is a margin that's added to the measured BW (and
hence also the Bus BW votes) that's present to account for the time it
takes to ramp up the DDR BW while the CPU continues to use the DDR.
- bw_step: All BW votes are rounded up to multiples of bw_step. The default
value is 200 MB/s that turns out to ~25 or 12.5 MHz based on the SoC. A
smaller value would mean more frequent bus BW changes. A higher value
would mean less frequent BW vote updates, but also means at times an
unnecessarily higher BW vote (due to the rounding up).
Change-Id: I88629a3e545cdca7160af8f8ca616ecc949d9947
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[aparnam@codeaurora.org: Replaced snprintf with scnprintf]
Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org>
[avajid@codeaurora.org: updated attr definitions and made minor styling changes]
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
Enable the RPMh clock driver so that consumers can vote
for real RPMh clocks.
Change-Id: I274f9035b93766473a15731814f16da9f80f4070
Signed-off-by: David Dai <daidavid1@codeaurora.org>
