rimps_memlat driver will cache PMU counter values when cpu
is going down in hotplug path and also when CPU is entering
lpm. Once the PMU counter values are saved to the shared memory,
cache valid bit is set, and it is cleared when cpu comes back online
or exit from lpm.
RIMPS expects the PMU cache flag to be valid, when cpu is offline
or entered lpm. Observed a race when the hotplug is in progress
and that particular cpu can enter and exit lpm. The current
implementation clears the cache flag during lpm exit without
checking the cpu hotplug status. Once hotplug is complete, core
goes offline and the status flag will remain in incorrect state
indicating cache area is invalid, which will cause RIMPS to read
PMU counter values directly from hardware which will result in APB
read errors.
When hotplug is in progress, do not set status flag to
PMU_CACHE_INVALID in CPU_PM_EXIT path.
Change-Id: I17947ad93eeef99b2148e873dc719622aa372b7c
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Setup pmu counter functions of rimps memlat driver check cpu_is_hp
flag before creating counters, and the setup of pmu counters will
be called in two places one in probe and other when cpu is coming
up from hotplug path.
The hotplug path will clear cpu_is_hp after the pmu setup calls are
issued, but pmu setup function will not create pmu events as the
cpu_is_hp flag not cleared at this point, this results in pmu
counters not getting setup even cpu is up from the hotplug path.
Add a parameter to these functions indicating from which path these
are called and update the logic accordingly to allow creation of
pmu events when core is coming up.
Change-Id: I8bf8d52d91d14ab3f4d837271055f03e704e98a0
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
RIMPS memlat driver reads the current PMU counter value
using perf_event_read_local() API at the time of core
going offline or entering LPM and saves the current
snapshot to a shared memory for access by RIMPS.
RIMPS reads these values from the shared memory when
core is offline or in LPM state, and reads directly
from PMU hardware when core is online. The value read
from hardware and the one read from shared memory are
going out of sync because perf event driver limits the
counting range of PMU counter to half of the total range
supported by hardware, and it configures the counter to
start counting from midpoint at the time of counter reset
and upon overflow. It keeps adding the delta read from
hardware counters to software maintained counters and it
returns the same through perf_event_read API.
As this is not the exact same value as what is read from
hardware counters, the values read by RIMPS from shared
memory are going out of sync.
To address this get the current snapshot of hardware counter
value from prev_count member of hw_perf_event structure which
is part of perf_event structure, and store that to shared memory.
Change-Id: I71f416270a02f7925b16e576f637cf3579fec6ce
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Previous iterations of the llcc driver did not account for caches with
no llcc broadcast hardware. This fixes this issue.
Change-Id: I221d0d65d17c34645cd1a4070737fe9bebfa4b16
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
Update the register offsets for the debug mux to measure
the clock frequency correctly.
Change-Id: I329f3f3416d6b097e0fc38e72d136a5b21db7049
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
This module is used to tunnel multicast
packets received on an interface to WLAN
clients which have registered for these
packet streams. Mainly used to tunnel
EMBMS packets received on TMGI streams.
Change-Id: I1cea29bff192d375317dda3d1baebb594e0b9c39
Acked-by: Raju Velpula <rvelpula@qti.qualcomm.com>
Signed-off-by: Paras Singh Jain <parassin@codeaurora.org>
Pass minimum and maximum voltage values while enabling regulators.
Change-Id: I3de7f343cd0d8fd1953fa5d091c411c013a0dd29
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
CDSPRM module implements a RPMSG interface to communicate with CDSP
while providing a way for CDSP to vote for CPU QoS to benefit CDSP
applications performance.
Change-Id: Ib2627e611b3d4e25f68b7ecee672d4a6474050c3
Acked-by: Sreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: Bavyasritha Alahari <alahari@codeaurora.org>
Currently ipc_logging will capture the usb request's dma address but
when sg list is used usb request's dma address is not populated. This
change adds start_sg's dma address which is populated when sg list is
used for usb transfers. Also increase the number of log pages to capture
more ep events.
Change-Id: I36ada11429e168e2d3d09cf3427b1f3bcdacc285
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
Removed the support for game status node to specifically compare
for gfx events, the same is archived with checking the value of pid.
This saves an extra fops on each iteration for game on and off.
Rejecting events with timestamp = 0.
Change-Id: Icbafc4d1f8fa1e444b9074fcf2fde47a6e85d609
Signed-off-by: Aman Mehta <amanmeht@codeaurora.org>
Avoid sending fw down uevent to wlan driver twice for
one ssr/pdr.
Change-Id: I9c99b16c3760ef7b432df16b2f326db39371e3c3
Signed-off-by: Sandeep Singh <sandsing@codeaurora.org>
Refine driver's power on/off flow and make regulators' state
to be proper in all scenes.
Change-Id: I5d26c3134dfbdc53037fe4aac16739b24c0c183b
Signed-off-by: Fei Mao <feim1@codeaurora.org>
Align iova based on size for optimal performance before mapping.
Change-Id: Ic1d9a2125690f91ad3b15f7373683edb48d9f497
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
Set hw reset flag as done after sdcc hw reset else
hw reset as part of recovery happens only once.
md->reset_done flag is set inside mmc_blk_reset function with
flag MMC_BLK_CQE_RECOVERY. And this flag is cleared only
inside function mmc_blk_reset_success. But since mmc_blk_reset
and mmc_blk_reset_success are used with if else condition, code
flow can execute only one of the function, hence if mmc_blk_reset
is executed and not cleared within mmc_blk_reset_success, next
mmc_blk_reset call returns without resetting the hw.
Change-Id: I14915ae26240769b45cec8d2793e5f8604062eef
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
During cqe initialization, upon enabling cqe enable bit,
command queue engine gets reset. During hw reset this is
leading to SMMU fault as during reset tdl base register
contents are getting lost.
Restore cmdq vendor cfg register data post hw reset to disable
cqe reset post cqe initialization.
Change-Id: I8ffa2c2fa6754b697c4d441004efa4dc366bbf5f
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
Add support for gcc hw reset for sdcc. This feature would
help recover emmc host controller and card cleanly in case
software recovery fails.
This would also help reset hwkm key during probe for crypto
when called during probe.
Change-Id: I32c7fbfb1a97bb69924e1a0c6ea90a400dd35c43
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
