When a context bank's SCTLR is programmed for an SMMU client
that wishes to bypass S1 translations and enable io-coherency, the
SHCFG bitfield of the SCTLR is set to 0. This means that a
client's transaction's shareability memory attribute will not be
modified as it goes through the SMMU.
This is problematic if the SMMU client's transaction is marked as
non-shareable, as the attribute will not be modified to be classified
as io-coherent, since io-coherent transactions should be cacheable
and shareable. Instead, the transaction will not snoop the CPU
caches, and will go to DDR, and may read incorrect data.
Thus, program the SHCFG bitfield in the context bank's SCTLR to
override the shareability attribute to outer shareable when
enabling io-coherency for clients using S1 bypass.
Change-Id: Ia4c1bbe7812ce7c2062c636e2b1bb39fa1ac516c
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
store eth_ready_info pointer for late callback
trigger instead of storing cb and user data addresses.
eth_ready_info pointer is static and shall be searched
when callback is unregistered.
Change-Id: I03cbbc4920ee663890bad12ece6d41e9bd2a68d5
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Pull the RFR line before doing stop_rx in uart driver.
This is to prevent any rx data to come into the uart rx fifo when
stop_rx is being executed.
Remove the rx length zero check in
handling dma rx to prevent race conditions with EOT and DMA_DONE
interrupt bits.
Issue scenarios could be that during baud rate change/ runtime
suspend or any other place where stop_rx is used, there might
be a race between rx data entering uart rx fifo and availability
of dma buffers in uart driver. In this scenarios there will
be interrupt storm with rx water mark interrupt.
Change-Id: I92163c4997c1709269dce67a1d492533f710abfb
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Add snapshot of the smb358 charger as of msm-4.14
commit 790f0644f00c ("net: stmmac: Alert QTI on SDX
of host AP's SSR status"). Fix minor static analysis
tool errors.
Change-Id: I7c88f48a90cfca6c22ac4ed5289f78a32e524dc4
Signed-off-by: Kavya Nunna <knunna@codeaurora.org>
Add novatek chip id and firmware during boot up to
enable touch.
Change-Id: I382ae51c7bb4bf270c2e01b484281fcc24270062
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
Update phy revision information before calling phy_init(),
so that phy driver can perform revision specific configurations.
Change-Id: I834306851e30a203705ad824fc142813b989abc5
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Enable MFD SPMI PMIC driver and several SPMI and PMIC drivers
which are needed to provide baseline support of PMIC peripherals.
Change-Id: Ic0b24c62bec654c61bbf0034c20d775d686eb9c4
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Add support for UFS controller and add support for
QTI inline encryption.
Change-Id: I680c75448c0fd9b2e6c37d106075c1a39213abac
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Enable interconnect L3 driver so that consumer can vote
for L3 performance points.
Change-Id: Id0ff3e976976a05fa6ff47c7ccb9e1a3a3aed2e3
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Enable the SM8150 interconnect driver so that consumers are
able to obtain their path handles properly.
Change-Id: Ie099accf2dbfa587f23dd9f434bf04c7eca6b348
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
To improve OVP handling increase the min-offtime and dead-time
as per hardware recommendation.
Change-Id: I28040808d6c114b718aad0e0ab63554683e7746f
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
