Commit graph

891,729 commits

Author SHA1 Message Date
qctecmdr
797e04bfa4 Merge "mmc: Enable clk scaling for cqe" 2020-10-19 03:31:29 -07:00
qctecmdr
2777a719d6 Merge "soc: qcom: smem: increase smem hosts max count" 2020-10-19 03:31:29 -07:00
qctecmdr
63fbc8ffb1 Merge "mmc: sdhci-msm: Pass min and max voltage values to enable regulators" 2020-10-19 03:31:29 -07:00
qctecmdr
819fc38366 Merge "net/embms-kernel : EMBMS Tunneling Module" 2020-10-19 03:31:28 -07:00
qctecmdr
9cd07da8bf Merge "icnss2: Avoid sending fw down uevent to wlan driver twice" 2020-10-19 03:31:28 -07:00
Deepak Kumar Singh
9228043d74 soc: qcom: smem: increase smem hosts max count
Increase max host count to 14, inorder to accommodate newly
added sybsystem wpss with smem host id 13.

Change-Id: I48c7e576d3478bdc4645c44aa435900f3eaaa2c4
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
2020-10-19 11:53:06 +05:30
Santosh Mardi
8616e29d2c drivers: soc: qcom: fix incorrect updation of pmu cache flag in CPU_PM_EXIT
rimps_memlat driver will cache PMU counter values when cpu
is going down in hotplug path and also when CPU is entering
lpm. Once the PMU counter values are saved to the shared memory,
cache valid bit is set, and it is cleared when cpu comes back online
or exit from lpm.

RIMPS expects the PMU cache flag to be valid, when cpu is offline
or entered lpm. Observed a race when the hotplug is in progress
and that particular cpu can enter and exit lpm. The current
implementation clears the cache flag during lpm exit without
checking the cpu hotplug status. Once hotplug is complete, core
goes offline and the status flag will remain in incorrect state
indicating cache area is invalid, which will cause RIMPS to read
PMU counter values directly from hardware which will result in APB
read errors.

When hotplug is in progress, do not set status flag to
PMU_CACHE_INVALID in CPU_PM_EXIT path.

Change-Id: I17947ad93eeef99b2148e873dc719622aa372b7c
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:36:04 +05:30
Santosh Mardi
67838f80cd drivers: soc: qcom: allow setup of pmu events during hotplug
Setup pmu counter functions of rimps memlat driver check cpu_is_hp
flag before creating counters, and the setup of pmu counters will
be called in two places one in probe and other when cpu is coming
up from hotplug path.

The hotplug path will clear cpu_is_hp after the pmu setup calls are
issued, but pmu setup function will not create pmu events as the
cpu_is_hp flag not cleared at this point, this results in pmu
counters not getting setup even cpu is up from the hotplug path.

Add a parameter to these functions indicating from which path these
are called and update the logic accordingly to allow creation of
pmu events when core is coming up.

Change-Id: I8bf8d52d91d14ab3f4d837271055f03e704e98a0
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:36:03 +05:30
Santosh Mardi
cbcfe29a9d drivers: soc: qcom: use hw counter values for PMU snapshot to RIMPS
RIMPS memlat driver reads the current PMU counter value
using perf_event_read_local() API at the time of core
going offline or entering LPM and saves the current
snapshot to a shared memory for access by RIMPS.

RIMPS reads these values from the shared memory when
core is offline or in LPM state, and reads directly
from PMU hardware when core is online. The value read
from hardware and the one read from shared memory are
going out of sync because perf event driver limits the
counting range of PMU counter to half of the total range
supported by hardware, and it configures the counter to
start counting from midpoint at the time of counter reset
and upon overflow. It keeps adding the delta read from
hardware counters to software maintained counters and it
returns the same through perf_event_read API.
As this is not the exact same value as what is read from
hardware counters, the values read by RIMPS from shared
memory are going out of sync.

To address this get the current snapshot of hardware counter
value from prev_count member of hw_perf_event structure which
is part of perf_event structure, and store that to shared memory.

Change-Id: I71f416270a02f7925b16e576f637cf3579fec6ce
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:35:52 +05:30
Santosh Mardi
2cb80d18ee drivers: soc: qcom: code clean up for rimps_memlat driver
Remove unused variable in hotplug path.

Change-Id: Ida006e8f39adc741ee63f63cdddcb51ddd2804f1
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 03:24:43 -07:00
Santosh Mardi
dc4268916b drivers: soc: qcom: Handle CPU_PM_ENTER_FAILED notification
Mark PMU cache invalid if CPU_PM_ENTER fails.

Change-Id: Ieb2d34fcd94b99972443a3ade0458f9955281ffe
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 03:24:21 -07:00
qctecmdr
d77ee90deb Merge "defconfig: msm: Enable qfprom_sys for Lahaina GKI" 2020-10-16 22:07:17 -07:00
qctecmdr
03e52f59a8 Merge "clk: qcom: debugcc: Update register offset for debug mux" 2020-10-16 18:49:20 -07:00
qctecmdr
e12ac54b46 Merge "defconfig: sdxlemur: Enable RPMh and GPIO regulators" 2020-10-16 18:49:19 -07:00
qctecmdr
f11438db40 Merge "defconfig: sdxlemur: Enable LLCC driver on sdxlemur" 2020-10-16 18:49:19 -07:00
Melody Olvera
9cc45909c1 defconfig: sdxlemur: Enable LLCC driver on sdxlemur
This change enables LLCC driver on sdxlemur.

Change-Id: Ife2eb2c8ea5c4b5190cc58f882a72c525f6b0163
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2020-10-16 10:36:36 -07:00
Jeevan Shriram
c2d1b1bf9e drivers: llcc: Add LLCC driver for sdxlemur target
Add Last Level Cache Controller (LLCC) driver for sdxlemur platform.

Change-Id: I5fe907c6ed6dd2863e6488dac42e0c352ca48f48
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
2020-10-16 10:36:29 -07:00
Melody Olvera
f7101cee8b drivers: llcc: Allow configurations with no broadcast hardware
Previous iterations of the llcc driver did not account for caches with
no llcc broadcast hardware. This fixes this issue.

Change-Id: I221d0d65d17c34645cd1a4070737fe9bebfa4b16
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2020-10-16 10:32:29 -07:00
qctecmdr
1ca2f08101 Merge "msm-perf: Removed game active status node" 2020-10-16 10:09:28 -07:00
qctecmdr
557b8f8282 Merge "usb: f_gsi: Memory optimization for buffers on gsi for low MEM variants" 2020-10-16 10:09:28 -07:00
qctecmdr
c8b9369a28 Merge "USB: f_fs: Fix epfile crash during composition switch" 2020-10-16 10:09:27 -07:00
qctecmdr
cd758fb1b9 Merge "usb: dwc3-msm: Add interconnect bus voting through dt-node" 2020-10-16 10:09:26 -07:00
qctecmdr
060b3e941e Merge "net: config: Enabling SYN_COOKIES config option for lahaina target" 2020-10-16 10:09:26 -07:00
qctecmdr
6e67ceb99f Merge "defconfig: holi-gki: Enable CDSPRM driver" 2020-10-16 10:09:26 -07:00
qctecmdr
ce9c398026 Merge "input: touchscreen: mxt: refine power on/off flow" 2020-10-16 10:09:26 -07:00
Naveen Yadav
25738f2916 clk: qcom: debugcc: Update register offset for debug mux
Update the register offsets for the debug mux to measure
the clock frequency correctly.

Change-Id: I329f3f3416d6b097e0fc38e72d136a5b21db7049
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
2020-10-16 18:59:02 +05:30
Paras Singh Jain
5f73483da2 net/embms-kernel : EMBMS Tunneling Module
This module is used to tunnel multicast
packets received on an interface to WLAN
clients which have registered for these
packet streams. Mainly used to tunnel
EMBMS packets received on TMGI streams.

Change-Id: I1cea29bff192d375317dda3d1baebb594e0b9c39
Acked-by: Raju Velpula <rvelpula@qti.qualcomm.com>
Signed-off-by: Paras Singh Jain <parassin@codeaurora.org>
2020-10-16 18:23:27 +05:30
Pradeep P V K
45a05399cf mmc: sdhci-msm: Pass min and max voltage values to enable regulators
Pass minimum and maximum voltage values while enabling regulators.

Change-Id: I3de7f343cd0d8fd1953fa5d091c411c013a0dd29
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
2020-10-16 04:46:04 -07:00
Ram Prakash Gupta
674da8208b mmc: Enable clk scaling for cqe
Enable clk scaling for cqe.

Change-Id: I99e87a808e4d7663114736e45614a8082dda0eb1
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
2020-10-16 15:52:56 +05:30
Bavyasritha Alahari
e543f305ad defconfig: holi-gki: Enable CDSPRM driver
CDSPRM module implements a RPMSG interface to communicate with CDSP
while providing a way for CDSP to vote for CPU QoS to benefit CDSP
applications performance.

Change-Id: Ib2627e611b3d4e25f68b7ecee672d4a6474050c3
Acked-by: Sreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: Bavyasritha Alahari <alahari@codeaurora.org>
2020-10-16 12:02:27 +05:30
Chinmay Agarwal
bbe4ddc207 net: config: Enabling SYN_COOKIES config option for lahaina target
Enabling SYN_COOKIES config to allow multi stream tcp scenarios to
connect simultaneously.

Change-Id: Idaf6ef9faf8df33df834ce7fbcbd63b91887f934
Signed-off-by: Chinmay Agarwal <chinagar@codeaurora.org>
2020-10-16 11:05:49 +05:30
Pratham Pratap
1b64983eb0 usb: dwc3: core: Add ipc logs when sg lists are used
Currently ipc_logging will capture the usb request's dma address but
when sg list is used usb request's dma address is not populated. This
change adds start_sg's dma address which is populated when sg list is
used for usb transfers. Also increase the number of log pages to capture
more ep events.

Change-Id: I36ada11429e168e2d3d09cf3427b1f3bcdacc285
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
2020-10-15 21:59:57 -07:00
qctecmdr
6998de7d04 Merge "mmc: core: Set reset done after hw reset" 2020-10-15 17:09:24 -07:00
qctecmdr
0b7aa5a74c Merge "iommu: arm-smmu: domain power on arm_smmu_map/map_sg" 2020-10-15 17:09:23 -07:00
qctecmdr
e308a4d511 Merge "iommu: iommu-debug: align iova before mapping" 2020-10-15 17:09:23 -07:00
qctecmdr
6e14331c56 Merge "input: touchscreen: focaltech: queue touch suspend work on workqueue" 2020-10-15 17:09:23 -07:00
qctecmdr
22c40c4905 Merge "haven: hh_msgq: add MSGQ label for display" 2020-10-15 17:09:23 -07:00
Aman Mehta
0ef671a26e msm-perf: Removed game active status node
Removed the support for game status node to specifically compare
for gfx events, the same is archived with checking the value of pid.
This saves an extra fops on each iteration for game on and off.

Rejecting events with timestamp = 0.

Change-Id: Icbafc4d1f8fa1e444b9074fcf2fde47a6e85d609
Signed-off-by: Aman Mehta <amanmeht@codeaurora.org>
2020-10-15 10:22:59 -07:00
qctecmdr
ccbf386326 Merge "f2fs: handle errors of f2fs_get_meta_page_nofail" 2020-10-15 08:45:49 -07:00
qctecmdr
742ed2a741 Merge "defconfig: sdxlemur: Enable CNSS platform driver" 2020-10-15 08:45:49 -07:00
qctecmdr
d659404b98 Merge "mmc: sdhci-msm: Add support for gcc hw reset for sdcc" 2020-10-15 08:45:48 -07:00
qctecmdr
10404900a1 Merge "Firmware: arm_scmi: Add #ifdef guards for vendor extensions" 2020-10-15 08:45:48 -07:00
Sandeep Singh
00410da99c icnss2: Avoid sending fw down uevent to wlan driver twice
Avoid sending fw down uevent to wlan driver twice for
one ssr/pdr.

Change-Id: I9c99b16c3760ef7b432df16b2f326db39371e3c3
Signed-off-by: Sandeep Singh <sandsing@codeaurora.org>
2020-10-15 19:57:37 +05:30
Neeraj Upadhyay
0071fbbdb1 defconfig: msm: Enable qfprom_sys for Lahaina GKI
Enable qfprom_sys as module in Lahaina gki defconfig.

Change-Id: I91d0c9e3883d130ca7ed51c12aa96581950e09db
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
2020-10-15 18:09:11 +05:30
qctecmdr
74d363dba8 Merge "soc: qcom: msm_perf: Allow freq updates regardless of policy" 2020-10-15 05:37:58 -07:00
qctecmdr
abe544901b Merge "msm: kgsl: Don't allow re-importing memory owned by KGSL" 2020-10-15 05:37:57 -07:00
qctecmdr
b4b4cb7340 Merge "usb: dt-bindings: Add USB 5NM QMP PHY register macros" 2020-10-15 05:37:57 -07:00
qctecmdr
899c0b5bc8 Merge "rpmsg: glink: Remove channel decouple from rpdev release" 2020-10-15 05:37:57 -07:00
qctecmdr
6fe5f956c4 Merge "defconfig: enable config to add QTI specific code for sdxlemur" 2020-10-15 05:37:56 -07:00
Fei Mao
d35c6d58eb input: touchscreen: mxt: refine power on/off flow
Refine driver's power on/off flow and make regulators' state
to be proper in all scenes.

Change-Id: I5d26c3134dfbdc53037fe4aac16739b24c0c183b
Signed-off-by: Fei Mao <feim1@codeaurora.org>
2020-10-15 18:09:15 +08:00