Commit graph

898,925 commits

Author SHA1 Message Date
qctecmdr
1cbc9f171d Merge "iio: qcom-spmi-adc5: Add AMUX2_GPIO channel to rev2 channel list" 2021-04-29 21:27:42 -07:00
qctecmdr
db135d0e62 Merge "dt-bindings: msm: Add binding for OT Fuse support" 2021-04-29 21:27:42 -07:00
qctecmdr
c4ff6bd5b5 Merge "msm: kgsl: Initialize local variable" 2021-04-29 21:27:41 -07:00
qctecmdr
3ddaf4eb3f Merge "msm-5.4 : net: SIP Segmentation incase of TCP" 2021-04-29 21:27:40 -07:00
Paras Jain
c9d00ac7e0 netfilter: Port Trigger: Support added for Port Trigger Feature
With Port Trigger feature, the DL traffic forward ports get opened
once the UL traffic is sent on respective trigger ports.

Change-Id: I7fc67a48ab4d079aa3e7c1b5fa81b4611f54493f
Acked-by: Vinisha Varre <vvarre@qti.qualcomm.com>
Signed-off-by: Paras Jain <parassin@codeaurora.org>
2021-04-30 05:19:34 +05:30
Ram Chandrasekar
743b6cc02e defconfig: sdxlemur: Enable thermal drivers
Enable thermal framework features and other thermal drivers like QMI
sensor and mitigation driver for sdxlemur.

Change-Id: I1e4a45ada65b3bff83cfc902cc059547787fbce2
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2021-04-29 08:48:59 -07:00
Ram Chandrasekar
7cece1c6dc drivers: thermal: qmi_sensor: Add support for new sensors
Add support for new QMI sensors. Here is the list of sensors that are
newly added,
qtm_therm
modem_bcl_warn
sdr0_pa0
sdr0_pa1
sdr0_pa2
sdr0_pa3
sdr0_pa4
sdr0_pa5
sdr0
sdr1_pa0
sdr1_pa1
sdr1_pa2
sdr1_pa3
sdr1_pa4
sdr1_pa5
sdr1
mmw0
mmw1
mmw2
mmw3
mmw_ific0

This will enable these sensors to be registered with thermal framework.

Change-Id: I5ea49478afee82f7058247ee7e0e505955423e72
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2021-04-29 08:48:54 -07:00
Sneh Shah
701109ad7a net: stmmac: Return from smmu platform remove and depopulate pdev
Return from smmu pdev remove and depopulate pdev.

Change-Id: I82ab6a8feebdc2eafa45019b5d3d754c6af99308
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
2021-04-29 16:01:34 +05:30
Naman Padhiar
578ed3c90d icnss2: Add support for MHI state info
Read MHI state from MSA and export API to get MHI state.
Add SMP2P handshakes according to below sequence to manage
PCI EP low power state.
1. Host driver calls prevent_l1.
2. ICNSS sends SMP2P to FW with PCI_EP_POWER_SAVE_EXIT.
3. FW bring EP out of power save and update in memory
   location.
4. Once Host reads updated value it access registers.
4. Host driver calls allow_l1.
5. ICNSS send SMP2P to FW with PCI_EP_POWER_SAVE_ENTER.

Change-Id: Ia93a270cbe86d1fb7c8402c69eb9b64b1400abb6
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
2021-04-29 13:32:46 +05:30
Sachin Kumar Garg
7a30b2cef9 arm: defconfig: Add video h/w accelerators support for MONACO
Enable video h/w accelerators for MONACO.

Change-Id: Id5fe45d010d7f8a02c9af0ad778cc8a9a8bd47bf
Signed-off-by: Sachin Kumar Garg <sachinku@codeaurora.org>
2021-04-29 12:50:37 +05:30
Deepak Kumar Singh
32933046af rpmsg: glink: mark intent request complete before wake up
Channel release function is not making intent wait condition true
before calling wake_up, due to this thread waiting on intent is
stuck and does not wake up until timeout happens. By this time
channel context is freed and this casues finish wait to fail due
to access of wait queue in freed channel context.

Mark intent request complete before calling wake_up.

CRs-Fixed: 2914979
Change-Id: Ia4162c9e62f0f5a7bd04ca0e09c2cd58319ef341
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
2021-04-29 11:42:22 +05:30
Sriharsha Allenki
8e8dbca45a pci: msm: Disable access to MSI config as part of suspend
Some platforms do not support DRV suspend and resume.
On these platforms the access to MSI config is not
prevented as part of suspend leading to NOC faults.
Fix this by preventing the access to the same as part
of suspend, and allowing it as part of resume.

Change-Id: I435d9f1bad3843154f5a4ebff21cd8e358802817
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
2021-04-29 11:13:20 +05:30
Santosh Mardi
e5c82d7b7c drivers: soc: qcom: rimps_memlat: add NULL check for SCMI handle
SCMI handle will remain NULL in case of SCMI failures during
initialization.

Update all store functions to check for NULL before accessing
vendor ops structure.

Change-Id: Ied56f62785579078fb06fb526e29aaef9d45e00d
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2021-04-28 22:29:14 -07:00
Ashish Chavan
f62bc5be51 power: supply: smblite: Add support for concurrency mode
Add an interface to enable/disable boost concurrency. When
enabled the charger in buck-mode can act as a boost over a
separate path. The feature is supported only on PM5100 and
can be enabled using "qcom,concurrency-mode-supported" flag.

Change-Id: I3ab78af2123add2c4d5cba96500e1576b3c7deb3
Signed-off-by: Ashish Chavan <ashichav@codeaurora.org>
2021-04-29 10:29:49 +05:30
wadesong
72155bb8e2 msm-5.4: Auto pcie aspm config propagation
Propagate the pcie aspm settings from original auto (both metal
and gvm) defconfigs to make sure they're aligned with the
settings on top of the newly adopted kernel branch.

Change-Id: I260cd9b236e715183d11bbc3e625641b57c93ee8
Signed-off-by: wadesong <wadesong@codeaurora.org>
Signed-off-by: Hans Chang <hansc@codeaurora.org>
2021-04-28 21:47:52 -07:00
Jishnu Prakash
25000642a4 defconfig: Enable ADC_TM for sdxnightjar
Enable ADC_TM driver for sdxnightjar.

Change-Id: I71c74eecf6bc2721ac53a11bf3008a065ebb64ed
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2021-04-29 09:40:46 +05:30
Can Guo
7149f8914f msm: ep-pcie: Give BAR0 and BAR2 the right size
dev->mmio_res_size is not initialized, so during D3_COLD -> D0 transition,
when the driver re-initializes the BAR registers, they are overwritten by
dev->mmio_res_size. Fix it by calculating the size of MMIO resource and
using the calculated size in ep_pcie_bar_init().

Change-Id: Ifad54ed1ffbcf205e89f9ab6d54e54350d5e7788
Signed-off-by: Can Guo <cang@codeaurora.org>
2021-04-29 12:01:56 +08:00
qctecmdr
55572f84cc Merge "iio: adc: Add QCOM SPMI PMIC5 GEN3 ADC driver" 2021-04-28 17:58:46 -07:00
qctecmdr
489d62a621 Merge "defconfig: autogvm: Enable boot stats and boot marker" 2021-04-28 17:58:46 -07:00
qctecmdr
4df76a611c Merge "msm: ipa3: support dymaic nf pkt-threshold change" 2021-04-28 17:58:46 -07:00
qctecmdr
180a53c7c1 Merge "QCMAP: Packet counters are not updated in conntrack" 2021-04-28 17:58:46 -07:00
qctecmdr
c72a3aa209 Merge "Port Trigger Config" 2021-04-28 17:58:45 -07:00
qctecmdr
095e984b70 Merge "cnss2: Add support to retry with a list of PCIe RC ports" 2021-04-28 17:58:45 -07:00
Yue Ma
5bb387ed02 cnss2: Add support to retry with a list of PCIe RC ports
If PCIe enumeration fails with primary PCIe RC port, retry with
other PCIe RC ports if any in the list from device tree using
the same logic.

Change-Id: I4e803f74dfeda914a9944ab2d14a4055fc223301
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-04-28 13:40:57 -07:00
Paras Jain
5be87b2ffa Port Trigger Config
Config change for enabling Port Trigger Feature

Change-Id: Ibd75ffd6346b10a4d666363e2e657c1cdb073b94
Acked-by: Vinisha Varre <vvarre@qti.qualcomm.com>
Signed-off-by: Paras Jain <parassin@codeaurora.org>
2021-04-29 01:06:48 +05:30
Paras Jain
a64c3b212f QCMAP: Packet counters are not updated in conntrack
Return value of counter api returns s64 instead of u64
Type-casting to the right type.

Change-Id: I8f399ccd52ec4e4f4b23d39f3faa7bb6f23262cc
Acked-by: Vinisha Varre <vvarre@qti.qualcomm.com>
Signed-off-by: Paras Jain <parassin@codeaurora.org>
2021-04-28 12:32:55 -07:00
Jilai Wang
5a3d3c05c5 msm: npu: update uapi header file to align with 4.14/4.19 kernel
This change is to update npu driver's uapi header file to align
data structures' definition same as those in 4.14 and 4.19 kernel
which allows the user application to be used on different kernel
version.

Change-Id: I426308c98f058981517aa46fd2475a5a137f548f
Signed-off-by: Jilai Wang <jilaiw@codeaurora.org>
2021-04-28 15:30:16 -04:00
Skylar Chang
d7a0a85fe9 msm: ipa3: support dymaic nf pkt-threshold change
Add the support for user-space module to dynamically
enable or disable nf pkt threshold values to decide
traffic going to ipa offload or not.

Change-Id: I00871464d4058d51e1551fd6275c82483d86f934
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2021-04-28 09:52:45 -07:00
Anant Goel
5ad46bb7d4 clk: qcom: Add PCIe clocks to Direwolf VM
Add support for virtual clocks needed for PCIe RCs
2a, 2b, 3a, 3b, and 4, to the Direwolf VM.

Change-Id: I73002071c18f85d8cbcb15c06e030650d10dc5b9
Signed-off-by: Anant Goel <anantg@codeaurora.org>
2021-04-28 09:32:02 -07:00
Venkata Rao Kakani
efd1b58bf4 defconfig: autogvm: Enable boot stats and boot marker
Enable boot stats driver and boot time marker config
options for Linux GVM targets.

Change-Id: Iaf05a6d61b820b88f849f550eebaefb150834948
Signed-off-by: Venkata Rao Kakani <vkakani@codeaurora.org>
2021-04-28 21:04:45 +05:30
Vivek Pernamitta
e6716d048b mhi: msm: Abort RDDM dump collection in PBL state
Abort RDDM dump collection through __mhi_download_rddm_in_panic()
when device is in PBL state.

Change-Id: Ic2b5b9be79523881fca5c37dd1a3e1264bfa3829
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
2021-04-28 20:44:37 +05:30
Akhil P Oommen
76e3267cd1 msm: kgsl: Expose memtype stats through sysfs
Expose the per-process memory usage of each memtype through kgsl
sysfs interface.

Change-Id: Ifbc729f321d2d2e596f33f1c76c21f0894362316
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
2021-04-28 18:34:13 +05:30
Paul Zhang
b1e616299d defconfig: sdmsteppeauto: enable cnss module
Enable cnss module to bring up wlan for sdmsteppeauto.

Change-Id: I2caf794303a2517c63d6e2d06a62d94db830cb4c
Signed-off-by: Paul Zhang <paulz@codeaurora.org>
2021-04-28 17:59:45 +08:00
Komal Bajaj
f2049e6626 soc: qcom: Add check to handle out of bound access
Adding check in msm_minidump_add_region() to handle scenarios for
out of bound access while adding region in minidump table in SMEM.

Change-Id: Ic20663dbd2fa8ae96899930a7f7ba79dc204ff5e
Signed-off-by: Komal Bajaj <kbajaj@codeaurora.org>
2021-04-28 02:28:29 -07:00
Lei wang
f7886d93bf hwrng: refine hwrng delay for retry
Per internal test, about 5us-6us is enough for hwrng prepare
the random data. 440us udelay is much more then needed, So
reduce the udelay time for better performance.

Change-Id: I714b67ca6e4f97717db537c799936ea31c96e475
Signed-off-by: Lei wang <leiwan@codeaurora.org>
2021-04-27 22:54:17 -07:00
qctecmdr
37a1126894 Merge "ion: implement interface to export total_pools_kb" 2021-04-27 22:49:33 -07:00
qctecmdr
9a82131643 Merge "neighbour: Prevent Race condition in neighbour subsytem" 2021-04-27 22:49:33 -07:00
qctecmdr
708dde5b10 Merge "arm64: defconfig: Add support for GPUCC, DISPCC and DEBUGCC for BLAIR" 2021-04-27 22:49:32 -07:00
qctecmdr
36666de1db Merge "drivers: qcom: Add declaration of msm_timer_get_sclk_ticks" 2021-04-27 22:49:32 -07:00
qctecmdr
733e5740b2 Merge "usb: dwc3: gadget: Handle race between remove_request & ep_dequeue" 2021-04-27 22:49:31 -07:00
Paras Jain
d23ca84eae msm-5.4 : net: SIP Segmentation incase of TCP
- This change prevents kernel crash in case of SIP Segmentation over TCP.

Change-Id: I1be0546aaf8c68981aab1285c9081deaf4844427
Signed-off-by: Paras Jain <parassin@codeaurora.org>
2021-04-28 10:36:54 +05:30
Shreyas K K
63f476db34 defconfig: Enable LLCC PMU on Direwolf target
Enable LLCC PMU for monitiring and measuring various
LLCC events on Direwolf target.

Change-Id: I8d9f8ad889140c2c21f8c63dc8774307ebbe2c88
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-04-27 21:45:44 -07:00
Shreyas K K
cb77a26232 defconfig: Enable Socinfo driver on Direwolf target
Enable Socinfo driver support on Direwolf target.

Change-Id: Ic148b9e7bdb25950ee9be26ceaae38d4a0261eb7
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-04-27 21:45:39 -07:00
Shreyas K K
244996a62c drivers: qcom: socinfo: Add Direwolf SoC IDs
Add Direwolf SoC IDs for SC, IVI, and ADAS platform.

Change-Id: I6b8263921eca2781c5903c2316bb60bc0273c290
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-04-27 21:45:34 -07:00
Shreyas K K
888f7fc66d defconfig: Enable LLCC support on Direwolf target
Enable QCOM_LLCC to allow clients to use the last level
cache controller block.

Change-Id: Ic63669cb395097198bfd6f2822955d5f3d521215
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-04-27 21:45:26 -07:00
Shreyas K K
62d5c1cb69 drivers: qcom: Add LLCC driver for Direwolf platform
Add Last Level Cache Controller driver for Direwolf
platform.

Change-Id: I489d5053495653f66ecd788faa441434d2c209dd
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-04-27 21:45:18 -07:00
Madhuri Medasani
72d803fccf clk: qcom: gcc-blair: Remove support for GCC_PRNG_BCR
Remove support for GCC_PRNG_BCR.

Change-Id: I734f69d68955caa263c4a9aeea582cd799997328
Signed-off-by: Madhuri Medasani <mmedasan@codeaurora.org>
2021-04-28 10:07:25 +05:30
Ayush Kumar
8ae4d4b15b dt-bindings: msm: Add binding for OT Fuse support
Add dt binding macro for OT enable disable control
through fuse feature.

Change-Id: I0ba3db518843ec4ae92e6fa464b6b474b027f0a5
Signed-off-by: Ayush Kumar <ayushkr@codeaurora.org>
2021-04-28 09:58:48 +05:30
qctecmdr
5e999608a4 Merge "llcc: Overcome unused function warnings when CONFIG_QCOM_LLCC is not enable" 2021-04-27 20:12:57 -07:00
qctecmdr
511c300659 Merge "defconfig: gen3auto: Enable Lock and RCU debugging" 2021-04-27 20:12:57 -07:00