Commit graph

892,328 commits

Author SHA1 Message Date
qctecmdr
a1702cebeb Merge "spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout" 2020-11-19 06:55:49 -08:00
qctecmdr
2113e65f7b Merge "drivers: thermal: qmi_sensor: Add support for extended sensor list" 2020-11-19 06:55:48 -08:00
qctecmdr
376dd78d67 Merge "defconfig: Enable USB BAM on sdxlemur" 2020-11-19 03:06:15 -08:00
qctecmdr
bba65054f1 Merge "mm: Kconfig: Add support for config size of purging vmap_area" 2020-11-19 03:06:14 -08:00
qctecmdr
5cc19bc1b5 Merge "sched: Fix "releasing a pinned lock" lockdep warning" 2020-11-18 22:31:08 -08:00
qctecmdr
d9b738bc54 Merge "ion: Check for valid vmids for msm system heap" 2020-11-18 22:31:07 -08:00
qctecmdr
2da0027008 Merge "msm: ipa3: Define ipa_get_wdi_version method" 2020-11-18 22:31:07 -08:00
qctecmdr
4a9a5a5300 Merge "pci: msm: Dump PCIe registers to debug linkdown" 2020-11-18 22:31:07 -08:00
qctecmdr
6dd629487f Merge "mmc: core: Add debug enhancement logs" 2020-11-18 01:48:37 -08:00
qctecmdr
070943a3f7 Merge "fsa4480: Resolve euro usb analog headset detect issue after PDR" 2020-11-18 01:48:37 -08:00
Pavankumar Kondeti
c83a851f7d sched: Fix "releasing a pinned lock" lockdep warning
WALT requires both src and dst runqueue locks to be held
during migration. So a double_lock_balance() is added
in move_queued_task() before calling set_task_cpu(). However,
releasing the src rq lock, which is pinned is giving a
lockdep warning. Fix this by unpinning the lock before
calling double_lock_balance.

Change-Id: I64dec0701b3467185cf53f311ebb521c6a822e88
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2020-11-18 08:58:35 +05:30
qctecmdr
ce480240e1 Merge "dt-bindings: clock: Update clock ids of GPUCC for YUPIK" 2020-11-17 17:05:50 -08:00
qctecmdr
03d0199dd1 Merge "dma: gpi: Correct the return code in dmaengine_pause api" 2020-11-17 17:05:50 -08:00
qctecmdr
53c40d0501 Merge "mmc: sdhci-msm: Use auto suspend instead of sync" 2020-11-17 17:05:49 -08:00
qctecmdr
37c562ad9d Merge "mmc: sdhci-msm: Set PWRSAVE bit to '0' during tuning" 2020-11-17 17:05:49 -08:00
qctecmdr
b414bf80c4 Merge "tzlog: Update structs as per the new requests" 2020-11-17 17:05:49 -08:00
qctecmdr
756b932c44 Merge "serial: msm_geni_serial: Add enable/disable of dma irq bits" 2020-11-17 17:05:48 -08:00
qctecmdr
6652990708 Merge "msm: kgsl: Increase MAX_PWRLEVELS Limit" 2020-11-17 17:05:48 -08:00
qctecmdr
61717f9f5f Merge "soc: qcom: msm_perf: enable msm_perf driver on default config" 2020-11-17 17:05:48 -08:00
qctecmdr
2f8aed210e Merge "msm: msm-geni-se: Add proxy votes to fix earlycon crash" 2020-11-17 17:05:47 -08:00
qctecmdr
49b2e4a13c Merge "f_fs: fix scheduling while atomic issue of ffs_epfile_io()" 2020-11-17 13:29:01 -08:00
qctecmdr
55b65a4d60 Merge "defconfig: sdxlemur: Allow writing to regmap only on debug builds" 2020-11-17 13:29:01 -08:00
qctecmdr
4c48eb3326 Merge "icnss2: Avoid sending qdss_trace_mem_info to fw if it is down" 2020-11-17 13:29:00 -08:00
qctecmdr
003a1824ff Merge "msm: kgsl: Properly set fault bit in adreno_set_gpu_fault" 2020-11-17 13:29:00 -08:00
qctecmdr
2129bf638c Merge "cfg80211: Add support to calculate and report 4096-QAM HE rates" 2020-11-17 13:29:00 -08:00
qctecmdr
f6b4905d47 Merge "input: touchscreen: mxt: remove disable_irq" 2020-11-17 13:28:59 -08:00
qctecmdr
9a71644291 Merge "i2c: i2c-msm-geni: Wait for abort command completion" 2020-11-17 13:28:59 -08:00
Pooja Kumari
63b2502945 msm: ipa3: Define ipa_get_wdi_version method
Define ipa_get_wdi_version method in framework
context to get wdi version.

Change-Id: I4ba2a340bfa33eb089da40f1b7460d3395c365f4
Signed-off-by: Pooja Kumari <kumarip@codeaurora.org>
2020-11-17 09:01:14 -08:00
qctecmdr
e915fc5948 Merge "msm: kgsl: Add a Kconfig setting for GPU idle timeout" 2020-11-17 05:57:29 -08:00
qctecmdr
c496ba6c04 Merge "arm: defconfig: Enable QRTR MHI for sdxlemur" 2020-11-17 05:57:29 -08:00
qctecmdr
fee2b06454 Merge "icc: dt-bindings: add endpoint IDs for interconnects for SM8150" 2020-11-17 05:57:29 -08:00
qctecmdr
704966b60e Merge "cnss2: Avoid suspending PCIe after QMI send get is called" 2020-11-17 05:57:29 -08:00
qctecmdr
e2f18ef14c Merge "defconfig: Enable relay fs for lahaina" 2020-11-17 05:57:28 -08:00
qctecmdr
75d5a41f25 Merge "usb: misc: nb7vpq904m: disable chip when boot up without cable" 2020-11-17 05:57:28 -08:00
qctecmdr
8c62bda756 Merge "msm: pcie: correct PCIe target link speed mask macro" 2020-11-17 05:57:28 -08:00
qctecmdr
bba465d5c1 Merge "Add support for EMMC storage type" 2020-11-17 05:57:27 -08:00
Vipin Deep Kaur
0070266e70 spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout
Propagate a change from 4.19 to 5.4 for SPI. 'commit 556e7c13ceaa
("spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout")'.

Change-Id: Ica785f7b3cd3a9f9df6d173413ce136c2a018312
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
2020-11-17 14:11:03 +05:30
Vivek Pernamitta
9c31f04cf2 pci: msm: Dump PCIe registers to debug linkdown
Support to dump PARF,PHY,DBI/dm_core registers
for PCIe linkdown.

Change-Id: I54a19245e91e68f0d58f230509e6cb1a2ff02665
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
2020-11-17 12:37:22 +05:30
Shaik Sajida Bhanu
832d9eaf5b mmc: core: Add debug enhancement logs
Add debug enhancement logs to notify request timeout, when cqe is
turned off and when deferred scaling happens.

Change-Id: Ib499f41632427cba3ab0b67e04d605b6cf4419f5
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
2020-11-17 11:25:16 +05:30
Vijayanand Jitta
cae595f476 ion: Check for valid vmids for msm system heap
Add a check for valid vmids before doing an allocation
for msm system heap. This check does a hyp_assign on a
page, stores the vmids and mark them as valid or invalid
based on hyp_assign result. If vmid is invalid it returns
or if its valid then proceeds with the allocation. So, this
prevents ion pages leak in cases where hyp_assign fails.
Also add a check for ion_hyp_assign_sg return value to
prevent leak.

Change-Id: Ibbc150490daf69d27b36db0e45a3c58496e6b9bd
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
2020-11-17 09:35:35 +05:30
qctecmdr
5f551b3328 Merge "Kconfig: have ENABLE_VMALLOC_SAVING depend on QGKI" 2020-11-16 19:15:08 -08:00
qctecmdr
4104c0f498 Merge "input: touchscreen: focaltech: toggle reset gpio during error" 2020-11-16 19:15:08 -08:00
qctecmdr
8b249d7cb9 Merge "Merge android11-5.4.61+ (dc2d5a0) into msm-5.4" 2020-11-16 19:15:08 -08:00
Kishore Sri venkata Ganesh Bolisetty
206e048a12 soc: qcom: msm_perf: enable msm_perf driver on default config
carve out frequency boost functionality of msm_perf driver
and enable it on non perf images too.

Change-Id: I2a0af988edf04a88d2fc16018f50830a0ab73220
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <bsrivenk@codeaurora.org>
2020-11-16 14:35:54 -08:00
Guru Das Srinagesh
6c3524dd68 defconfig: sdxlemur: Allow writing to regmap only on debug builds
For security reasons, allow modifying register values via the regmap
debugfs interface only on debug builds.

Change-Id: Ie22dbb2ff72da2072d46ab1116fb9623fe2185ff
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
2020-11-16 09:07:35 -08:00
Vatsal Bucha
1ca159a38c fsa4480: Resolve euro usb analog headset detect issue after PDR
Euro headset is sometimes detected as headphone post PDR.
This is due to race condition between powering up of PGA
and cross connection detection due to which cross conn
detection is not successful resulting in usb analog headset
being detected as headphone post PDR. Save switch_control
value before PDR and apply same value during fsa reg notifier
after PDR so that euro side does not detect as cross conn
post PDR to resolve issue.

Change-Id: I4af17d83a8e4a55185421b370162d8e7a5d5b91f
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2020-11-16 02:08:00 -08:00
Veera Vegivada
48bfd0d68c icc: dt-bindings: add endpoint IDs for interconnects for SM8150
Add master and slave ID constants for all Qualcomm Technologies, Inc.
SM8150 interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: Ie3d92159bf34e2cd57873cd3cd85c75e6a62638a
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-11-16 11:45:30 +05:30
Anmolpreet Kaur
bbe813c8f7 tzlog: Update structs as per the new requests
Update structs as per the new requests.

Change-Id: Idea5ebdf6c558b4a2e26031334f47eb7914a0615
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
2020-11-16 11:41:54 +05:30
Vamsi Krishna
5301754193 cfg80211: Add support to calculate and report 4096-QAM HE rates
Drivers supporting 4096-QAM rates as a vendor extension in HE mode need
to update the correct rate info to userspace while using 4096-QAM (MCS12
and MCS13) in HE mode. Add support to calculate bitrates of HE-MCS12 and
HE-MCS13 which represent the 4096-QAM modulation schemes. The MCS12 and
MCS13 bitrates are defined in IEEE P802.11be/D0.1.

In addition, scale up the bitrates by 3*2048 in order to accommodate
calculations for the new MCS12 and MCS13 rates without losing fraction
values.

CRs-Fixed: 2796770
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
Signed-off-by: Jouni Malinen <jouni@codeaurora.org>
Link: https://lore.kernel.org/r/20201029183457.7005-1-jouni@codeaurora.org
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: 9c97c88d2f4b221d99491c3196da42004c195fb5
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
Change-Id: I44f71f40a57b57703bbbe138e690d6f92369d0ec
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
2020-11-16 11:08:52 +05:30
qctecmdr
58329ca148 Merge "clk: qcom: Add the debug mux information for SM8150" 2020-11-15 17:44:56 -08:00