Enable CONFIG_DEBUG_SPINLOCK to debug issues with respect to
deadlocks on Lahaina platforms.
Change-Id: I9599e3478118c1decdfe7a0b2c76064e710ef9f3
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
The SELinux policy on Android doesn't provide the kernel-space
with CAP_SYS_ADMIN capability. The perf-core checks for this
capability before giving access to the callers to read the PMU
counters. Hence, when the kernel drivers try to gain access
to the PMU (via perf_event_create_kernel_counter()), it fails
with -EACCES.
To get past this, add another condition to check if the request
is coming from kernel-space or user-space. If kernel-space,
don't check for the capability any further and move on.
Change-Id: Ie2ddc6b619fa0d60d4752994ea0c9cedf5b96b5c
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add SOC ID to support socinfo for Shima SOC.
Change-Id: I2f3c8476d02ab55e55d14c64e359a1a2a5deeafd
Signed-off-by: Chandra Sai Chidipudi <cchidipu@codeaurora.org>
The interconnect graphs can be difficult to understand and the current
"interconnect_summary" file doesn't even display links in any way.
Add a new "interconnect_graph" file to debugfs in the graphviz "dot"
format which describes interconnect providers, nodes and links.
The file is human-readable and can be visualized by piping through
graphviz. Example:
ssh $TARGET cat /sys/kernel/debug/interconnect/interconnect_graph \
| dot -Tsvg > interconnect_graph.svg
Change-Id: I372a284efd67cf02b6791758c0ab836b8f011f7a
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Git-commit: 1a0013c62b33158dcb67a3c11872a03be50711a3
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Georgi Djakov <gdjako@codeaurora.org>
If sysctl_sched_prefer_spread is enabled, then tasks would be freely
migrated to idle cpus within same cluster to reduce runnables.
By default, the feature is disabled.
User can trigger feature with:
echo 1 > /proc/sys/kernel/sched_prefer_spread
Aggressively spread tasks with in little cluster.
echo 2 > /proc/sys/kernel/sched_prefer_spread
Aggressively spread tasks with in little cluster as well as
big cluster, but not between big and little.
Change-Id: I0a4d87bd17de3525548765472e6f388a9970f13c
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Add msm_hdmi_hdcp_mgr.h header that is exported from the display
techpack for use in the display userspace modules.
Change-Id: Ib17dee3daf3f7998ea76d18cdc55e724266a0021
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Certain SMMU implementation, such as the QSMMUV500 model, have
hardware that can be used to collect information that is useful
for debugging adversarial scenarios, such as TLB sync timeouts.
Add support for collecting information for debugging TLB sync
timeouts, as well as triggering the SMMU HW to perform a
translation for verification purpose, and wire up the QSMMUV500
implementations of these hooks. In doing so, there are no
users of the iova_to_phys_hard() and tlb_sync_timeout() hooks
in the arm_smmu_arch_ops structure, so remove these fields.
Change-Id: I61df57e82f3058a7e8a09f4df1fe147a71ae2fc3
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Some SMMU implementations, such as the QSMMUV500 model, may
need to program a specific context bank, in addition to the
initial context bank programming. Thus, add support for
implementation specific context bank initialization, and
migrate the QSMMUV500 context bank initialization to use
the new hook.
Consequently, as there are no current users of the
arm_smmu_arch_init_context_bank() hook, remove it.
Change-Id: Ia89420cc8b669a142b37bf4250c09b6aa3646172
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Rework the QSMMUV500 initialization sequence, such that the
QSMMUV500 implementation initialization uses the existing
SMMU implementation architecture.
This means ensuring that all of the implementation specific
data structures are allocated as part of the initialization,
as well as ensuring that all of the TBUs have probed. Also,
move the logic for hardware version detection to the QSMMUV500
configuration probe function.
Consequently, there are now no users of the arm_smmu_arch_init()
and arm_smmu_arch_device_reset() hooks, so remove them.
Change-Id: I8ca82ef8ea821b9e2171f7dca707f4da6ce2c0d7
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
All of the implementation details related to the QSMMUV500 model
of the SMMU-V2 architecture currently reside in arm-smmu.c.
This clashes with the current ARM SMMU SW architecture, as
arm-smmu.c is meant to house architecture specific details,
and arm-smmu-[$VENDOR].c is meant to house vendor specific
implementation details about those architectures.
To prepare to move to comply with this architecture, migrate
the QSMMUV500 related logic to arm-smmu-qcom.c, as well as
export any shared data structures. This patch should not
introduce any functional changes.
Change-Id: I711e41e38cd35b6727faf5a399eefcf5db453612
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
While isolating/un-isolating CPUs to cater the needs of other
virtual machines in the system, clients would want to run CPUs
at some reasonable frequency to balance perf/power needs.
This patch adds frequency QoS support to enable clients to run
the CPUs at desired frequecy.
Change-Id: I3c577815ddc246df2ff1d87218db18c2bfb05819
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Awake PM with a timeout in kernel soon after response from DSP to
keep the system awake and allow the ioctl call reach user space from
kernel space.
Change-Id: If518e17ec300565af2d16feca0524e741790ba7f
Acked-by: Himateja Reddy <hmreddy@qualcomm.com>
Signed-off-by: Anirudh Raghavendra <araghave@codeaurora.org>
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
Add the missing __func__ argument to the failed hypercall error print
in hh_dbl_send().
Change-Id: If40a13db695822fb363ea870389e42ba8dbb9015
Signed-off-by: Chris Lew <clew@codeaurora.org>
The threaded interrupt handler needs access to the cap_table_entry
structure and the clients passed in private data. All this information
is store in the cap_table_entry struct. Pass this in as irq private
data instead of the clients private pointer.
Change-Id: If2455704236f3531724d5c007210559391e5cfd8
Signed-off-by: Chris Lew <clew@codeaurora.org>
Use the IRQF_ONESHOT flag while requesting the threaded interrupt.
This flag keeps the virtual interrupt line masked until the threaded
handler has executed.
Change-Id: I041823f8b30e4326d3b28635c80918e4b501432a
Signed-off-by: Chris Lew <clew@codeaurora.org>
When there is only 2 tasks in 1 cpu and the other
task is currently running, allow load bigger task
to be balanced if the other task is currently
running.
Change-Id: I489e9624ba010f9293272a67585e8209a786b787
Signed-off-by: Maria Yu <aiquny@codeaurora.org>
Signed-off-by: Cong Zhang <congzhan@codeaurora.org>
Currently NR_KERNEL_MISC_RECLAIMABLE is being updated with units of bytes.
Fix to correctly update NR_KERNEL_MISC_RECLAIMABLE using page units.
Change-Id: Ie6c620a2a2218be1b30e9f1539c9d0d92870a726
Signed-off-by: Liam Mark <lmark@codeaurora.org>
This change is for general scheduler improvements.
Change-Id: I780f52ebc3cb69ee2c497d2d2f8e8fddd789421d
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
We are kicking no-hz idle balance when the CPU has two tasks.
It should be done only when the CPU is overutilized on
energy aware systems. This approach seems to be causing more
number of wakeups on HZ=250 systems compared to HZ=100.
Revisit the no-hz idle scheme and only send the IPI if and
when it is necessary.
Change-Id: I82e58a2aa3b6508c86d05c93c9fb7fe6dfbde500
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Enable CONFIG_DMA_COHERENT_HINT_CACHED to allow clients to configure
their device as dma-coherent-hint-cached.
Change-Id: I955bf57abc6a385544737a128b7d492c98c10c47
Signed-off-by: Liam Mark <lmark@codeaurora.org>
When clients configure their device as dma-coherent-hint-cached this will
result in the memory framework only trying to DMA map buffers as
IO-coherent if the framework is confident that the buffers are mapped as
cached in the CPU.
Clients should configure their device as dma-coherent-hint-cached instead
of dma-coherent when they need to DMA map both buffers that have cached
CPU mappings and other buffers which have uncached CPU mappings. By using
dma-coherent-hint-cached the framework will ensure that the client's
buffers with uncached CPU mappings don't get DMA mapped as IO-coherent.
Change-Id: I990184b54d4148bf952cc672ec267b51efd81473
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Drivers may request a QoS latency on a CPU using the dev_pm_qos
framework. Check for DEV_PM_QOS_RESUME_LATENCY as well while selecting
the idle state for a CPU and for all the CPUs in a cluster to select the
best idle state for the cluster.
Change-Id: Ic4e18f05ef8a09a8f668b89b9973f8e8499d7e02
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
