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875,490 commits

Author SHA1 Message Date
Syed Rameez Mustafa
a9e87164b8 sched: reduce sleep duration in wait_task_inactive()
Sleeping for a second adds unnecessary latency to hotplugging a cpu
(cpu_up). Reduce the wait time down to 1 ms which is in line with
earlier kernel versions. The 1 second value was caused due to an
incorrect merge conflict resolution during kernel upgrade.

Change-Id: Ice58147fff4d9b997def823436510ce23b02eb8e
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[satyap@codeaurora.org: trivial merge conflict resolution]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:57 -08:00
Pavankumar Kondeti
bf868a6f04 sched/topology: Enable EAS on SMP systems also
Currently EAS gets disabled when the system has only symmetric CPUs.
For example, either the system is SMP or all big or little CPUs are
hotplugged out on a b.L system. EAS features are required for better
power and performance on systems with symmetric CPUs. So don't disable
EAS on symmetric systems. This is done by assigning sd_asym_cpucapacity
per-cpu pointer to the only available sched domain.

Change-Id: If08a162f652a6a73884481ebc60e940373dbf9e2
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2019-12-04 16:27:56 -08:00
Abhijeet Dharmapurikar
79785b91dd power: em: correct increasing freq/power ratio
As freq increases freq/power should decrease, indicating nonlinearly
higher power is required for running at higher frequencies.

If freq/power increases, the cost associated with that
freq will be lower than its previous one, causing the energy
calculations to choose a cpu with that frequency over a cpu with
the previous lesser freq.

For some frequencies, if their voltage increment from the
previous ones is very small (or is the same), we could end up with
higher freq/power ratio. This is primarily because
of_dev_pm_opp_get_cpu_power() returns power in mW and looses precision.

But instead of addressing it, enforce the same cost as the previous
frequency.

The energy evaluation code prefers the previous cpu when the energy costs
are same as other candidates. By keeping the energy costs same in these
situations we are increasing the likely hood of selecting prev cpu even
if it results in a slight freq bump. In general, selecting prev cpu is
beneficial because it avoids warming up the caches at a different cpu.

Change-Id: Ic66ab18ba65f2917b73d9fbe92a39b743b9839a0
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
2019-12-04 16:27:56 -08:00
Morten Rasmussen
b53675c0d2 ANDROID: sched/fair: Avoid unnecessary balancing of asymmetric capacity groups
On systems with asymmetric cpu capacities, a skewed load distribution
might yield better throughput than balancing load per group capacity.
For example, running compute intensive tasks on high capacity cpus while
leaving low capacity cpus idle. So we let load-balance back off if the
busiest group isn't really overloaded.

cc: Ingo Molnar <mingo@redhat.com>
cc: Peter Zijlstra <peterz@infradead.org>

Signed-off-by: Morten Rasmussen <morten.rasmussen@arm.com>
Change-Id: I8b08a0fa73f357a9972324bc76cec3912fe293cf
Signed-off-by: Chris Redpath <chris.redpath@arm.com>
Git-commit: c42f9795e6a0c0e9d3cc6e1fe02fa60829ceb23a
Git-repo: https://android.googlesource.com/kernel/common/
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
[clingutla@codeaurora.org: Took partial commit '5494e2edf59c2 ("ANDROID:
  sched: Consider misfit tasks when load-balancing")', which defined
  function group_similar_cpu_capacity.]
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
2019-12-04 16:27:55 -08:00
Puja Gupta
44d528b138 Revert "sched/deadline: Remove cpu_active_mask from cpudl_find()"
This reverts commit 9659e1ee. The change leaves a possibility of
scheduling dl task on offline cpu. The original commit text suggests
that it should not be a problem since migrate_tasks() will take care of
it, but there can be delay between marking cpu as offline and
migrate_tasks() call since they are called on different hotplug
notifications-offline happens on CPUHP_TEARDOWN_CPU while
migrate_tasks() gets called on CPUHP_AP_SCHED_STARTING. And in
between this duration there is a chance the dl task can get scheduled on
this offline cpu and lead to BUG_ON. Hence revert the change.

Change-Id: I6f4ea10d2ce4e83e12d36b9b90b1b630ffe4fc74
[pujag@codeaurora.org: fix minor conflicts due to reorg of the code]
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
[satyap@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:55 -08:00
Satya Durga Srinivasu Prabhala
3f223d4909 trace/sched: set priority to 150 for deadline tasks
As deadline tasks doesn't have priority, their priority is set
to -1. If there are any deadline tasks in the system, chrome/tracing
doesn't show results as expected as it can't recognize tasks with
priority -1. Fix it by using 150 as priority for deadline tasks.

Change-Id: I49b43f77b97ebfe6d79a7c9e9ec346ea60e79768
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:54 -08:00
Pavankumar Kondeti
091048b54d cpu/hotplug: Ensure that sched domains are rebuilt before hotplug
When cpusets are enabled, the rebuilding of the scheduling domains
is deferred to a workqueue context. Make sure that the work is
completed before proceeding to the next hotplug. Otherwise scheduler
observes an inconsistent view of online and offline CPUs in the
root domain. If the online CPUs are still stuck in the offline i.e
default domain, those CPUs would not be visible when scheduling
happens on from other CPUs in the root domain. This results in
packing tasks more on certain CPUs while leaving the other CPUs
idle. Also RT_RUNTIME_SHARE feature i.e borrowing RT runtime from
the other CPUs would not work correctly. Because the CPUs in the
root domain can't borrow the runtime from the online CPUs but stuck
in the offline/default domain.

Change-Id: I93c51d2abc8a9c099b62f1d2cbb9095d3a788bda
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:54 -08:00
Syed Rameez Mustafa
61f31539cf sched: turn off the TTWU_QUEUE feature
While the feature TTWU_QUEUE has the advantage of reducing cache
bouncing of runqueue locks, it has the side effect that runqueue
statistics are not updated until the remote CPU has a chance to
enqueue the task. Since there is no upper bound on the amount of
time it can take the remote CPU to enqueue the task, several
sequential wakeups can result in suboptimal task placement based
on the stale statistics. Turn off the feature as the cost of
sub-optimal placement is much higher than the cost of cache bouncing
spinlocks for msm based systems.

Change-Id: I0b85c0225237b2bc44f54934769f5e3750c0f3d6
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflict]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:54 -08:00
Satya Durga Srinivasu Prabhala
3ab58753c8 sched: Introduce PANIC_ON_SCHED_BUG
Introduce PANIC_ON_SCHED_BUG to catch issues related to scheduler
like calling sleepable functions inside atomic context etc.

Change-Id: I9f1fe96772b317b17bd0e7423a48023d3cf141c7
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:53 -08:00
Santosh Shukla
2d9dd2dcc3 timer: Add function to migrate timers
Add function to migrate timer that will be used by later patch set.

Change-Id: I2d4fbe312fe635273c7386aba8378937f4b0ac15
Signed-off-by: Santosh Shukla <santosh.shukla@linaro.org>
[ohaugan@codeaurora.org: Updated commit text and fixed trivial merge conflict]
Git-commit: 3633b88d8fcb4273807574c27c328b6908a741e5
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
[rameezmustafa@codeaurora.org: Port to msm-4.9]
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:53 -08:00
Gary S. Robertson
f4396389a5 hrtimer.h: prevent pinned timer state from breaking inactive test
An hrtimer may be pinned to a CPU but inactive, so it is no longer valid
to test the hrtimer.state struct member as having no bits set when inactive.
Changed the test function to mask out the HRTIMER_STATE_PINNED bit when
checking for inactive state.

Change-Id: Icb4156f4b7cb10138ea6c5cd5b762e35dc25428d
Signed-off-by: Gary S. Robertson <gary.robertson@linaro.org>
[ohaugan@codeaurora.org: Port to 4.4]
Git-commit: 902e4d4eb0d2158d2792166221a72a829caecf07
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
[satyap@codeaurora.org: Port to 4.19 and fix merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:52 -08:00
Viresh Kumar
55efbbcc5f hrtimer: make sure PINNED flag is cleared after removing hrtimer
Change-Id: I1a3211bc0d5d310c7fa7b92dc44ec6c4722dd7b9
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
[forward port to 3.18]
Signed-off-by: Santosh Shukla <santosh.shukla@linaro.org>
Git-commit: d6c894e515b4cd93c3a08e7c60cce0aa5118c656
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:52 -08:00
Viresh Kumar
a13bd9b940 hrtimer: create hrtimer_quiesce_cpu() to isolate CPU from hrtimers
To isolate CPUs (isolate from hrtimers) from sysfs using cpusets, we need some
support from the hrtimer core. i.e. A routine hrtimer_quiesce_cpu() which would
migrate away all the unpinned hrtimers, but shouldn't touch the pinned ones.

This patch creates this routine.

Change-Id: Icf93622bdeed9c6c28eb1aca1637bc5b9522a533
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
[forward port to 3.18]
Signed-off-by: Santosh Shukla <santosh.shukla@linaro.org>
[ohaugan@codeaurora.org: Port to 4.4]
Git-commit: d4d50a0ddc35e58ee95137ba4d14e74fea8b682f
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
[rameezmustafa@codeaurora.org: Port to msm-4.9]
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[satyap@codeaurora.org: Port to msm-4.19 and fix merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:52 -08:00
Viresh Kumar
e2e45baa03 hrtimer: update timer->state with 'pinned' information
'Pinned' information would be required in migrate_hrtimers() now, as we can
migrate non-pinned timers away without a hotplug (i.e. with cpuset.quiesce). And
so we may need to identify pinned timers now, as we can't migrate them.

This patch reuses the timer->state variable for setting this flag as there were
enough number of free bits available in this variable. And there is no point
increasing size of this struct by adding another field.

Change-Id: Id2cdd74903598e31fab6999c4cbab9c2fd17fe23
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
[forward port to 3.18]
Signed-off-by: Santosh Shukla <santosh.shukla@linaro.org>
[ohaugan@codeaurora.org: Port to 4.4]
Git-commit: 62feaf1ed0b64c04868d143d8bdb92d60dc3189b
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
[markivx: Port to 4.14, fix merge conflicts due to lack of timer stats code]
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
[satyap@codeaurora.org: Port to 4.19, fix merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:51 -08:00
Viresh Kumar
d205b84171 timer: create timer_quiesce_cpu() to isolate CPU from timers
To isolate CPUs (isolate from timers) from sysfs using cpusets, we need some
support from the timer core. i.e. A routine timer_quiesce_cpu() which would
migrates away all the unpinned timers, but shouldn't touch the pinned ones.

This patch creates this routine.

Change-Id: I4795aeffd1be41830ac295a1e2e8f36fb05e98b7
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
[forward port to 3.18]
Signed-off-by: Santosh Shukla <santosh.shukla@linaro.org>
[ohaugan@codeaurora.org: Port to 4.4. Fixes for compilation error]
Git-commit: 313910b70ea0c73f8789d9189c11e1f339080646
Git-repo: git://git.linaro.org/people/mike.holmes/santosh.shukla/lng-isol.git
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
[rameezmustafa@codeaurora.org: Port to msm-4.9 and rebase to change
					patch dependency order.]
Signed-off-by: Syed Rameez Mustafa <rameezmustafa@codeaurora.org>
[markivx: Port to 4.14, fix merge conflicts]
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
[satyap@codeaurora.org: Port to 4.19 and resolve trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2019-12-04 16:27:51 -08:00
qctecmdr
f41050307f Merge "firmware: qcom-scm: Fix formatting errors in the trace string" 2019-12-04 14:57:36 -08:00
qctecmdr
f7ef9d9893 Merge "msm: ipa: Add PIL driver as soft dependency for IPA" 2019-12-04 02:35:00 -08:00
qctecmdr
d4cf41dc2e Merge "media: v4l2-core: guard code against ABI breakage" 2019-12-04 02:34:59 -08:00
qctecmdr
5f14f07b0b Merge "defconfig: enable fastrpc driver on Lahaina" 2019-12-04 01:54:28 -08:00
qctecmdr
bf2389a109 Merge "clk: qcom: add clk rpmh support for Lahaina" 2019-12-04 01:22:17 -08:00
qctecmdr
4d3767fbbb Merge "msm: cvp: Disabe sys cache and dsp initialization" 2019-12-04 01:22:15 -08:00
qctecmdr
de44503b2e Merge "mm: cma: Reduce dmesg spam" 2019-12-04 00:47:31 -08:00
qctecmdr
f07284b38a Merge "mm: cma: restrict base_pfn exposure" 2019-12-04 00:47:30 -08:00
qctecmdr
99049a00e4 Merge "soc: qcom: Add spss transport for Glink Probe driver" 2019-12-04 00:06:54 -08:00
qctecmdr
106819260e Merge "arm64: defconfig: Enable GLINK Packet driver for Lahaina" 2019-12-04 00:06:53 -08:00
qctecmdr
2f61ee8554 Merge "checkpatch: check symlinks while searching compatible strings" 2019-12-04 00:06:52 -08:00
Edgar Flores
f745eaca11 defconfig: enable fastrpc driver on Lahaina
Enable compilation of the fastrpc driver on Lahaina, which
provides a communication mechanism that allows clients to
make remote method invocations across processor boundary
to applications, compute and sensors DSP processors.

Change-Id: I2a43104e260b3e129e3447840f3180843c10ce3a
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
2019-12-03 22:14:29 -08:00
himta ram
b6f9c071a2 media: v4l2-core: guard code against ABI breakage
Guard the code against ABI breakage using IS_ENABLED Helper macro.
Guarded code will be compiled when config is set to m or y.

CRs-Fixed: 2579332
Change-Id: Ic1a5ab22c8ced2c7b527bf5086c2c7b14fe24919
Signed-off-by: himta ram <hram@codeaurora.org>
2019-12-03 21:41:18 -08:00
George Shen
b12de3763b msm: cvp: Disabe sys cache and dsp initialization
System cache and DSP CVP driver not ready for Lahaina
bring up. Disable them until they are ready.

Change-Id: I70acfe8d53e527f7456084d72d93116a047f919a
Signed-off-by: George Shen <sqiao@codeaurora.org>
2019-12-03 18:16:39 -08:00
qctecmdr
3da863f0f8 Merge "ABI: aarch64: Update ABI snapshot based on v5.4" 2019-12-03 18:00:47 -08:00
qctecmdr
f8008953da Merge "dt-bindings: sound: Add GPR device tree bindings" 2019-12-03 18:00:47 -08:00
Murali Nalajala
4b52ed4ea1 checkpatch: check symlinks while searching compatible strings
"grep -r" option excludes symlinks. This breaks if there are symlinks
present in the bindings and actual source resides outside of the kernel.
To consider symlinks invoke grep with "-R" option.

Change-Id: Ie43876a0caee8f7f5a217391213cbb12efd52ff9
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: Siddharth Gupta <sidgup@codeaurora.org>
2019-12-03 17:09:16 -08:00
qctecmdr
aed6dbfc5b Merge "arm64: defconfig: Enable IPC IRQ bridge for Lahaina" 2019-12-03 16:27:01 -08:00
qctecmdr
f6ddaecb4f Merge "ion: msm: Move msm_ion probe to subsys_initcall_sync" 2019-12-03 16:27:00 -08:00
qctecmdr
9745a9b4af Merge "clk: qcom: dispcc: Fix stuck on warning for disp_cc_mdss_mdp_lut_clk" 2019-12-03 16:27:00 -08:00
qctecmdr
1e0cee8ff8 Merge "clk: qcom: dispcc: Voltage voting support for Lahaina" 2019-12-03 16:26:59 -08:00
qctecmdr
1768daa512 Merge "msm: ipa3: Fix to hold the clock until replenish the descriptors" 2019-12-03 15:33:49 -08:00
qctecmdr
5939f51cb4 Merge "msm: ipa3: Fix to increase timeout value for send command" 2019-12-03 15:33:49 -08:00
qctecmdr
0100b2ce16 Merge "mm: usercopy: skip stack page span check" 2019-12-03 15:33:49 -08:00
qctecmdr
eac37ae56c Merge "soc: qcom: secure_buffer: Move to subsys_initcall" 2019-12-03 15:33:48 -08:00
qctecmdr
acfac220ec Merge "arm64: defconfig: Enable the MSM ION heaps on Lahaina GKI" 2019-12-03 15:33:48 -08:00
Patrick Daly
9848b4d838 mm: cma: Reduce dmesg spam
CONFIG_CMA_DEBUG was #defining DEBUG, which has the side effect of
changing the behavior of pr_debug statements to always print into
the dmesg log, as opposed to printing only if they are enabled via
dynamic debug.

Log etiquette indicates that messages should only be printed for
error conditions.

Change-Id: I5eebc1060618a3abc87a7f85ae770505c991c017
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2019-12-03 14:01:37 -08:00
Prakash Gupta
01151d5fcf mm: cma: restrict base_pfn exposure
We are exposing cma region's base_pfn without any restriction. Make this
dependent on kptr_restrict configuration.

Change-Id: If454194cc5e7639f33b2e1dd29f5d925a17340c1
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2019-12-03 13:55:10 -08:00
David Dai
c957e677cf clk: qcom: add clk rpmh support for Lahaina
Add clock rpmh data to communicate with RPMH clocks for Lahaina.

Change-Id: I1291fbd77bd5412036023c3cad82f49d1ad3f0e5
Signed-off-by: David Dai <daidavid1@codeaurora.org>
2019-12-03 13:51:59 -08:00
David Dai
5fb81a39ca dt-bindings: clock: Add rpmh header for Lahaina
Add new RPMH clocks for Lahaina.

Change-Id: Ie599365550887854a18549416ebb875135caab96
Signed-off-by: David Dai <daidavid1@codeaurora.org>
2019-12-03 13:50:49 -08:00
Vignesh Kulothungan
1957106371 dt-bindings: sound: Add GPR device tree bindings
Add definitions for GPR domain id's and ADSP service
id's in device tree bindings.

Change-Id: I1d7d81893643287c5720a339b1eedbb6be92b4c4
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
2019-12-03 13:35:45 -08:00
Jordan Crouse
ae4a818923 firmware: qcom-scm: Fix formatting errors in the trace string
Fix a handful of format errors in the trace string. Use a %llx for
u64 values.

Fixes: 873f25f ("firmware: qcom_scm: Add trace points to scm driver")
Change-Id: Ic0dedbad69ffdb044e094bfcb4e95f848338edd0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2019-12-03 13:47:24 -07:00
Ghanim Fodi
2fe74a2fa4 msm: ipa: Add PIL driver as soft dependency for IPA
IPA driver uses PIL driver to load IPA firmware.
PIL driver need to be loaded before IPA driver for
GKI configuration.

Change-Id: Ib910bb7429bc739a95e47973332578806c5e5ca4
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
2019-12-03 08:49:48 -08:00
Ashok Vuyyuru
5dfa9644c3 msm: ipa3: Fix to hold the clock until replenish the descriptors
When CPU load is high IPA buffer replenish WQ scheduling got delayed
because of that not able to replenish the descriptors. Add changes to
hold the clock until replenish the minimum number of descriptors.

Change-Id: Iea79dcaa90d12fc4324522ba2c63dfcdfded2f90
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2019-12-03 04:19:16 -08:00
Ashok Vuyyuru
fbec6ce31d msm: ipa3: Fix to increase timeout value for send command
Due to freeing the command payload Observing proc error
from IPA HW when HW delayed to process the command. Add
changes to increase timeout value and handling return
value from timeout function.

Change-Id: I0c953a9cc299ffdf1bd8c746a2b60a2107e993ee
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2019-12-03 04:17:26 -08:00