Use rwsem to ensure serialization of the callers and to avoid
starvation of high priority tasks, when the system is under
heavy IO workload.
Change-Id: Ifac519c3de127f79d8613ee742a68f7fc0377e36
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Add initial architecture support for arch and pincontrol
for scuba on 5.4.
Change-Id: I844f2c3fc0776f77c533808c2cca6f05ee946644
Signed-off-by: Archit Saxena <archsaxe@codeaurora.org>
Signed-off-by: Nagireddy Annem <nannem@codeaurora.org>
Allwinner's SoC timer driver (timer-sun4i.c) has to be built-in rather
than modularized for the following limitations in linux timer framework:
1. tick broadcast installed by insmod cannot switch to oneshot mode
correctly
2. cpus cannot enter cpuidle state due to the issue above.
3. rcu warnings will appear if we forcibly re-enable tick-broadcast
for each cpu when new tick broadcast device is installed by insmod
(timer-sun4i.c in our case)
Bug: 173667601
Change-Id: If077db348c027ec02549e25eee3e17c2cc429644
Signed-off-by: Martin Wu <wuyan@allwinnertech.com>
A porting error in commit 0ae8088521d9 ("ANDROID: uid_cputime: Adds
accounting for the cputimes per uid.") caused
/proc/uid_cputime/show_uid_stat to report times in milliseconds
instead of microseconds. Restore the expected behavior.
Bug: 133273154
Bug: 146339763
Signed-off-by: Ed Savage-Jones <edward.savage-jones@sony.com>
Signed-off-by: Connor O'Brien <connoro@google.com>
Change-Id: I203919d1d44b300dab91810b16626a6950b063f8
(cherry picked from commit 305d5c197508b80a8dec0ab506de309e5d85fd26)
Access to the AMU counters should be disabled by default in kvm guests,
as information from the counters might reveal activity in other guests
or activity on the host.
Therefore, disable access to AMU registers from EL0 and EL1 in kvm
guests by:
- Hiding the presence of the extension in the feature register
(SYS_ID_AA64PFR0_EL1) on the VCPU.
- Disabling access to the AMU registers before switching to the guest.
- Trapping accesses and injecting an undefined instruction into the
guest.
Bug: 172781912
Change-Id: Ie8048574431dfe00e9d8f59ecbcf51b4c1167000
Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Julien Thierry <julien.thierry.kdev@gmail.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 4fcdf106a4330bb5c2306a1efbb3af3b7c0db537)
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
The activity monitors extension is an optional extension introduced
by the ARMv8.4 CPU architecture. In order to access the activity
monitors counters safely, if desired, the kernel should detect the
presence of the extension through the feature register, and mediate
the access.
Therefore, disable direct accesses to activity monitors counters
from EL0 (userspace) and trap them to EL1 (kernel).
To be noted that the ARM64_AMU_EXTN kernel config does not have an
effect on this code. Given that the amuserenr_el0 resets to an
UNKNOWN value, setting the trap of EL0 accesses to EL1 is always
attempted for safety and security considerations. Therefore firmware
should still ensure accesses to AMU registers are not trapped in
EL2/EL3 as this code cannot be bypassed if the CPU implements the
Activity Monitors Unit.
Bug: 172781912
Change-Id: I231595cd2d1e36bfc6abd24559c9c3d13e7eab03
Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 87a1f063464afd934f0f22aac710ca65bef77af3)
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
The activity monitors extension is an optional extension introduced
by the ARMv8.4 CPU architecture. This implements basic support for
version 1 of the activity monitors architecture, AMUv1.
This support includes:
- Extension detection on each CPU (boot, secondary, hotplugged)
- Register interface for AMU aarch64 registers
Bug: 172781912
Change-Id: I8fa585dd992213d8042e6f9ddec2cb3bcefade05
Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 2c9d45b43c39e26fd2a73f2203321cdaee98b58b)
[neeraju: Resolved minor conflicts in Kconfig, cpucaps.h, cpufeature.h]
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
CONFIG_MSM_PERFORMANCE_QGKI will enable full functionality of
msm_performance driver on QGKI and minimal functionality on
GKI.
Change-Id: Ie2a2184c9390d904532c4d659d02562c93b7e725
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <bsrivenk@codeaurora.org>
commit e4b469c66f3cbb81c2e94d31123d7bcdf3c1dabd upstream.
A previous commit aligning splits to physical block sizes inadvertently
modified one return case such that that it now returns 0 length splits
when the number of sectors doesn't exceed the physical offset. This
later hits a BUG in bio_split(). Restore the previous working behavior.
Bug: 173583534
Fixes: 9cc5169cd4 ("block: Improve physical block alignment of split
bios")
Reported-by: Eric Deal <eric.deal@wdc.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Cc: Bart Van Assche <bvanassche@acm.org>
Cc: stable@vger.kernel.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Bug: 173583534
(cherry picked from commit f09dbec9c0)
Signed-off-by: Chenggang Wang <wangchenggang@vivo.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I5f4708059f106b6ded162cbe096e45bae7a7fca4
Current logic on handling corrupted_errs countes is not considering
DM_VERITY_MAX_CORRUPTED_ERRS limit so correcting the logic.
Change-Id: Ide3f3e6b9d8bec8f02cbb5a72b7d0935bcd87826
Signed-off-by: Ravi Kumar Siddojigari <rsiddoji@codeaurora.org>
Wlan fw will provide RD card chain mask capability
for as part of cap qmi message exchange between host
platform and fw platform. Using this info host platform
will determine whether RD card chain is 1x1 or 2x2. It
will enabled chain1 regulator if RD card is 2x2 and also
if wlan fw doesn't provide any details about RD card
chain mask capability chain1 regulator will enabled
by default.
Change-Id: I83d9058fe505f2519a2300a4989e08acbdbcaafb
Signed-off-by: Sandeep Singh <sandsing@codeaurora.org>
Kernel 5.4 introduces HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE, devices
need to be set explicitly with this flag.
Bug: 170072925
Bug: 170126889
Tests: atest android.hardware.input.cts.tests
(cherry picked from commit f59ee399de4a8ca4d7d19cdcabb4b63e94867f09
https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git for-5.10/upstream-fixes)
Signed-off-by: Chris Ye <lzye@google.com>
Change-Id: I65742e96babc59adde0ab32656850ef4f164ac3e
Add and remove the needed depedencies in the cqhci
crypto drivers on the CONFIG_MMC_CQHCI_CRYPTO
config. This is needed to make driver successfully
compile as a module and be gki compatible.
Add module license and module description for
cqhci-crypto and cqhci-crypto-qti drivers.
Change-Id: I0da29a7d19d2f2606f5c85316ab47c6df73e66d7
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
Add PDC interrupt controller chip support for sm8150.
Change-Id: I5fc53d3567f779961d6afe7fe36d47bbaa0f9590
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Although PDC has the capability to route falling edge interrupt to
GIC by inverting the input signal, falling edge of the interrupts marked
as dual edge type is routed as is. This causes GIC to ignore to falling
edge of these interrupts when the system is active. During APSS system
sleep once PDC starts monitoring these interrupts, PDC always replays a
rising edge irrespective of which edge woke the APSS from sleep. So,
the issue does not happen during the system sleep.
To address the issue when system is active, route the falling_edge
of these interrupts through one of the direct connect interrupts
available for APSS. The original GIC interrupt is configured as dual
edge at PDC, rising edge at GIC (same as earlier, this does not change).
This solution requires additional programming of 2 registers:
TLMM_<ZONE>_DIR_CONN_INTRn_CFG_HMSS - program GPIO_SEL with the gpio
number and set POLAIRTY to 0 for inverting the falling edge
TLMM_GPIO_INTR_CFGn - set DIR_CONN_EN bit to 1 for enabling direct
connect for gpio.
Change-Id: Iaa9dfe391ef4942cd8b12fd1e7d8f9c238947af2
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
WALT requires both src and dst runqueue locks to be held
during migration. So a double_lock_balance() is added
in move_queued_task() before calling set_task_cpu(). However,
releasing the src rq lock, which is pinned is giving a
lockdep warning. Fix this by unpinning the lock before
calling double_lock_balance.
Change-Id: I64dec0701b3467185cf53f311ebb521c6a822e88
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
This patch adds to update GKI symbol list for Exynosauto SoC. To review
the allowed list easily, this patch does not include any newly additions
of GKI symbols.
Bug: 173340486
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Change-Id: I6854f5e813845840b4db052282a92f59c6864cc0
When changing to use suspend-to-idle to save power, the PMIC irq can not
wakeup the system due to lack of wakeup capability, which will cause
the sub-irqs (such as power key) of the PMIC can not wake up the system.
Thus we can add the wakeup capability for PMIC irq to solve this issue,
as well as removing the IRQF_NO_SUSPEND flag to allow PMIC irq to be
a wakeup source.
Reported-by: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Baolin Wang <baolin.wang7@gmail.com>
Tested-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Bug: 173341055
(cherry picked from commit a75bfc824a2d33f57ebdc003bfe6b7a9e11e9cb9)
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Change-Id: Ibe5f907b96d59e8b02e8e4838fc8b3cde5f4f35e
Suspend to IDLE invokes tick_unfreeze() on resume. tick_unfreeze() on the
first resuming CPU resumes timekeeping, which also has the side effect of
resetting the softlockup watchdog on this CPU.
But on the secondary CPUs the watchdog is not reset in the resume /
unfreeze() path, which can result in false softlockup warnings on those
CPUs depending on the time spent in suspend.
Prevent this by clearing the softlock watchdog in the unfreeze path also
on the secondary resuming CPUs.
[ tglx: Massaged changelog ]
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20200110083902.27276-1-chunyan.zhang@unisoc.com
Bug: 173341055
(cherry picked from commit 5167c506d62dd9ffab73eba23c79b0a8845c9fe1)
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Change-Id: Iab440b4137726811fce76f3636a4cf8bafc2c202
Enable setting trip thresholds in thermal zones for debug purposes.
Change-Id: Ifbd154ba343a319cbd9ddca24efe539db557abbd
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
when gadget pullup, add this event allow redriver
do some operation according to the pullup state.
Change-Id: I9cbd3f9e95aae327e1f872aff7ebff7a8926e5a5
Signed-off-by: Linyu Yuan <linyyuan@codeaurora.org>
when redriver connect to a USB hub, and do adb root operation,
due to redriver rx termination detection issue,
hub will not detct device logical removal.
workaround to temp disable/enable redriver when usb pullup operation.
Change-Id: Ia3b0c99a28dd7d0601e7c5bcc612c4c48447c165
Signed-off-by: Linyu Yuan <linyyuan@codeaurora.org>
