There is a race condition when a write operation is blocked
waiting for an available request and the function is disabled
due to disconnection or reset. usb_ep_disable() is called from
acc_function_disable() and causes the UDC to call the pending
requests' completions, which will wake up the writer thread and
proceed to call usb_ep_queue() before the endpoint is fully
disabled. The UDC driver may not handle this and could allow
the request to be requeued inadvertently. In DWC3's case, this
allows the HW to attempt a transfer with stale TRBs that point
to invalid DMA buffers.
Let's ensure the function driver acts as a good citizen and handle
it by moving the check for dev->offline || dev->disconnected to
after the wait_event to make sure the endpoint is enabled before
attempting to queue another request.
Change-Id: I1aa005e0c1e3ed1e1d814ff79496b70fdb401571
Signed-off-by: Jack Pham <jackp@codeaurora.org>
Add dbg_state sysfs to facilitate trace instance to be enabled
only on debug flavor builds.
Change-Id: I6524e6184e2a81b2e39b0f0338e4d8a9b7989542
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Enable USB PD config flag on sdxlemur to add
PD support.
Change-Id: If7a91abb4c6d1b0f368a931c9c686012a310eb99
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
Calling SSR unregister for other peripherals from glink_ssr device remove
call back results in deadlock if multiple SSRs happens in parallel.
SSR unregister is defer to other worker to avoid notifier SRCU deadlock.
Change-Id: Ifa5c461201eec4b4beb8bf405bd0a2904a2cc90f
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
Signed-off-by: Sarannya S <sarannya@codeaurora.org>
Get kernel time during start and end of map create
to keep track of time taken to create map. The time
variables are added as member of map struct. Same
time variables are added for buffers also.
Change-Id: I6454f5b60bec1a24a43ea1b7539ec45ba5358f2e
Acked-by: Ekansh Gupta <ekangupt@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
There is potential issue where uninitialized variable can be
used, so fix it.
Change-Id: If725b7efc2979889415da2673c68d4be71e41631
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Add clock ids for GCC/DISPCC/GPUCC for clients to be able
to request for clocks from these clock controllers for
monaco.
Change-Id: Ie09a5a7a5fd1101fb863e836a0e554198e699511
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
Avoid race condition between soc wake release from queue
context and host driver context.
Change-Id: I6e20a9a8781f65447e89160ff4e362a04ec4ec5c
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
Send force FW crash message to FW via smp2p to trigger
SSR. This will be used by host to recover FW bad state.
Change-Id: If840a94c9102acb775fc67e6fd2098e9ae3b8a33
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
For QMI dpm port to open, control manager needs
to know about usb/mhi ep details corresponding to
RMNET and RMNET_CV2X tethering.
IPA driver has all endpoint info at one place.
- provide IOCTL interface to get ep_pair info.
- Add support for new dtsi entry specifying auto config.
- Add support in ipa-usb driver for rmnet_cv2x.
Change-Id: Ia5ec0df955ef7794ca992129dab538f65af36211
Signed-off-by: Mohammed Javid <mjavid@codeaurora.org>
Shortcut forward Engine (SFE) is a software packet accelerator
It depends on packet tuple entries based on conntrack information
The change adds its config entry in net Kconfig.
Change-Id: Ied018e83e26f69682590989242b333754f367556
Signed-off-by: Aman Gupta <amangupt@codeaurora.org>
Update bus voting for sdxlemur nand driver with the new icb framework.
Change-Id: I59108be9545780adc5f9040f97ae0d07536cc6bf
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
As per current code, pm_lvl is read from DT on every probe
during system resume after suspend.
Therefore, rpm_lvl and spm_lvl updated by sysfs will be overwritten
with the pm_lvl read from DT during probe after resume from
system suspend.
To avoid this read pm_lvl from DT only when current pm_lvl
is invalid or during the first ufs probe after boot.
Change-Id: I059d574a81d0e0f7cee8b6492e495819579a2d4c
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>
Enable SPMI debug bus driver which is useful for writing to PMIC
peripheral registers over debug bus on devices when the fuse is
not blown. While at it, enable CONFIG_SPMI_MSM_PMIC_ARB as well
explicitly though it's selected for sdxlemur already.
Change-Id: I8d04c96efcdb089f8950e57fd1b152cd1cc5a84f
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
To handle dev_boot debugfs, group the API calls based on contexts
to avoid exiting because of irrelevant invalid context.
Change-Id: I3d031ca53fc2739ae4947a40c4b3b0e7f7a74bb3
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Avoid suspending PCIe bus from QMI send put path if device is
already down.
Change-Id: I3ac7e37af3f81ec9f4ad8ae84de111a730a1f90f
Signed-off-by: Yue Ma <yuem@codeaurora.org>
The regulator_is_enabled() API doesn't guarantee that CX gdsc has
collapsed at hardware. There could be a vote on the GDSC from another
subsystem like TZ. So poll the CX GDSCR register to ensure that CX has
indeed collapsed.
Change-Id: Ic07cde5ba3442689cb73b33fe57c3d4371cb9565
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
It has been observed that without gmu_clk, any active transactions will
cause that transaction to be stuck in QSMMU. As of now we don't halt
GBIF when moving to NAP state. So there is a possibility of transactions
inflight when gmu_clk is gated. This will cause transactions to be stuck
in QSMMU forever. This can eventually lead to GPU hang or TLB sync
timeout. So halt GBIF before moving to NAP.
Change-Id: I13bbe3b21b327d0d5c962bb2133c6d5d0f3a43c3
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
deassert_gbif_halt is needed only for the a6xx targets that use
clear_pending_transactions. So move deassert_gbif_halt to a6xx specific
space. This helps to provide some clarity and avoid gmu and gbif
related checks.
Change-Id: If46fa22a54737c2dbc35205318ed75ead351760a
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
During adreno_stop, GBIF halt is asserted to halt any new transaction from
GPU before GPU power collapse, but in current code it is cleared
immediately which can allow few GPU transactions to go through before gdsc
is turned-off and can result in issues.
To avoid this situation don't deassert this halt before GPU gdsc goes off.
It will deassert automatically when gdsc goes off but in case gdsc doesn't
toggle as it is a shared resource, it is deasserted during adreno_start to
ensure wake-up doesn't fail.
Change-Id: If0a892470d04a0f3a79a1ea882ee5bfd16ad24ed
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
Currently during stall-on-fault recovery, we keep resuming SMMU and
check if GBIF halt succeeded. This is done to recover from a case where
a GPU block continuously initiated faulty transactions, which would keep
stalling SMMU. If we set CFCFG to 0 as part of handling the first fault,
all these transactions will be terminated and will not stall SMMU. This
simplifies the GBIF halt sequence and avoids resuming every time.
Change-Id: Iada83d6a08e5e0a4f6241b17d1b178ab680f1364
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
Chipsets which have PCIe Gen4 PHY and controller on MX rail
requires explicit vote for higher corners than the default.
Therefore add support to vote for and scale MX rail based on the
Gen speed which PCIe link operates at.
Change-Id: I1c2896d083fd57e02e1b19f7a75f356129d0e40f
Signed-off-by: Tony Truong <truong@codeaurora.org>
During Gen3 and Gen4 link training, PCIe PHY may require
additional time during the equalization master phase before
proceeding to the next LTSSM state. Add the support to configure
the minimum amount of time spent during equalization master
phase.
Change-Id: Id3e7ff631f6ce004829065ad798223d7d774edc1
Signed-off-by: Tony Truong <truong@codeaurora.org>
There are PCIe Gen3 and Gen4 PHY related settings which has to be
programmed at the PCIe controller. Add the infrastructure to
support such settings. Settings for Gen3 also needs to be
applied to Gen4 controllers. Move existing settings to the
new infrastructure.
Change-Id: I67c7c3d7c5bfa13ed30c8fca55f941c8cab0a7f0
Signed-off-by: Tony Truong <truong@codeaurora.org>
For chipsets which are Gen4 capable, the PCIe core preset
settings need to be configured accordingly based on trace
length. Therefore add the support to configure PCIe core
preset.
Change-Id: I6968e24135482aa356dd94fde4988ef342747337
Signed-off-by: Tony Truong <truong@codeaurora.org>
After PCIe link is up, scale PCIe resources based on the Gen
speed rather than the value of CX vote for the Gen speed. Before
CX vote was the only factor for scaling resources. This is an
incorrect assumption as additional resources can be added and
do not have any dependency with CX. Therefore, remove the
dependency on CX and bind it to the Gen speed instead.
Change-Id: I64ca90892769e43d694a21e172f51d7fd4c76e68
Signed-off-by: Tony Truong <truong@codeaurora.org>
Add support to cache PCIe current link speed after each link
training and Gen switching. This will help check users check
which Gen speed the link was operating at all times.
Change-Id: I64487dff10cf9c5a6dc87dad42239c7cd119763c
Signed-off-by: Tony Truong <truong@codeaurora.org>
If data processing of an event is scheduled out because core
is busy handling multiple irqs, this can starves the processing
of MHI M0 state change event on another core. Fix this issue by
disabling irq on the core processing data events.
Change-Id: I4d784d2c343d4a9c50741f3e72df4c373993ae79
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Put the migration failure info of a page under DEBUG_VM as most of
the times this info is not required.
Change-Id: I798f0bef9c558a272c6aa94424236d8f65f801dd
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
