Add a new SPMI bus driver which can manage the SPMI debug bus
found on SPMI PMIC arbiter version 5 and above. This debug
bus has read and write access to all PMIC peripherals regardless
of ownership configurations. It cannot be used on production
devices because it is disabled by an eFuse.
Change-Id: I7dd7171d775db02269b98bb079bdccf5d0f4aae4
Signed-off-by: David Collins <collinsd@codeaurora.org>
The I2C PMIC Controller is used by multi-function PMIC devices
which communicate over the I2C bus. The controller enumerates
all child nodes as platform devices, and instantiates a regmap
interface for them to communicate over the I2C bus.
The controller also controls interrupts for all of the children
platform devices. The controller handles the summary interrupt
by deciphering which peripheral triggered the interrupt, and
which of the peripheral interrupts were triggered. Finally, it
calls the interrupt handlers for each of the virtual interrupts
that were registered.
This is a snapshot from msm-4.19
commit 9a702c565e5a ("Use 'GPL-2.0-only' as the
SPDX-License-Identifier tag").
Change-Id: I28a4905e1666c06cb2c06d00f56ef66981621b2d
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for TEMP_ALARM GEN2 PMIC peripherals with digital
major revision 1. This revision utilizes a different temperature
threshold mapping than earlier revisions.
Change-Id: Iaae5c64558d1ac7fb87d2f5a5b2baa26bf1c38eb
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for qcom,pm8350-gpio, qcom,pm8350b-gpio,
qcom,pm8350c-gpio, and qcom,pmk8350-gpio variants.
Change-Id: I9f914a4e0c54997665bff8372f7fd2c57efccf14
Signed-off-by: David Collins <collinsd@codeaurora.org>
pmic_gpio_child_to_parent_hwirq() and
gpiochip_populate_parent_fwspec_fourcell() translate a pinctrl-
spmi-gpio irqspec to an SPMI controller irqspec. When they do
this, they use a fixed SPMI slave ID of 0 and a fixed GPIO
peripheral offset of 0xC0 (corresponding to SPMI address 0xC000).
This translation results in an incorrect irqspec for secondary
PMICs that don't have a slave ID of 0 as well as for PMIC chips
which have GPIO peripherals located at a base address other than
0xC000.
Correct this issue by passing the slave ID of the pinctrl-spmi-
gpio device's parent in the SPMI controller irqspec and by
calculating the peripheral ID base from the device tree 'reg'
property of the pinctrl-spmi-gpio device.
Change-Id: If04a7ca73b995dd99939d340f2d33d4488197de0
Signed-off-by: David Collins <collinsd@codeaurora.org>
The SPMI based PMICs have the HIGH and LOW GPIO output
strength mappings interchanged, fix them.
Keep the mapping same for older SSBI based PMICs.
CRs-Fixed: 2246473
Change-Id: I4ec78469c436b54642ee67108943c82fba46e1c4
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Currently, if the GPIO is configured as output in the bootloader
and user changes the mode to input in HLOS, it would end up
getting configured as input/output. Functionally, this is fine;
however, there may be some requirements where the output needs
to be disabled so that it can be used only for input.
Add support to enable/disable output mode through "output-enable"
or "output-disable" pinctrl properties.
Change-Id: Ie857f94d529a6209bcb82ef3775d414f19d5678a
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
The spmi_devices spawn platform devices for pmic peripherals. Some of these
devices are required early on in the boot process.
Initialize the driver at arch_initcall to avoid unnecessary probe
deferrals.
Change-Id: I38474bedcb284ed5a7df1ec8d26f680787f2c074
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
[collinsd@codeaurora.org: add module exit function]
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add device tree support for configuring if mutexes or spinlocks
should be used in the regmap configuration (i.e. the fast_io
element value). This ensures that qcom-spmi-pmic slave devices
can be used with SPMI busses that must operate in process
context.
Change-Id: I3abdee36935457db497ce6ff2a242755fc3aff90
Signed-off-by: David Collins <collinsd@codeaurora.org>
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently, when handling the SPMI summary interrupt, the hw_irq
number is calculated based on SID, Peripheral ID, IRQ index and
APID. This is then passed to irq_find_mapping() to see if a
mapping exists for this hw_irq and if available, invoke the
interrupt handler. Since the IRQ index uses an "int" type, hw_irq
which is of unsigned long data type can take a large value when
SID has its MSB set to 1 and the type conversion happens. Because
of this, irq_find_mapping() returns 0 as there is no mapping
for this hw_irq. This ends up invoking cleanup_irq() as if
the interrupt is spurious whereas it is actually a valid
interrupt. Fix this by using the proper data type (u32) for id.
CRs-Fixed: 2357600
Change-Id: I451e33d61e063d3a9381c2b43767946117a5bbb9
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Have the qpnpint_irq_set_type function clear unwanted high/low
trigger bits when updating the interrupt flags.
Change-Id: Ie55d6178ea94350ecf8c79714cb863ea63d76ea6
Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Increase the SPMI transaction timeout delay from 100 us to
1000 us in order to account for the slower execution time
found on some simulator targets.
Change-Id: I5805fa77131336e56db35ae7948012e072c15746
Signed-off-by: David Collins <collinsd@codeaurora.org>
The system crashes due to an access permission violation when
writing to a PMIC peripheral which is not owned by the current
ee. Add a check for PMIC arbiter version 5 for such invalid
write requests and return an error instead of crashing the
system.
Change-Id: If601a8c737f10be2a7d1e894f7285cf0de4eb4a5
Signed-off-by: David Collins <collinsd@codeaurora.org>
Correct the way that duplicate PPID mappings are handled for PMIC
arbiter v5. The final APID mapped to a given PPID should be the
one which has write owner = APPS EE, if it exists, or if not
that, then the first APID mapped to the PPID, if it exists.
Change-Id: I387e25d5e0d29434a6191faaf887db1e1a90243d
Signed-off-by: David Collins <collinsd@codeaurora.org>
Current implementation of SPMI arbiter dispatches interrupt based on the
Arbiter's accumulator status, in some cases the accumulator status may
remain zero and the interrupt remains un-handled. Add logic to dispatch
interrupts based Arbiter's IRQ status if the accumulator status is zero.
Change-Id: I068f5c7d33758063878721d7cce1308fa803e3bd
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Check that the apid for an SPMI interrupt falls between the
min_apid and max_apid that can be handled by the APPS processor
before invoking the per-apid interrupt handler:
periph_interrupt().
This avoids an access violation in rare cases where the status
bit is set for an interrupt that is not owned by the APPS
processor.
Change-Id: Ib74cb4ae7be9849f0243659bb4c1435340e1e087
Signed-off-by: David Collins <collinsd@codeaurora.org>
Currently, cleanup_irq() is invoked when a peripheral's interrupt
fires and there is no mapping present in the interrupt domain of
spmi interrupt controller.
The cleanup_irq clears the arbiter bit, clears the pmic interrupt
and disables it at the pmic in that order. The last disable in
cleanup_irq races with request_irq() in that it stomps over the
enable issued by request_irq. Fix this by not writing to the pmic
in cleanup_irq. The latched bit will be left set in the pmic,
which will not send us more interrupts even if the enable bit
stays enabled.
When a client wants to request an interrupt, use the activate
callback on the irq_domain to clear latched bit. This ensures
that the latched, if set due to the above changes in cleanup_irq
or when the bootloader leaves it set, gets cleaned up, paving way
for upcoming interrupts to trigger.
With this, there is a possibility of unwanted triggering of
interrupt right after the latched bit is cleared - the interrupt
may be left enabled too. To avoid that, clear the enable first
followed by clearing the latched bit in the activate callback.
Change-Id: If126d6f6cdf6c944ca513c53a71a91e225ee63e2
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
[collinsd@codeaurora.org: fix merge conflict]
Signed-off-by: David Collins <collinsd@codeaurora.org>
The cleanup_irq() was meant to clear and mask interrupts that were
left enabled in the hardware but there was no interrupt handler
registered for it. Add an error print when it gets invoked.
Change-Id: Iccf0daadeb82b0fca29829424439ac225e2b3b88
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The spmi arbiter device spawns spmi_devices which in turn spawn
platform_devices for pmic peripherals.
Move the arbiter's driver init to arch_initcall so that the subsequent
devices it spawns get instantiated earlier.
Change-Id: Ib96937f274745549ee86f758673aab4db97acbaf
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
[collinsd@codeaurora.org: added module exit function]
Signed-off-by: David Collins <collinsd@codeaurora.org>
A spmi controller may have many child devices, which together may take
a signifigant amount of time to register and probe. Reduce this effect
by probing asynchronously.
After:
[ 0.277217] calling__software_resume+0x0/0x24c_@_1
Before:
[ 0.319295] calling__software_resume+0x0/0x24c_@_1
Change-Id: I95704a2ae7aae98e23dc9f29c7d023867d60388d
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Swathi Sridhar <swatsrid@codeaurora.org>
