Commit graph

2,290 commits

Author SHA1 Message Date
qctecmdr
266303e04f Merge "ARM: dts: msm: Remove CPU and reserved memory for trustedvm" 2020-08-16 15:56:08 -07:00
qctecmdr
d0e8ac243d Merge "ARM: dts: msm: remove FDE from qseecom" 2020-08-16 15:56:08 -07:00
qctecmdr
50efc0e212 Merge "ARM: dts: msm: add dcc node on sdxlemur" 2020-08-16 15:56:08 -07:00
qctecmdr
c630287d4e Merge "ARM: dts: qcom: update ddr voting device for holi target" 2020-08-16 15:56:08 -07:00
Akash Asthana
6018a83564 ARM: dts: msm: Define console before other QUP devices
QUP core clock is shared among all the SE drivers, during earlybootup
if any SE driver turn off the clock before real console gets probe,
the device will crash because of unclocked access by earlycon.

In order to fix this move the console device definition up in DT file
this ensures that console probe is called before other SE drivers.

Change-Id: I341940fd56890b9c6b316fd767eb79d384948efd
2020-08-16 20:40:58 +05:30
qctecmdr
a090b1b4af Merge "ARM: dts: msm: Add IMEM location to disable PIL timeout" 2020-08-16 05:04:35 -07:00
qctecmdr
efb327fdf3 Merge "ARM: dts: msm: Add addtional KGSL SMMU clocks" 2020-08-16 05:04:35 -07:00
qctecmdr
a3fe2bf99e Merge "ARM: dts: msm: Enable new download/restart mode drivers for Shima" 2020-08-16 05:04:35 -07:00
qctecmdr
cda462d600 Merge "ARM: dts: msm: Updates V2 memory map for Shima" 2020-08-16 05:04:35 -07:00
qctecmdr
bac708db85 Merge "ARM: dts: msm: Do not disable modem PIL for Lahaina APQ" 2020-08-16 05:04:35 -07:00
qctecmdr
5a6e934799 Merge "ARM: dts: msm: Add pm qos dt entries for sdcard" 2020-08-16 02:32:34 -07:00
Gopala Krishna Nuthaki
b29ddb75db ARM: dts: qcom: Update pm6150l alarm and gfx regulator cdev config
Update pm6150l alarm and gfx regulator cooling devices with
proper node names.

Change-Id: I727d3f5fd6def13940eda0f667a95c0412baa4f0
2020-08-15 22:19:07 +05:30
qctecmdr
079d79d59b Merge "ARM: dts: msm: Add gpu gaming bin support for holi" 2020-08-15 07:11:21 -07:00
qctecmdr
959d1c957f Merge "ARM: dts: qcom: Update bus votes for DDR5" 2020-08-15 07:11:21 -07:00
Yuanfang Zhang
4e3781ad67 ARM: dts: msm: disable wcss cti on holi
Wcss cti need be disabled on holi.

Change-Id: I0b79eb9a092ec9d442377a7d0cc72708710e0e49
2020-08-15 20:31:05 +08:00
Guru Das Srinagesh
f34b782043 ARM: dts: msm: add SPMI PMIC arbiter device for sdxlemur
Add an SPMI PMIC arbiter device so that it is possible to
communicate with PMICs attached to the SPMI bus.

Change-Id: I72b1def1fb68d9eccf9e80c1e6968a09234ac245
2020-08-14 14:53:47 -07:00
Guru Das Srinagesh
9c1e7c2540 dt-bindings: qcom-pmic-gpio: Add PMX65 bindings
Update the Qualcomm Technologies, Inc. PMIC GPIO binding
documentation to include compatible strings for PMX65.

Change-Id: Ifc4b0b1a159577e162786c776797569420785b84
2020-08-14 14:53:47 -07:00
Santosh Mardi
431033c05a ARM: dts: qcom: update ddr voting device for holi target
Holi target does not support different ddr types, update
dcvs ddr voting devices to use default voting driver.

Change-Id: I7122c1bf95769b4cad7a93f4ba2954c4da1ceb47
2020-08-14 21:50:37 +05:30
Rajeev Nandan
80c7f22eaf ARM: dts: qcom: add support for backlight cooling device on Holi
This change adds support for backlight cooling device on
Holi target.

Change-Id: I0a13a8ed6a4549918f8cf682dbc99922f75b52d7
2020-08-14 15:33:54 +05:30
Mayank Grover
aea6246b6d ARM: dts: msm: Add support for SCM PAS for holi
The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.

Change-Id: I9a0537930a246705382dc727f1014b397b982ec3
2020-08-14 13:03:25 +05:30
Vatsal Bucha
b19423527b ARM: dts: msm: Include audio overlay in shima idps dts
Include audio overlay file in shima idps.

Change-Id: If9a55ebe9ac38d425f512b95b2b748d86895ca66
2020-08-13 21:23:56 -07:00
Lina Iyer
768d25aa4c ARM: dts: msm: update cpuidle state definitions
Update CPU definitions to specify cpu power down state.

Change-Id: Ib0f63b72f7ae58ae00f320f0e9b068cc92a94011
2020-08-13 21:14:52 -06:00
Chris Lew
3242c0ee5e ARM: dts: msm: Remove CPU and reserved memory for trustedvm
The reserved memory nodes will be generated and overlayed at runtime
when the trustedvm is started. Remove these nodes from the base device
tree.

In addition, reduce the cpu core usage by changing the vcpu vmconfig
and removing the nodes for CPU[2..7].

Change-Id: I24e66bcc87621289b093e2d6781e201b18430029
2020-08-13 21:12:14 -06:00
Chris Lew
c5bf93afcd ARM: dts: msm: Change SLPI QRTR net id
Move SLPI QRTR to Net ID 2. This will enable qrtr forwarding between
SLPI and HSP.

Change-Id: Idee1bccc9a2f92df771dfd278ca064f73274b659
2020-08-13 13:10:08 -07:00
Gopala Krishna Nuthaki
e906608c74 ARM: dts: qcom: Add PMIC and GPU config thermal zones for SHIMA
Add GPU, alaram and bcl thermal mitigation rules and
update NSP thermal mitigation rules for SHIMA.

Change-Id: Ic29b8b53b97b49adb2538c914d03d1937d950256
2020-08-14 00:03:53 +05:30
Raghu Ananya Arabolu
c675971a66 ARM: dts: qcom: Add clocks to access KGSL SMMU register space
Add GPU_CC_CX_GMU_CLK, GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK, GPU_CC_HUB_AON_CLK
and GPU_CC_HUB_CX_INT_CLK clock to the list of clocks to vote for in
order to access the KGSL SMMU register space.

Change-Id: Ia91e01ed4758caff7a050ce41f67247682fc8ebe
2020-08-13 10:48:26 -07:00
qctecmdr
2ac81c29c7 Merge "ARM: dts: msm: Change the SMPS2C max-voltage to 0.95V for shima" 2020-08-13 10:28:12 -07:00
Jishnu Prakash
511f80906a ARM: dts: msm: Correct ADC_TM interrupt name
Correct ADC_TM interrupt name for PM7250b and PM6150l to
match value from ADC_TM driver on msm-5.4.

Change-Id: I88d5959ed10d26d3155b40239fcab8c06dc4c6c5
2020-08-13 18:40:52 +05:30
qctecmdr
9d1c0028f7 Merge "ARM: dts: msm: Add entry for non secure display heap memory" 2020-08-13 04:49:32 -07:00
qctecmdr
dfe5e75250 Merge "ARM: dts: msm: Add device tree for Shima for IDPS with digital mics" 2020-08-13 04:49:32 -07:00
Mukesh Ojha
547d838270 ARM: dts: msm: Enable new download/restart mode drivers for Shima
Enable download/restart mode drivers for Shima.

Change-Id: If8ef6b227705e8e701a4a9c6aecc3a91c0aaba7d
2020-08-13 03:59:07 -07:00
Sahitya Tummala
4155c3044c ARM: dts: msm: set NAV path permission to rmtfs shared buffer on Shima
Set NAV permission to rmtfs shared memory buffer as the MSS CE is
connected to NAV block on Shima.

Change-Id: I97652e300a3a3679db4cecb71bec4aa5714f3864
2020-08-13 15:54:10 +05:30
Meng Wang
9061535fa2 ARM: dts: msm: add audio support for Lahaina HDK
on Lahaina HDK device, only one WSA and normal headset is
supported. Update audio devicetree setting for Lahiana HDK.

Change-Id: Ide86b98ef78c68280e1d1369a7875f2be32f8213
2020-08-13 16:12:12 +08:00
Vatsal Bucha
58c3dc4192 ARM: dts: qcom: Add support for CPS speaker protection
Add static cps speaker protection configurations to
enable cps speaker protection feature.

Change-Id: I0da3f58702d110311ffca22f042b72933fcdeccc
2020-08-13 00:38:35 -07:00
Faiyaz Mohammed
e4129e0511 ARM: dts: msm: Add the mem-buf device for Shima
Add the mem-buf device for shima to enable memory transfers
between VMs.
The role of the mem-buf driver on the primary VM is to satisfy
allocation requests. There is no realistic scenario in which it
would need to allocate memory from other VMs, so mark the mem-buf
device as a supplier for the primary VM.

Change-Id: Id675fbe6d065063227a518ba66a275910fd12e3e
2020-08-13 10:42:47 +05:30
qctecmdr
6e22617270 Merge "ARM: dts: msm: Add PM qos and regulator dt entry for ufs" 2020-08-12 08:31:56 -07:00
qctecmdr
a105c8e036 Merge "ARM: dts: msm: Update SPI SE4 to select a static GPII number" 2020-08-12 08:31:56 -07:00
qctecmdr
2ec7d60476 Merge "ARM: dts: msm: Add DTSI entry to handle PA conf" 2020-08-12 08:31:56 -07:00
qctecmdr
16fd1654b1 Merge "ARM: dts: msm: Enable qsee drivers for shima" 2020-08-12 08:31:56 -07:00
Sandeep Singh
970685feab ARM: dts: msm: Update wlan configuration for holi
Update regulator properties and smmu sids for holi.

Change-Id: I1da89ffaeef43dea69e8ab4293d6466ad0638b37
2020-08-12 18:04:22 +05:30
Kiran Gunda
3ee451070b ARM: dts: msm: Change the SMPS2C max-voltage to 0.95V for shima
Change the SMPS2C max-voltage from 0.925V to 0.95V as per the
HW recommendation.

Change-Id: I622bb85f3d67e687e6bbb5d0253ed997a285d90c
2020-08-12 02:56:54 -07:00
qctecmdr
a14b1652ee Merge "ARM: dts: msm: Add flag to support cfgready signal bypass sw workaround" 2020-08-12 01:56:14 -07:00
qctecmdr
9ff64161ab Merge "ARM: dts: msm: add DCVS nodes for shima target" 2020-08-12 01:56:14 -07:00
qctecmdr
666e7de93c Merge "ARM: dts: msm: Add feature config node for qfprom for Shima" 2020-08-12 01:56:14 -07:00
qctecmdr
b0525a23aa Merge "ARM: dts: msm: Remove io-coherency support" 2020-08-12 01:56:14 -07:00
qctecmdr
d3d040b55c Merge "ARM: dts: msm: Add irq type value for IPA interrupts" 2020-08-12 01:56:14 -07:00
qctecmdr
e683db8c4a Merge "ARM: dts: msm: Add touch support for shima target" 2020-08-12 01:56:14 -07:00
qctecmdr
1660414788 Merge "ARM: dts: msm: fix for incorrect dt entries for holi" 2020-08-12 01:56:14 -07:00
qctecmdr
e9462460a4 Merge "ARM: dts: msm: Replace "qcom,cmb_msr_skip" with "qcom,cmb-msr-skip"" 2020-08-12 01:56:14 -07:00
Tao,Zhang
d30308cbb1 ARM: dts: msm: Add CTI config for ETB and ETR for shima
Add CTI flush and reset config to coresight device tree for ETR
and ETB for shima.

Change-Id: I607545e0085ffafae123129ce83e772a403e1475
2020-08-12 16:22:17 +08:00