Commit graph

858,634 commits

Author SHA1 Message Date
qctecmdr
1dbe00d010 Merge "msm: kgsl: Add the kgsl uapi header file" 2019-10-01 14:23:21 -07:00
Prakash Gupta
a9cbc7f9c5 iommu: iommu-debug: check valid pfn before performing ATOS ops
ATOS operation can be fatal when performed on invalid pfn. Validate mapped
entry pfn for validity before performing ATOS operation.

Change-Id: Ie1b118d768c396f91618ee1eb101754cbee5318e
Signed-off-by: Prakash Gupta <[email protected]>
[isaacm@codeaurora: Move PFN validity check prior to IOVA assignment]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-10-01 11:02:39 -07:00
Perry Randise
b8da68935f msm: ipa3: SRAM NAT, DDR NAT, back-and-forth NAT
A new application level feature has NAT running out of SRAM, DDR, or
both. The addtion of just this feature's header to the kernel will
allow it to be propagated to older kernels, such that they can be
compatible (in terms of structure size) with the new application level
feature.

Change-Id: I16b5bfaa1156c69e0a6ae0c2ca4be416a283d049
CRs-Fixed: 2437567
Signed-off-by: Perry Randise <[email protected]>
2019-10-01 13:03:44 -04:00
Lina Iyer
47e18613bc irqchip: qcom-pdc: Add IPC logging support
Add IPC logging support for debugging PDC interrupts.

Change-Id: I541acccc44cdc617a72d44ac8b3528bbc05b2e69
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:02:48 +05:30
Lina Iyer
1582c6bcd9 irqchip: qcom-pdc: Additionally set type in SPI config registers
GPIOs that can be configured as wakeup are routed to the PDC wakeup
interrupt controller and from there to the GIC interrupt controller. On
some QCOM SoCs, the interface to the GIC for wakeup capable GPIOs have
additional hardware registers that need to be configured as well to
match the trigger type of the GPIO. This register interfaces the PDC to
the GIC and therefore updated from the PDC driver.

Typically, the firmware intializes the interface registers for the
wakeup capable GPIOs with commonly used GPIO trigger type, but it is
possible that a platform may want to use the GPIO differently. So, in
addition to configuring the PDC, configure the interface registers as
well.

Change-Id: Icab7d9eeb77b5dab9d6a5a8280ce568da40b6ca6
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:02:48 +05:30
Lina Iyer
67c413154e irqchip: qcom-pdc: add irqchip set/get state calls
Add irqchip calls to set/get interrupt state from the parent interrupt
controller. When GPIOs are renabled as interrupt lines, it is desirable
to clear the interrupt state at the GIC. This avoids any unwanted
interrupt as a result of stale pending state recorded when the line was
used as a GPIO.

Change-Id: Ibd551f84d8f6ae15b8d9702faeb585a69f283f6e
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:02:38 +05:30
Lina Iyer
72ec76f95c drivers: qcom: rpmh-rsc: add IPC logging support for RSC driver
In addition to logging using FTRACE. let's also log in the IPC logging
for all RPMH transactions.

Change-Id: I2b19006bbc776053f63eee55b447428fdb023ba4
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:00:44 +05:30
Lina Iyer
7aa301db5b soc: qcom: rpmh-rsc: log interrupt status when TCS is busy
To debug issues when TCS is busy, report interrupt status as well. If
the interrupt line is pending at GIC, then Linux was too busy to process
the interrupt and if not pending then AOSS was too busy to handle the
request.

Change-Id: I8fd8289c74a8e1d6c771b77c2800a52f18c3a0b2
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:00:44 +05:30
Lina Iyer
d1c7802611 soc: qcom: rpmh: Fix sending incorrect data during rpmh flush
During flush of current cached data, Sleep and Wake TCSes have
previously programmed data present. Due to this incorrect data
is sent.

Fix this by cleaning TCSes and freshly program current cached
sleep and wake data.

Change-Id: I8f1cb9925a7800aad65d665192d3b129c76dd9de
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 18:00:35 +05:30
Lina Iyer
2f5cb5c667 ARM: smp: export pending IPI state
Record and export if an IPI is pending on the current CPU. Knowing if an
IPI is pending helps make better idle state determinations.

Change-Id: I92ab0aaeb3162cd312aa00a4e3eb978be2ad8efc
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 17:56:59 +05:30
Channagoud Kadabi
8790fa13c4 drivers: clksource: add API to return cval
Sleep driver needs to program the absolute clock value for next expiry
into pdc register for system wake up. Add an API to read the cval low
and high counters.

Change-Id: I3f08b3320ea281894d46f3c4bb0862784cc337a1
Signed-off-by: Channagoud Kadabi <[email protected]>
Signed-off-by: Lina Iyer <[email protected]>
2019-10-01 17:56:44 +05:30
Ashok Vuyyuru
6f2b5a7729 msm: ipa4: Fix to add wake up handle for coalescing pipe
Changes to add wake up handle for coalescing pipe.

Change-Id: I0cfc38c91a6a5b93211933f0af87640cbec8a4bf
Signed-off-by: Ashok Vuyyuru <[email protected]>
2019-10-01 00:08:58 -07:00
Prakash Gupta
c1c73311c3 iommu: iommu-debug: Add support for page table dump
Add support for page table dump for test domain.

eg:
cd /d/iommu/tests/soc:apps_iommu_test_device
echo 1 > attach
echo 0x20000,0x80000000,0x10000,0x1 > map
echo 0x21000,0x1000 > unmap
echo 0x24000,0x1000 > unmap
cat iommu_page_tables

---[ start ]---
0x0000000000020000-0x0000000000021000 4K PTE USR ro x AF NG DEVICE/nGnRnE
0x0000000000022000-0x0000000000024000 8K PTE USR ro x AF NG DEVICE/nGnRnE
0x0000000000025000-0x0000000000030000 44K PTE USR ro x AF NG DEVICE/nGnRnE

Change-Id: I56ac2615c4aa30dd75a2cdc1cf46de042e681cdc
Signed-off-by: Prakash Gupta <[email protected]>
[[email protected]: Explicitly set final entry in the markers array]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-30 16:38:43 -07:00
Sudarshan Rajagopalan
4439f330f7 dma-mapping-fast: add support for atomic fastmap allocations
Support for coherent and non-coherent atomic allocations
in fastmap.

Change-Id: I3628508a4b2af5aa82d56a4a6a6ee4cef98cd47f
Signed-off-by: Sudarshan Rajagopalan <[email protected]>
[[email protected]: Leverage atomic DMA pool framework code]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-30 14:02:39 -07:00
Chris Goldsworthy
bda68082e0 defconfig: enable reserved memory check on Lahaina
Enable a check to see if devices with reserved memory regions allocate from
those regions, when using the DMA API for allocations.  WARN_ON if check
doesn't pass.

Change-Id: Ic788dc4638d83cdf8a1e34f60efe678b9639d4b3
Signed-off-by: Chris Goldsworthy <[email protected]>
2019-09-27 11:06:48 -07:00
Chris Goldsworthy
d9c9998b16 of: reserved_mem: Check that memory reserved in device tree is in use
Inside of dma_alloc_attrs(), verify that devices with a reserved memory
region are actually using the region, in order to prevent wastage of
memory.

Change-Id: I56852a761d3253ec2a3a7db0f6501c73983e55c6
Signed-off-by: Chris Goldsworthy <[email protected]>
2019-09-27 10:25:31 -07:00
qctecmdr
b94e0753f5 Merge "ion: remove cpu binding of pool refill kthreads" 2019-09-26 18:19:14 -07:00
qctecmdr
50d99abda8 Merge "soc: qcom: qmi_interface: Remove ineffective mutex lock from txn struct" 2019-09-26 17:45:36 -07:00
qctecmdr
af0b277dbf Merge "soc: qcom: qmi_interface: Add send timeout helper" 2019-09-26 17:08:56 -07:00
qctecmdr
270e085d20 Merge "soc: qcom: qmi: Remove txn idr entry in qmi handle release" 2019-09-26 16:36:26 -07:00
qctecmdr
7eb503f63d Merge "msm: ipa: add the version check for FnR stats ioctl" 2019-09-26 15:47:34 -07:00
qctecmdr
049152c66e Merge "soc: qcom: qmi_interface: sync release and data_ready callback" 2019-09-26 15:11:14 -07:00
Bojun Pan
a7cdc47c78 msm: ipa: add the version check for FnR stats ioctl
Add version check for FnR stats ioctl and error return,
since only IPA4.5+ HW will support this feature.

Change-Id: If5c5021d16bc1ee6af516d9e2200c3e6b5081d27
Signed-off-by: Bojun Pan <[email protected]>
2019-09-26 14:21:53 -07:00
qctecmdr
872e13b08b Merge "ipa3: add hasting AP+STA quota/stats support" 2019-09-26 13:41:31 -07:00
Harshdeep Dhatt
c3f8417829 msm: kgsl: Add the kgsl uapi header file
Add the UAPI header file for the KGSL Adreno GPU driver.

Change-Id: I7de3f8d2bcb39cefb26cd0720388108578d158e4
Signed-off-by: Harshdeep Dhatt <[email protected]>
2019-09-26 14:34:45 -06:00
qctecmdr
14b5a2da73 Merge "ion: msm: Correct memory-region of_node reference counting" 2019-09-26 11:14:33 -07:00
Skylar Chang
566b07e021 ipa3: add hasting AP+STA quota/stats support
Add uc event ring to have ipa-uc monitor the
quota and bw-voting threshold to generate the
irq to ipa-driver to inform if quota or and bw
threshold is hit.

Change-Id: I7ce9c1a0048016fc6b6248a1632365f51717422c
Signed-off-by: Skylar Chang <[email protected]>
2019-09-26 10:55:19 -07:00
qctecmdr
1aea860783 Merge "Revert "staging: android: ion: Use the MSM dmabuf ops when possible"" 2019-09-26 10:38:24 -07:00
qctecmdr
4f857060ef Merge "ion: msm: Update the heap IDs as per the ION core standards" 2019-09-26 10:03:02 -07:00
qctecmdr
306f178df8 Merge "msm: ipa3: remove ipa3_ctx access from wan driver and qmi service" 2019-09-26 09:16:12 -07:00
qctecmdr
f2b18e2809 Merge "include: dt-bindings: ion: Add header for the MSM ION heap IDs" 2019-09-26 08:47:42 -07:00
qctecmdr
af4a510da5 Merge "ion: msm: Define heap IDs as constants in their own file" 2019-09-26 08:08:29 -07:00
Isaac J. Manjarres
9fa87fcfa2 iommu/arm-smmu: Adopt bitfield model for remaining SMMU registers
Migrate the remaining register offset macros to bitfields.

Change-Id: I58659c69e3c6b5b3b3c7ec360492a00d8e65514e
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:52 -07:00
Robin Murphy
45eebc8243 iommu/arm-smmu: Add reset implementation hook
Reset is an activity rife with implementation-defined poking. Add a
corresponding hook, and use it to encapsulate the existing MMU-500
details.

Change-Id: I674738a3d93af8152282d645a2d1c0e4f1ff5dd9
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 62b993a36e
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:51 -07:00
Robin Murphy
4670e9e03e iommu/arm-smmu: Add context init implementation hook
Allocating and initialising a context for a domain is another point
where certain implementations are known to want special behaviour.
Currently the other half of the Cavium workaround comes into play here,
so let's finish the job to get the whole thing right out of the way.

Change-Id: I2fc1b383a5084d6a92e99002ed12b610e0cf7b04
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: ba7e4a08bb
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:51 -07:00
Robin Murphy
7d0946b9a3 iommu/arm-smmu: Move Secure access quirk to implementation
Move detection of the Secure access quirk to its new home, trimming it
down in the process - time has proven that boolean DT flags are neither
ideal nor necessarily sufficient, so it's highly unlikely we'll ever add
more, let alone enough to justify the frankly overengineered parsing
machinery.

Change-Id: I86a898715cb1d036949df4dcf7333068bcf64836
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 6d7dff62af
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:50 -07:00
Robin Murphy
9f896c0d49 iommu/arm-smmu: Add configuration implementation hook
Probing the ID registers and setting up the SMMU configuration is an
area where overrides and workarounds may well be needed. Indeed, the
Cavium workaround detection lives there at the moment, so let's break
that out.

Change-Id: I2b828a98981866a1a5adf21555055b8a4c9788d2
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 3995e18689
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolve trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:50 -07:00
Robin Murphy
2027b20101 iommu/arm-smmu: Add implementation infrastructure
Add some nascent infrastructure for handling implementation-specific
details outside the flow of the architectural code. This will allow us
to keep mutually-incompatible vendor-specific hooks in their own files
where the respective interested parties can maintain them with minimal
chance of conflicts. As somewhat of a template, we'll start with a
general place to collect the relatively trivial existing quirks.

Change-Id: Ie1ee37e9250a8295bc07cb78d879b98452f50920
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: fc058d37b3
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflics and build errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:50 -07:00
Robin Murphy
e0ced41cce iommu/arm-smmu: Rename arm-smmu-regs.h
We're about to start using it for more than just register definitions,
so generalise the name.

Change-Id: I15630ae6f50ce8c10a624542038275861608174d
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: c5fc64881f
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:49 -07:00
Robin Murphy
74b884d08e iommu/arm-smmu: Abstract GR0 accesses
Clean up the remaining accesses to GR0 registers, so that everything is
now neatly abstracted. This folds up the Non-Secure alias quirk as the
first step towards moving it out of the way entirely. Although GR0 does
technically contain some 64-bit registers (sGFAR and the weird SMMUv2
HYPC and MONC stuff), they're not ones we have any need to access.

Change-Id: I254eef03e4350fc2abf60547e860c5c65cedafc4
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 00320ce650
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:49 -07:00
Robin Murphy
c4803f35a2 iommu/arm-smmu: Abstract context bank accesses
Context bank accesses are fiddly enough to deserve a number of extra
helpers to keep the callsites looking sane, even though there are only
one or two of each.

Change-Id: I4ec6ce09eae4c41d228086b15574c3e9e816f552
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 19713fd40d
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:48 -07:00
Robin Murphy
49eaf1034e iommu/arm-smmu: Abstract GR1 accesses
Introduce some register access abstractions which we will later use to
encapsulate various quirks. GR1 is the easiest page to start with.

Change-Id: I2dfb3a12ebcb705874f75799ec6f1997abf488ff
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: aadbf2143a
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:48 -07:00
Robin Murphy
bdb627108e iommu/arm-smmu: Get rid of weird "atomic" write
The smmu_write_atomic_lq oddity made some sense when the context
format was effectively tied to CONFIG_64BIT, but these days it's
simpler to just pick an explicit access size based on the format
for the one-and-a-half times we actually care.

Change-Id: I5b4ca8162c801aa320576ff3d31bb20acca9b1f8
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-repo: 6100576284
Git-commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:47 -07:00
Robin Murphy
d2eac4d855 iommu/arm-smmu: Split arm_smmu_tlb_inv_range_nosync()
Since we now use separate iommu_gather_ops for stage 1 and stage 2
contexts, we may as well divide up the monolithic callback into its
respective stage 1 and stage 2 parts.

Change-Id: I566d03bd7941baedcbc2345ffdeefcb4041e9b54
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 71e8a8cdaf
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:47 -07:00
Robin Murphy
d683e0f78c iommu/arm-smmu: Rework cb_base handling
To keep register-access quirks manageable, we want to structure things
to avoid needing too many individual overrides. It seems fairly clean to
have a single interface which handles both global and context registers
in terms of the architectural pages, so the first preparatory step is to
rework cb_base into a page number rather than an absolute address.

Change-Id: I2401a30f38550823a60421355d73c4306d0613ed
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 490325e0c1
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolve trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:46 -07:00
Robin Murphy
352cdae88d iommu/arm-smmu: Convert context bank registers to bitfields
Finish the final part of the job, once again updating some names to
match the current spec.

Change-Id: I405fa064194b5c90b13935fb37b36ba9e8ee35c0
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 620565a76b
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts/build time errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:46 -07:00
Robin Murphy
3838623d1d iommu/arm-smmu: Convert GR1 registers to bitfields
As for GR0, use the bitfield helpers to make GR1 usage a little cleaner,
and use it as an opportunity to audit and tidy the definitions. This
tweaks the handling of CBAR types to match what we did for S2CR a while
back, and fixes a couple of names which didn't quite match the latest
architecture spec (IHI0062D.c).

Change-Id: Ic6833f472f162ab6080aaba37b8259e573436a65
Signed-off-by: Robin Murphy <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Git-commit: 5114e96cb2
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:45 -07:00
Robin Murphy
67ddab5056 iommu/arm-smmu: Convert GR0 registers to bitfields
FIELD_PREP remains a terrible name, but the overall simplification will
make further work on this stuff that much more manageable. This also
serves as an audit of the header, wherein we can impose a consistent
grouping and ordering of the offset and field definitions

Change-Id: I3935f9f9b7526cb5c5906093131e856159b0899b
Signed-off-by: Robin Murphy <[email protected]>
Git-commit: 0caf5f4e84
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[[email protected]: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:45 -07:00
Isaac J. Manjarres
5a61571110 iommu/arm-smmu: Fix SMMU derivation in arm_smmu_power_off_atomic
The arm_smmu_power_off_atomic() function derives the pointer to
the SMMU device by incorrectly assuming that all devices in the
power resources structures store that pointer as part of their
driver data.

While this is true for devices that represent an SMMU, this is
not the case for the devices that represent the TBUs, as they
store the TBU structures instead of a pointer to the SMMU device.
Thus, require the SMMU device as a parameter to the
arm_smmu_power_off[_atomic] functions so that it can be used
correctly.

Change-Id: I0101500468afe17456bd6178082850e5fa6590d7
Signed-off-by: Isaac J. Manjarres <[email protected]>
2019-09-25 22:48:31 -07:00
Chris Goldsworthy
79c240605e of: reserved_mem: add missing of_node_put() for proper ref-counting
Commit d698a38814 ("of: reserved-memory: ignore disabled memory-region
nodes") added an early return in of_reserved_mem_device_init_by_idx(), but
didn't call of_node_put() on a device_node whose ref-count was incremented
in the call to of_parse_phandle() preceding the early exit.

Fixes: d698a38814 ("of: reserved-memory: ignore disabled memory-region nodes")
Change-Id: I293be0fb7f86a1e6e4d4d7277039a881e590d5e0
Signed-off-by: Chris Goldsworthy <[email protected]>
2019-09-25 14:10:42 -07:00