If there is no change in CSID and TFE clock rates
then correctly assign current clock rates to local
varaibles.
CRs-Fixed: 2855742
Change-Id: Ibd71274ba7a7844c3841060eb3b3b14ba80ed4b0
Signed-off-by: Shravya Samala <shravyas@codeaurora.org>
Add new packer format to support LSB alignment for plain16_10
packer format.
CRs-Fixed: 2825675
Change-Id: I401241dc14dc67d3b363d3d39b37aabe716e167c
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
Added checks to confirm CSID frequency greater than
CSIPHY frequency, TFE frequency greater than CSID
frequency. Also TFE frequency should be such that
it can accommodate PHY data rate.
CRs-Fixed: 2847155
Change-Id: I5d3dcc53a6f27129f4b82cba1254445f58f6d0cf
Signed-off-by: Shravya Samala <shravyas@codeaurora.org>
This change add cpas hw version map entry for 680 titan
version. And remove cpas version check for ubwc support.
CRs-Fixed: 2825675
Change-Id: I858838a5a774c964a1a09d96114442f69058670a
Signed-off-by: Ayush Kumar <ayushkr@codeaurora.org>
Qchannel interface is used to ensure camnoc is idle. This needs
to be check before camera core power collapse and after camera core
power on sequence to make sure camera hw blocks are in proper state.
CRs-Fixed: 2847646
Change-Id: If9dbd980c2e8e983ac973f91e3d1ed132719c395
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
CDM driver check for available bl fifo slots before
submitting to HW. If no free slots available then
it wait for CDM HW to process all the BLs and return
available slots.
CDM driver was incorrectly calculating the available bl
slots and causing bl fifo overflow.
Corrected the sequence in wait for bl fifo logic.
CRs-Fixed: 2837583
Change-Id: I2861f8c66822e0739f0546eaf153d8e2af0caefe
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Add support to configure the incoming format in the top
core Camif register. Changes in CSID file to support YUV
TPG are also integrated.
CRs-Fixed: 2846873
Change-Id: I87fa0171a60013ba356a33455170cf1ecfbb0563
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
When we have smmu page fault of unmapped address and
active flag is false we can cache and store unmapped
address and print in case of error.
Added check for last flushed req during config hw for
jpeg as well.
CRs-Fixed: 2834236
Change-Id: I9b9bb735587799871f9bdef94985f6269ca6a29d
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
All csiphy hw common register need to program on first streamon
from any of csiphy hw in order to reduce the noise interferance
for other csiphy hw.
CRs-Fixed: 2839793
Change-Id: I256307b8b909da4a940be25a3aab60e8a301b6f8
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
last_applied_idx is updated on every successful applied
request and the buf_done. After buf_done last_applied_idx
is set to -1. While accessing last applied req the same
index is used, if the last_applied_idx is -1 accessing
last applied request will result in slab out of bound
error, so check last_applied_idx before accessing
last applied request.
CRs-Fixed: 2840329
Change-Id: I8f49b9df097859cde20e651149167db7316976bb
Signed-off-by: Tejas Prajapati <tpraja@codeaurora.org>
There is chance that handle error info get scheduled
after cdm deinit. As clock and regulator gets disabled
as part of deinit so this can cause issue for cdm hw
interaction as part of handle error.
Added cdm power state check before dumping CDM HW
status at the time of error.
CRs-Fixed: 2833653
Change-Id: I4bf01ce3900196909cf66ffdb24607c50ab03295
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
In certain scenarios, ICP init response
was not received on time.
Hence added retry logic to counter ICP
init failures.
CRs-Fixed: 2836166
Change-Id: Ibfab1e44e320dbcb1e1b47ba91d91c5ef2f9b3c1
Signed-off-by: Shravya Samala <shravyas@codeaurora.org>
Sometimes multiple io cofigs comes before start_dev. Therefore even we
force disable UBWC compression at start_dev time it can be override by
those io configs. Therefore moving disable UBWC comp logic to acquire
time. Acquire time a flag is sent if we have to enable or disable ubwc
compression, based on this we set bus side ubwc_disable flag. When ever
we start the WM or update the WM UBWC config we check this flag and
based on this flag we override the ubwc_mode_cfg register.
CRs-Fixed: 2833514
Change-Id: I8efc3f7abd53e0757f8e77ac0788e303f7c695b9
Signed-off-by: Wyes Karny <wkarny@codeaurora.org>
Sometimes, the cpu load is very high, then the devcies
stream on will be delayed, but the CRM watchdog is already
enabled before streaming on, then we will have a chance to
notify SOF freeze issue.
This change pauses the CRM watchdog timer before streaming
on sensor and after stopping ife, when we can detect the
stream on and stream off delay, but don't notify error,
also can detect the real SOF freeze issue.
CRs-Fixed: 2804587
Change-Id: Iccaee837930ea22290b109eff45b05300d844312
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
