Commit graph

893,580 commits

Author SHA1 Message Date
qctecmdr
e1eeda2440 Merge "icc: dt-bindings: add endpoint IDs for interconnects for SM6150" 2021-01-22 13:46:42 -08:00
qctecmdr
152d15378a Merge "coresight: cti: Solve boot up issue" 2021-01-22 10:04:02 -08:00
qctecmdr
1dd7418832 Merge "msm: kgsl: Fix nr_removed calculation while reducing pools" 2021-01-22 10:04:02 -08:00
qctecmdr
652039e88a Merge "msm: kgsl: Enable GMU BW scaling and update CP ROQ size" 2021-01-22 10:04:01 -08:00
qctecmdr
c23063ec72 Merge "serial:msm_geni_serial: Handling the cts counter in uart driver" 2021-01-22 10:04:01 -08:00
qctecmdr
f18fc34265 Merge "arm: defconfig: enable firmware loader helper" 2021-01-22 10:04:01 -08:00
qctecmdr
372a5f3f6d Merge "arm64: defconfig: Enable PDC device for sdmsteppeauto" 2021-01-22 10:04:00 -08:00
qctecmdr
7e44485813 Merge "drivers: thermal: Use lock before accessing thermal instance list" 2021-01-22 10:04:00 -08:00
Veera Vegivada
9256ad8778 icc: dt-bindings: add endpoint IDs for interconnects for SM6150
Add master and slave ID constants for all Qualcomm Technologies, Inc.
SM6150 interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I883cee60db070c45191b1a7ecec07f90a2c49190
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-22 10:31:36 +05:30
qctecmdr
dabe161962 Merge "msm: kgsl: Take devfreq event lock for ddr qos vote" 2021-01-21 18:57:27 -08:00
qctecmdr
cfb54b7fe5 Merge "mhi: core: Fix format specifier in mhi_alloc_bhie_table" 2021-01-21 18:57:27 -08:00
qctecmdr
669cc6266d Merge "cnss2: Minor enhancements for the driver" 2021-01-21 18:57:27 -08:00
qctecmdr
b7cbe3beb1 Merge "input: qcom-hv-haptics: ensure HBoost is ready before the play" 2021-01-21 15:17:06 -08:00
Hemant Kumar
6e9760c26f mhi: core: Fix format specifier in mhi_alloc_bhie_table
BHIe table size is printed incorrectly as unsigned long.
size is of type size_t hence use %zu instead of %lu.

Change-Id: Ic52bc6ea92e6dac8bd1e275f9a17986d08e2da79
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-01-21 09:39:50 -08:00
qctecmdr
2adfda1e32 Merge "cnss2: Add a 128kB to prealloc pool" 2021-01-21 08:58:51 -08:00
qctecmdr
2194883a58 Merge "interconnect: qcom: Fix re-initializing the bcm" 2021-01-21 08:58:51 -08:00
qctecmdr
eadeaeb231 Merge "sched/fair: Add sched_sync_hint_enable node" 2021-01-21 08:58:51 -08:00
qctecmdr
213e25baa7 Merge "usb: dwc3: gadget: Replace dev with its parent sysdev in ep_disable" 2021-01-21 08:58:50 -08:00
qctecmdr
12280a383f Merge "defconfig: enable debug page alloc config for holi" 2021-01-21 08:58:50 -08:00
qctecmdr
f9595c4291 Merge "soc: qcom: hab: add the guest_shm.h header file" 2021-01-21 08:58:50 -08:00
qctecmdr
156d735064 Merge "usb: phy: qmp: add missing hardware orientation debug function" 2021-01-21 08:58:49 -08:00
qctecmdr
8fea7e8845 Merge "ion: msm: dump invalid heap id" 2021-01-21 08:58:49 -08:00
Harshdeep Dhatt
2f2e145e4b msm: kgsl: Take devfreq event lock for ddr qos vote
This lock protects against any concurrent governor re-assignments
through sysfs. Furthermore, such re-assignment can lead to another
issue i.e. say someone assigns performance governor to this device
from sysfs. Then there can be a mismatch in what kgsl intends to
vote, and what actually gets voted. Therefore, fix both the min and
max frequencies for this devfreq device at the desired qos level so
that the intended vote is propagated regardless of the governor.

Change-Id: Ibc3b0ef1f585dae311aab028d8c2bc9f1a53b4b8
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2021-01-21 09:30:01 -07:00
qctecmdr
bd07c963db Merge "defconfig: Enable IPC logs for sdxlemur" 2021-01-21 04:59:13 -08:00
qctecmdr
31b7bc4b6d Merge "cnss2: Add support XO Clock selection leakage prevention" 2021-01-21 04:59:13 -08:00
qctecmdr
58dc954a3e Merge "net: qrtr: print error case for qrtr receive" 2021-01-21 04:59:13 -08:00
qctecmdr
e1a635a475 Merge "soc: qcom: mem-offline: isolate freepages in pageblock boundaries" 2021-01-21 04:59:12 -08:00
qctecmdr
b6766e400a Merge "msm: kgsl: Add GPU snapshot to minidump" 2021-01-21 04:59:12 -08:00
qctecmdr
154883363d Merge "msm: ipa: add mechanism to configure aggregation timeout" 2021-01-21 04:59:12 -08:00
qctecmdr
1fb9e4026b Merge "devfreq: Add devfreq-cpufreq governor" 2021-01-21 04:59:12 -08:00
Yuanfang Zhang
c20a1bfcc7 coresight: cti: Solve boot up issue
Move the read register DVID operation to function show_info_show()
to avoid boot up issue.

Change-Id: Ice7f09f6dc77a93c2709cb3c34ae80efb67095c6
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-01-21 02:24:26 -08:00
qctecmdr
b0f3e1b860 Merge "clk: qcom: sm6150: define vdd_levels enum and vdd_corner[] map" 2021-01-21 01:09:21 -08:00
qctecmdr
6c81f26786 Merge "dt-bindings: msm: Add bindings for CSI PHY fuse support" 2021-01-21 01:09:20 -08:00
qctecmdr
82196787ec Merge "defconfig: gen3auto: Add IOMMU related configs" 2021-01-21 01:09:20 -08:00
qctecmdr
2568f47851 Merge "power: smb1398: Handle USB power path suspension appropriately" 2021-01-21 01:09:20 -08:00
qctecmdr
a0c321e210 Merge "cnss2: retry mhi suspend in case packets are pending in MHI layer" 2021-01-21 01:09:20 -08:00
qctecmdr
db07dbc01d Merge "net: aquantia: Change max supported IPA bandwidth" 2021-01-21 01:09:19 -08:00
qctecmdr
6efe743bf0 Merge "dmaengine: gpi: Log the assigned GPII per SE during probe" 2021-01-21 01:09:19 -08:00
qctecmdr
95cfe8c295 Merge "defconfig: Enable SMB1351 and other drivers for sdxnightjar" 2021-01-21 01:09:19 -08:00
qctecmdr
5e5bf5c150 Merge "drivers: pinctrl: qcom: Add SM6150 pinctrl driver" 2021-01-21 01:09:19 -08:00
qctecmdr
6c35b44472 Merge "defconfig: gen3auto: Enable LLCC driver" 2021-01-21 00:44:32 -08:00
qctecmdr
3909534a7a Merge "defconfig: sdxlemur: Remove CONFIG_NO_VM_RECLAIM" 2021-01-21 00:44:32 -08:00
qctecmdr
ab09338b78 Merge "defconfig: gen3auto: Enable msm_geni_console" 2021-01-20 23:52:15 -08:00
qctecmdr
56dfee3f47 Merge "defconfig: enable CONFIG_ARM_SMMU_SELFTEST for debug config" 2021-01-20 23:52:15 -08:00
qctecmdr
38de743e5a Merge "ANDROID: usb: gadget: Do not disconnect unregistered dev" 2021-01-20 23:52:15 -08:00
qctecmdr
5d0cb44821 Merge "scsi: ufs: Hold auto suspend until ufs async scan completes" 2021-01-20 23:52:13 -08:00
qctecmdr
fed9b0b727 Merge "drivers: soc: Add support for SDMSHRIKE llcc driver" 2021-01-20 23:52:13 -08:00
Biao Long
e8f6113085 sched/fair: Add sched_sync_hint_enable node
Add sched_sync_hint_enable not to enable/disable sync.

Change-Id: Id6bdff3d4b9ea1051d7b55ca4cfd1d802c92fa64
Signed-off-by: Biao Long <blong@codeaurora.org>
2021-01-21 08:55:43 +08:00
Mahesh Kumar Kalikot Veetil
200b7dec04 cnss2: Add a 128kB to prealloc pool
WLAN host driver has a new memory requirement for regulatory structure
allocation of order 5. Increase 128 kB slot by one.

Change-Id: If95291c96df0b7588b54f8e19b287d846896b479
Signed-off-by: Mahesh Kumar Kalikot Veetil <mkalikot@codeaurora.org>
2021-01-20 14:19:47 -08:00
Yue Ma
5d442d9b68 cnss2: Minor enhancements for the driver
Use default RAM dump size if it is not defined in device tree node.
Also print MSI 64-bit address (high and low 32-bit) for debug purpose.

Change-Id: Iff382862e5a04ce995f2ec3bfeffaf7a1f6b78ee
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-01-20 11:44:46 -08:00