Commit graph

890,618 commits

Author SHA1 Message Date
qctecmdr
e41274f413 Merge "msm: kgsl: Disable stall on fault for GMU context bank" 2020-09-09 06:09:23 -07:00
qctecmdr
ffa0965a61 Merge "Revert "msm: pcie: add support to manage PCIe PHY PLL block"" 2020-09-09 06:09:23 -07:00
qctecmdr
6022ecf539 Merge "soc: qcom: add disable/enable SPSS SSR ioctl()" 2020-09-09 06:09:22 -07:00
qctecmdr
f532a03ce3 Merge "mmc: sdhci-msm: Add the missing check in sdhci_msm_check_power_status" 2020-09-08 20:31:26 -07:00
qctecmdr
1bb98f4d32 Merge "usb: dwc3: gadget: improve several ipc log" 2020-09-08 20:31:26 -07:00
qctecmdr
c9b46ab6d1 Merge "mmc: sdhci_msm: Allow turning off SD card's power during initialization" 2020-09-08 20:31:25 -07:00
qctecmdr
6e3916956f Merge "mmc: sdhci-msm: Disable always-on LDO's when eMMC is absent" 2020-09-08 20:31:25 -07:00
qctecmdr
ec45079898 Merge "arm64: defconfig: Enable L3 interconnect driver for Holi" 2020-09-08 20:31:24 -07:00
qctecmdr
2ac873fba2 Merge "qtee_shmbridge: register bridges for CMA heaps" 2020-09-08 14:43:37 -07:00
qctecmdr
7971c5d489 Merge "power: qpnp-qg: Do not round-up/down battery SOC in BASS" 2020-09-08 14:43:36 -07:00
qctecmdr
2e5aa99ff6 Merge "icnss: Allow register/unregister driver execution in serial manner" 2020-09-08 14:43:36 -07:00
qctecmdr
3f946ae954 Merge "input: misc: qcom-hv-haptics: disable auto resonance for FIFO streaming" 2020-09-08 14:43:36 -07:00
qctecmdr
b22faefba7 Merge "scsi: ufs-qcom: configure ufs clocks core memory" 2020-09-08 14:43:35 -07:00
Odelu Kukatla
c56ba7bb9c arm64: defconfig: Enable L3 interconnect driver for Holi
Enable L3 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: I92b407621e6c65563e5e88b63cf6b776329657cb
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2020-09-07 05:48:35 -07:00
Sarthak Garg
40fdaf3134 mmc: sdhci-msm: Disable always-on LDO's when eMMC is absent
Both eMMC and UFS share the regulators (vdd & vdd-io).
On UFS based devices this regulator can be turned off after the eMMC
probe fails.

Override vdd-io-always-on flag as false.

Change-Id: I2e2abb14512d5e3f8fc0cb67d1aa734c78674cfa
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2020-09-07 17:10:19 +05:30
qctecmdr
122f4cad33 Merge "backlight: qcom-spmi-wled: Force HFRC off when WLED is disabled" 2020-09-07 01:24:47 -07:00
qctecmdr
6fb13e7c75 Merge "platform: msm: free the codec node after disconnect" 2020-09-07 01:24:47 -07:00
qctecmdr
f64f2f13d4 Merge "cpufreq: qcom: Add support for performance lock feature" 2020-09-07 01:24:47 -07:00
qctecmdr
7765a70ffe Merge "mem-offline: improve the effective utilization of movable zone" 2020-09-07 01:24:46 -07:00
qctecmdr
f048fe34f8 Merge "defconfig: lahaina: Enable F2FS_CHECK_FS for lahaina" 2020-09-07 01:24:46 -07:00
qctecmdr
a9c39c41e9 Merge "power: smb1398: Do not disable FP_FET during IREV condition" 2020-09-07 01:24:45 -07:00
Sankeerth Billakanti
4945008ef3 platform: msm: free the codec node after disconnect
The codec interface node is allocated during the codec
addition during dp connect. These changes will free the
node after the dp disconnect.

Change-Id: I6f1fc5639f1a5fa61ef04557b888b3389800dce1
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-09-06 20:35:34 -07:00
Kiran Gunda
de264826a9 backlight: qcom-spmi-wled: Force HFRC off when WLED is disabled
Apply the configuration to force HFRC off when WLED module
is disabled.

Change-Id: Iff1df47fd26a620664087eb4c9140cc4e45251bc
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
2020-09-06 20:22:07 -07:00
qctecmdr
9a469b261f Merge "Minidump: Add registration/update support for suspend context" 2020-09-06 10:39:38 -07:00
qctecmdr
ebb72ba9c7 Merge "arm64: defconfig: Enable QCOM_SPMI_WLED driver for holi" 2020-09-06 10:39:37 -07:00
qctecmdr
4bb9d8e08b Merge "power: qpnp-smb5: Do not set BC1P2_START_ON_CC on DAM" 2020-09-06 10:39:37 -07:00
qctecmdr
2a46a957b7 Merge "msm: ipa: IPAv5 updates" 2020-09-06 10:39:36 -07:00
Konstantin Dorfman
8005d59933 soc: qcom: add disable/enable SPSS SSR ioctl()
During SPSS firmware update by fota, SPSS SSR causes cryptographic erase
of Secure Processor user data. To mitigate this, instead of related
SSR, platform reboot requested during fota update. In the end of fota
update, SPSS SSR re-enabled.

This change adds ioctl() to update internal driver configuration
(functionally disable or enable SSR).

Change-Id: I1d8362b4691e1a335f7f1f29bc2358d3f9b1cb21
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Nurit Lichtenstein <nuritl@codeaurora.org>
2020-09-05 23:24:43 -07:00
qctecmdr
9eaefd9787 Merge "arm64: defconfig: Enable cpufreq hw debug for HOLI and SHIMA" 2020-09-05 23:03:23 -07:00
qctecmdr
c373fc1ff6 Merge "soc: qcom: Move watchdog suspend/resume callbacks to syscore ops" 2020-09-04 21:28:06 -07:00
qctecmdr
4afbca2a87 Merge "msm: kgsl: Define RBBM_SW_RESET_CMD for a6xx targets" 2020-09-04 21:28:05 -07:00
qctecmdr
b0f8e690f6 Merge "power: qpnp-qg: Allow signed values for Rconn property" 2020-09-04 21:28:05 -07:00
qctecmdr
8f5c855adb Merge "msm: kgsl: Set the bit mask for read-modify-write of GMU registers" 2020-09-04 21:28:05 -07:00
qctecmdr
dfcc9e01ba Merge "ASoC: soc-pcm: Fix playback shutdown sequence" 2020-09-04 21:28:04 -07:00
qctecmdr
ac90e240e6 Merge "drivers: thermal: sdpm: Add support for regulator notification" 2020-09-04 21:28:04 -07:00
Jagadeesh Kona
822d6597b7 arm64: defconfig: Enable cpufreq hw debug for HOLI and SHIMA
Enable cpufreq hw debug support for HOLI and SHIMA.

Change-Id: I62b3404b918a738addeada83a1069712c55ebc21
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-09-05 07:36:21 +05:30
qctecmdr
e3bf003c8b Merge "crypto: Fix possible stack out of bound error" 2020-09-04 18:40:15 -07:00
qctecmdr
c1f96e11b1 Merge "usb: pd: Clear send_get_status flag in protocol reset" 2020-09-04 18:40:14 -07:00
qctecmdr
7b3ceccc73 Merge "Minidump: Add update region support for minidump regions" 2020-09-04 18:40:14 -07:00
qctecmdr
5f046bd246 Merge "clk: qcom: smd-rpm: Add support for clock handoff" 2020-09-04 15:55:42 -07:00
qctecmdr
5f689b7eb5 Merge "msm: cvp: All CVP load treated as real-time" 2020-09-04 15:55:42 -07:00
qctecmdr
e826883017 Merge "power: qpnp-smb5: Update the interrupt handler names" 2020-09-04 15:55:42 -07:00
qctecmdr
9d3f22c3a5 Merge "dt-bindings: msm: Add bindings for MFHDR fuse support" 2020-09-04 15:55:41 -07:00
qctecmdr
083c252107 Merge "clk: qcom: Add BIMC logging support during kernel panic" 2020-09-04 15:55:40 -07:00
qctecmdr
c1d17bef32 Merge "cnss2: Remove unnecessary logs for Bus BW voting" 2020-09-04 13:08:02 -07:00
Taniya Das
71821a2fe9 cpufreq: qcom: Add support for performance lock feature
In the case where the 'qcom,perf-lock-support' feature is enabled the
memory region bases would be required to be provided from the device
node. Any DCVS request requires the shared memory region to be updated
before the cpufreq-hw perf desired register is updated.

Change-Id: I16d068d3311edf8e32654ab29070d4721a7c1493
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2020-09-04 22:12:58 +05:30
Vikram Sharma
2e8f5628ef dt-bindings: msm: Add bindings for MFHDR fuse support
New feature bit for MFHDR is added in binding file.

CRs-Fixed: 2770220
Change-Id: Ic0a0059df707dd51efce04b1892803ab8cbae0de
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
2020-09-04 07:40:19 -07:00
Jishnu Prakash
377eacc4b2 power: qpnp-smb5: Update the interrupt handler names
It is observed that interrupt handlers with same names across drivers
are being incorrectly mapped. Until this is fixed and to align the names
with the driver name, update the interrupt handler names.

Change-Id: Ib2aea77c0b0e53ff99c34fafc531a5291f70449c
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2020-09-04 07:09:53 -07:00
Charan Teja Reddy
aa3fa08df4 mem-offline: improve the effective utilization of movable zone
When a memory block in a movable zone is onlined, only newly allocated
or swap in anon pages will fill it. This means that the migrated pages
from these memory blocks during offlining will sit in the lower zones
despite enough free space in the movable zone thus leaving pressure in
the lower zones. This pressure can effect the performance for the
allocations which can only be satisfied from lower zones.
This is avoided by filling in eligible pages from normal zone to movable
zone thus results in effective utilization of movable zone and also free
up memory in the lower zones.

Change-Id: I3404b9078e942c98f497cb462bc24fc53fb075ba
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
2020-09-04 06:15:14 -07:00
Veerabhadrarao Badiganti
e0c9c1fe3c scsi: ufs-qcom: configure ufs clocks core memory
Configure the ufs clocks core and peripheral memory state when
turned off. This configuration is required to allow retaining
ICE crypto configuration (including keys) when ice_core_clk is
turned off, and powering down non-ICE RAMs of host controller.

Change-Id: I93584851fd50c7006ccd48979087d707ab4c6408
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[vbadigan@codeaurora.org: updated clk_set_flag API with new API]
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
2020-09-04 18:26:34 +05:30