Commit graph

877,234 commits

Author SHA1 Message Date
qctecmdr
e64e00a6da Merge "ANDROID: Re-use SUGOV_RT_MAX_FREQ to control uclamp rt behavior" 2020-02-01 21:26:28 -08:00
qctecmdr
7ea28f1f3e Merge "dt-bindings: clock: Add support for HLOS1_VOTE_SMMU_CLK" 2020-01-31 22:21:46 -08:00
qctecmdr
1a400ddd98 Merge "Add support BT/FM CHK 3.2 chip" 2020-01-31 22:21:46 -08:00
qctecmdr
2480b5f50f Merge "arm64: defconfig: enable flash LED driver on Lahaina" 2020-01-31 22:21:46 -08:00
qctecmdr
bdf10ecec5 Merge "defconfig: lahaina: remove disablement of SPMI temp alarm driver" 2020-01-31 22:21:45 -08:00
qctecmdr
b8d282e19f Merge "f_fs: Return correct USB endpoint descriptor to user space daemon" 2020-01-31 16:56:06 -08:00
qctecmdr
cbcb2fc981 Merge "hrtimer: fix issue during core isolation" 2020-01-31 16:56:06 -08:00
qctecmdr
65411a1bfd Merge "usb: dwc3-msm: Fix out-of-bounds access in bus voting" 2020-01-31 16:56:06 -08:00
qctecmdr
e2cda63632 Merge "msm: kgsl: Move secvid programming to gpudev" 2020-01-31 10:27:18 -08:00
qctecmdr
e791172b7e Merge "arm64: defconfig: Enable QRTR MHI on lahaina_debug" 2020-01-31 10:27:18 -08:00
qctecmdr
f542d726be Merge "scsi: ufs: Make crypto updates on QTI ufs" 2020-01-31 10:27:17 -08:00
qctecmdr
d806fa1378 Merge "tracing: rework sched_preempt_disable trace point implementation" 2020-01-31 10:27:17 -08:00
qctecmdr
0326bf0e0f Merge "msm: kgsl: Move APRIV config to a6xx start" 2020-01-31 04:38:34 -08:00
Satish Kodishala
a772144a04 Add support BT/FM CHK 3.2 chip
Added support for BT/FM CHK 3.2 chip. Also,
cleaned up unused chip ids.

CRs-Fixed: 2609077
Change-Id: I8a99113250bbe28fe2f10b17b90b5f00e40f852b
Signed-off-by: Satish Kodishala <skodisha@codeaurora.org>
2020-01-31 01:39:41 -08:00
qctecmdr
be8d5fe010 Merge "cpuidle: lpm-levels: update lpm_disallowed() with sched hints" 2020-01-30 23:05:04 -08:00
qctecmdr
44eb78d31e Merge "msm: cvp: Support releasing persistent buffer" 2020-01-30 23:05:03 -08:00
qctecmdr
88353cd04a Merge "arm64: defconfig: Enable MSM PCIe and MHI Host driver for lahaina" 2020-01-30 23:05:03 -08:00
qctecmdr
b74745b4f0 Merge "dwc3-msm: Add dwc3_msm_release_ss_lane() API" 2020-01-30 23:05:03 -08:00
Mayank Rana
4abb83b709 f_fs: Return correct USB endpoint descriptor to user space daemon
Some of user space daemon like ADB queries endpoint descriptor using
ioctl to know wMaxPacketSize value. Based on wMaxPacketSize value it
queues additional buffer to read zero length packet if expected read
buffer size is multiple of wMaxPacketSize. Currently driver is missing
handling for super speed plus case which results into sending full
speed related USB endpoint descriptor (i.e. wMaxPacketSize 64 bytes).
Hence when adbd is expecting 64 bytes packet from host, it queues one
more additional buffer. This results into mismatch of ADB command and
response when multiple ADB commands are used and causing different ADB
related stability issues. Fix this issue adding super speed plus check
with FUNCTIONFS_ENDPOINT_DESC ioctl command.

Change-Id: I9416295c07c2d98f9d32df43d7e506f975da15a2
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-01-30 18:15:37 -08:00
Mayank Rana
e501d1acc0 usb: gadget: Update functions for SSP descriptors
This change updates USB function drivers to assign SSP descriptors
using usb_assign_descriptors() API. USB SSP descriptors are needed
to enumerate these functions as different composite device in
super speed plus mode.

Change-Id: Iea4d623afb2bf572358d1cc1d0673f20f2d7d5aa
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-01-30 18:15:37 -08:00
David Collins
acbb167a16 defconfig: lahaina: remove disablement of SPMI temp alarm driver
CONFIG_QCOM_SPMI_TEMP_ALARM is incorrectly disabled in
lahaina_QGKI.config and lahaina_debug.config.  Remove this
disablement so that the SPMI temp alarm driver is compiled
in both GKI and QGKI builds.

Change-Id: I2f54dae62dabe50758974c70f39f713141d16d8f
Signed-off-by: David Collins <collinsd@codeaurora.org>
2020-01-30 16:38:46 -08:00
qctecmdr
23d132223b Merge "defconfig: lahaina-gki: enable various USB CONFIGFS functions" 2020-01-30 16:12:58 -08:00
qctecmdr
fb6e032b48 Merge "smp: Wake up all idle CPUs when suspending to idle" 2020-01-30 16:12:58 -08:00
qctecmdr
871c6683e3 Merge "msm: gsi: Fix the WARNING for gsi_write_channel_scratch" 2020-01-30 16:12:58 -08:00
Vivek Aknurwar
a267c2a3de dt-bindings: clock: Add support for HLOS1_VOTE_SMMU_CLK
The SMMU consumer requires to enable/disable the
GPU_CC_HLOS1_VOTE_SMMU_CLK, add support for same.

Change-Id: I1ef969bba510ea5354c213c99390a3754f0a0766
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
2020-01-30 15:47:09 -08:00
Satya Durga Srinivasu Prabhala
61d1f2eb9b hrtimer: fix issue during core isolation
During core isolation, while migrating hrtimers to one of online CPUs,
below issue is being observed due to commit 5da7016046
("hrtimer: Implement support for softirq based hrtimers") which started
to enable local irqs. Fix it by moving local_bh_disable/enable calls to
hotplug path only.

[   73.488582] WARNING: CPU: 0 PID: 7 at kernel/softirq.c:106 \
					__local_bh_disable_ip+0xc4/0xd0
[   73.506182] WARNING: CPU: 0 PID: 7 at kernel/softirq.c:160 \
					__local_bh_enable_ip+0xd0/0x140
[   73.523834] kernel BUG at kernel/irq_work.c:138!
[   73.531979] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[   73.567732] pstate: 60400005 (nZCv daif +PAN -UAO)
[   73.572663] pc : irq_work_run+0x160/0x170
[   73.576795] lr : flush_smp_call_function_queue+0x178/0x1b0
[   73.674966] Call trace:
[   73.677494]  irq_work_run+0x160/0x170
[   73.681271]  flush_smp_call_function_queue+0x178/0x1b0
[   73.686558]  generic_smp_call_function_single_interrupt+0x14/0x20
[   73.692832]  handle_IPI+0x188/0x2f8
[   73.696426]  gic_handle_irq+0x110/0x1d8
[   73.700374]  el1_irq+0xb4/0x130

Change-Id: I969171022377dc793834c4c4343e5f839f224dbe
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-01-30 12:48:18 -08:00
Gaurav Kashyap
0bde03e734 scsi: ufs: Make crypto updates on QTI ufs
Make v6 updates on ufshcd-qti.c to match the updates
in ufshcd.c. Also compile UFS crypto when using
ufshcd-qti.

Change-Id: I1799b9b7f0aeee2cb76599403ae8461457a3fcd2
Signed-off-by: Gaurav Kashyap <gaurkash@codeaurora.org>
2020-01-30 11:05:32 -08:00
qctecmdr
addcafbc89 Merge "defconfig: enable schedutil governor on Lahaina" 2020-01-29 20:50:45 -08:00
qctecmdr
5898582bda Merge "net: qrtr: Introduce MHI transport for qrtr" 2020-01-29 20:50:45 -08:00
qctecmdr
e9130c5963 Merge "regulator: rpmh-regulator: support parent supply specification in subnodes" 2020-01-29 20:50:45 -08:00
qctecmdr
7d0324ab17 Merge "msm: cvp: Use compiler data type in uapi" 2020-01-29 20:50:44 -08:00
Hemant Kumar
1a54523a96 arm64: defconfig: Enable MSM PCIe and MHI Host driver for lahaina
Add configuration changes in lahaina to support MSM PCIe and MHI
HOST driver.

Change-Id: If6fbbaf3f8efb04566dba2a61a6c4f79dd391515
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2020-01-29 18:13:00 -08:00
Tony Truong
86c9bd5df0 msm: pcie: configure PCIe and MSI as modules in Makefile
This allows to compile PCIe MSM driver as one module. As part
of that remove Kconfig option PCI_MSM_MSI.

Change-Id: I225b880a01cfc7b480486d7d7db9fabe86256f52
Signed-off-by: Tony Truong <truong@codeaurora.org>
2020-01-29 18:11:26 -08:00
Mayank Rana
0ed723e6bb dwc3-msm: Add dwc3_msm_release_ss_lane() API
DP driver needs to use both USB SS lane in some use case. Hence
to release USB SS lane, add dwc3_msm_release_ss_lane() API which
performs below operations:
i. Stop USB host mode
ii. Start USB host mode into high speed mode if USB host mode
was active.

dwc3_msm_release_ss_lane() API is blocking call, and will comeback
once above both operations are performed.

Change-Id: I56df606914a613bfe4b76298b0041a66fc74878d
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-01-29 15:43:43 -08:00
George Shen
6c20003309 msm: cvp: Support releasing persistent buffer
CVP firmware introduced new feature to support releasing user
allocated persistent buffers. Added support in kernel.

Change-Id: Ifcd35c328ebfbb961247bf45e2e72222bd3e425b
Signed-off-by: George Shen <sqiao@codeaurora.org>
2020-01-29 15:33:09 -08:00
qctecmdr
5e7a256761 Merge "clk: qcom: clk-rpmh: Mark rfclka2 as optional for Lahaina" 2020-01-29 15:32:56 -08:00
qctecmdr
41c90d480a Merge "psi: Use deferrable psi_avgs_work" 2020-01-29 15:32:56 -08:00
Harshdeep Dhatt
2951173569 msm: kgsl: Move secvid programming to gpudev
Since eCP will need these register writes as well, instead
of exporting a function set_secvid, move these register writes
to respective target specific functions which are common to
both eCP enabled and disabled configurations. This also helps
get rid of the register offset definitions.

Change-Id: I2faa996901c746e7277dc2fdc272b9eb76e13e9c
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:58 -08:00
Harshdeep Dhatt
cfcdc95690 msm: kgsl: Do dispatcher init at first open
With eCP, we will no longer be using the dispatcher. And
we will have different first open functions depending on
whether eCP is enabled or disabled. Hence, move dispatcher
init to first open so that dispatcher is initialized only when
eCP is not enabled.

Change-Id: Ia65807dcfed65a4b810b886f71beb4c5ba30abb1
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:56 -08:00
Harshdeep Dhatt
1affb278e4 msm: kgsl: Move APRIV config to a6xx start
We need APRIV enabled for eCP as well. But eCP doesn't
call into a6xx_rb_start. Move it to a more generic function
which is called by eCP as well.

Change-Id: I3014bee48145ab5b7c54f01854fe520d9a6db0a6
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:55 -08:00
Harshdeep Dhatt
e13919782c msm: kgsl: Move preemption start to ringbuffer start
We should not be doing anything specific to preemption like
accessing preemption buffers in a6xx_start as a6xx_start is
called for both eCP and non eCP paths.

Change-Id: Ia7f9e7a54bcbbb6365ddd1f621e1c582faabd962
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:53 -08:00
Harshdeep Dhatt
840f7b8ab9 msm: kgsl: Move ringbuffer global allocations to init time
With eCP, kgsl will not be allocating these buffers or anything
related to the ringbuffers. Move this to init time so that this
only gets called when eCP is disabled.

Change-Id: I3c492581d904e35e4a58931bdd1f6e83546a3d2c
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:51 -08:00
Harshdeep Dhatt
90c1659e71 msm: kgsl: Fix memory leak in a6xx_init
Make sure the power up register list is allocated only
once and not every time a6xx_init gets called.

Change-Id: Ifc46c6307886d3911788001c05640c0029706fc4
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:50 -08:00
Harshdeep Dhatt
ef64d261f0 msm: kgsl: Create first_open and last_close
As the name suggests, the first_open is called when the device
is opened for the first time. And last_close is called when last
device instance is closed. This helps with differentiating eCP
and non eCP open within adreno namespace.

Change-Id: Idfbb487313d8be4de9d9785dbcdfb479dbab969e
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:48 -08:00
Harshdeep Dhatt
8afc60d2e8 msm: kgsl: Add function to get context bank number
Add a function to find the context bank a pagetable is attached
to.

Change-Id: I967c77e9d2f761440f28973485a8ce02c7d27dce
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:28 -08:00
Jack Pham
2c605b45cc usb: dwc3-msm: Fix out-of-bounds access in bus voting
The for loop in dwc3_msm_update_bus_bw() was using a NULL
condition rather than against ARRAY_SIZE(mdwc->icc_paths).
This can result in an out-of-bounds access if the memory
just beyond the array also happens to be non-zero.

Change-Id: Ib1f003f774b125a156ceb0070cd9d98a4d1f03ee
Signed-off-by: Jack Pham <jackp@codeaurora.org>
2020-01-28 20:19:08 -08:00
qctecmdr
e1007d065f Merge "sched/fair: consider uclamp boost while deciding the start_cpu" 2020-01-28 08:04:51 -08:00
qctecmdr
b325307ce5 Merge "regulator: qcom_pm8008: correct parent supply voltage voting" 2020-01-28 08:04:50 -08:00
qctecmdr
b1f377f8e9 Merge "iommu/arm-smmu: log outstanding transactions on sync timeout" 2020-01-28 08:04:50 -08:00
qctecmdr
154900b51b Merge "regulator: qcom_pm8008-regulator: correct chip-en chip variable type" 2020-01-28 02:41:33 -08:00