Commit graph

877,212 commits

Author SHA1 Message Date
qctecmdr
e791172b7e Merge "arm64: defconfig: Enable QRTR MHI on lahaina_debug" 2020-01-31 10:27:18 -08:00
qctecmdr
f542d726be Merge "scsi: ufs: Make crypto updates on QTI ufs" 2020-01-31 10:27:17 -08:00
qctecmdr
d806fa1378 Merge "tracing: rework sched_preempt_disable trace point implementation" 2020-01-31 10:27:17 -08:00
qctecmdr
0326bf0e0f Merge "msm: kgsl: Move APRIV config to a6xx start" 2020-01-31 04:38:34 -08:00
qctecmdr
be8d5fe010 Merge "cpuidle: lpm-levels: update lpm_disallowed() with sched hints" 2020-01-30 23:05:04 -08:00
qctecmdr
44eb78d31e Merge "msm: cvp: Support releasing persistent buffer" 2020-01-30 23:05:03 -08:00
qctecmdr
88353cd04a Merge "arm64: defconfig: Enable MSM PCIe and MHI Host driver for lahaina" 2020-01-30 23:05:03 -08:00
qctecmdr
b74745b4f0 Merge "dwc3-msm: Add dwc3_msm_release_ss_lane() API" 2020-01-30 23:05:03 -08:00
qctecmdr
23d132223b Merge "defconfig: lahaina-gki: enable various USB CONFIGFS functions" 2020-01-30 16:12:58 -08:00
qctecmdr
fb6e032b48 Merge "smp: Wake up all idle CPUs when suspending to idle" 2020-01-30 16:12:58 -08:00
qctecmdr
871c6683e3 Merge "msm: gsi: Fix the WARNING for gsi_write_channel_scratch" 2020-01-30 16:12:58 -08:00
Gaurav Kashyap
0bde03e734 scsi: ufs: Make crypto updates on QTI ufs
Make v6 updates on ufshcd-qti.c to match the updates
in ufshcd.c. Also compile UFS crypto when using
ufshcd-qti.

Change-Id: I1799b9b7f0aeee2cb76599403ae8461457a3fcd2
Signed-off-by: Gaurav Kashyap <gaurkash@codeaurora.org>
2020-01-30 11:05:32 -08:00
qctecmdr
addcafbc89 Merge "defconfig: enable schedutil governor on Lahaina" 2020-01-29 20:50:45 -08:00
qctecmdr
5898582bda Merge "net: qrtr: Introduce MHI transport for qrtr" 2020-01-29 20:50:45 -08:00
qctecmdr
e9130c5963 Merge "regulator: rpmh-regulator: support parent supply specification in subnodes" 2020-01-29 20:50:45 -08:00
qctecmdr
7d0324ab17 Merge "msm: cvp: Use compiler data type in uapi" 2020-01-29 20:50:44 -08:00
Hemant Kumar
1a54523a96 arm64: defconfig: Enable MSM PCIe and MHI Host driver for lahaina
Add configuration changes in lahaina to support MSM PCIe and MHI
HOST driver.

Change-Id: If6fbbaf3f8efb04566dba2a61a6c4f79dd391515
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2020-01-29 18:13:00 -08:00
Tony Truong
86c9bd5df0 msm: pcie: configure PCIe and MSI as modules in Makefile
This allows to compile PCIe MSM driver as one module. As part
of that remove Kconfig option PCI_MSM_MSI.

Change-Id: I225b880a01cfc7b480486d7d7db9fabe86256f52
Signed-off-by: Tony Truong <truong@codeaurora.org>
2020-01-29 18:11:26 -08:00
Mayank Rana
0ed723e6bb dwc3-msm: Add dwc3_msm_release_ss_lane() API
DP driver needs to use both USB SS lane in some use case. Hence
to release USB SS lane, add dwc3_msm_release_ss_lane() API which
performs below operations:
i. Stop USB host mode
ii. Start USB host mode into high speed mode if USB host mode
was active.

dwc3_msm_release_ss_lane() API is blocking call, and will comeback
once above both operations are performed.

Change-Id: I56df606914a613bfe4b76298b0041a66fc74878d
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-01-29 15:43:43 -08:00
George Shen
6c20003309 msm: cvp: Support releasing persistent buffer
CVP firmware introduced new feature to support releasing user
allocated persistent buffers. Added support in kernel.

Change-Id: Ifcd35c328ebfbb961247bf45e2e72222bd3e425b
Signed-off-by: George Shen <sqiao@codeaurora.org>
2020-01-29 15:33:09 -08:00
qctecmdr
5e7a256761 Merge "clk: qcom: clk-rpmh: Mark rfclka2 as optional for Lahaina" 2020-01-29 15:32:56 -08:00
qctecmdr
41c90d480a Merge "psi: Use deferrable psi_avgs_work" 2020-01-29 15:32:56 -08:00
Harshdeep Dhatt
1affb278e4 msm: kgsl: Move APRIV config to a6xx start
We need APRIV enabled for eCP as well. But eCP doesn't
call into a6xx_rb_start. Move it to a more generic function
which is called by eCP as well.

Change-Id: I3014bee48145ab5b7c54f01854fe520d9a6db0a6
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:55 -08:00
Harshdeep Dhatt
e13919782c msm: kgsl: Move preemption start to ringbuffer start
We should not be doing anything specific to preemption like
accessing preemption buffers in a6xx_start as a6xx_start is
called for both eCP and non eCP paths.

Change-Id: Ia7f9e7a54bcbbb6365ddd1f621e1c582faabd962
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:53 -08:00
Harshdeep Dhatt
840f7b8ab9 msm: kgsl: Move ringbuffer global allocations to init time
With eCP, kgsl will not be allocating these buffers or anything
related to the ringbuffers. Move this to init time so that this
only gets called when eCP is disabled.

Change-Id: I3c492581d904e35e4a58931bdd1f6e83546a3d2c
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:51 -08:00
Harshdeep Dhatt
90c1659e71 msm: kgsl: Fix memory leak in a6xx_init
Make sure the power up register list is allocated only
once and not every time a6xx_init gets called.

Change-Id: Ifc46c6307886d3911788001c05640c0029706fc4
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:50 -08:00
Harshdeep Dhatt
ef64d261f0 msm: kgsl: Create first_open and last_close
As the name suggests, the first_open is called when the device
is opened for the first time. And last_close is called when last
device instance is closed. This helps with differentiating eCP
and non eCP open within adreno namespace.

Change-Id: Idfbb487313d8be4de9d9785dbcdfb479dbab969e
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:48 -08:00
Harshdeep Dhatt
8afc60d2e8 msm: kgsl: Add function to get context bank number
Add a function to find the context bank a pagetable is attached
to.

Change-Id: I967c77e9d2f761440f28973485a8ce02c7d27dce
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2020-01-29 14:17:28 -08:00
qctecmdr
e1007d065f Merge "sched/fair: consider uclamp boost while deciding the start_cpu" 2020-01-28 08:04:51 -08:00
qctecmdr
b325307ce5 Merge "regulator: qcom_pm8008: correct parent supply voltage voting" 2020-01-28 08:04:50 -08:00
qctecmdr
b1f377f8e9 Merge "iommu/arm-smmu: log outstanding transactions on sync timeout" 2020-01-28 08:04:50 -08:00
qctecmdr
154900b51b Merge "regulator: qcom_pm8008-regulator: correct chip-en chip variable type" 2020-01-28 02:41:33 -08:00
qctecmdr
9d88952dd4 Merge "regulator: refgen: add support for proxy consumers" 2020-01-28 02:41:33 -08:00
qctecmdr
5f6b078629 Merge "msm: pcie: update PCIe RC and MSI driver to compile as GKI modules" 2020-01-28 02:41:31 -08:00
qctecmdr
b7906ffb6d Merge "dwc3: gadget: Fix dr_mode check with USB device mode APIs" 2020-01-27 20:21:00 -08:00
qctecmdr
d0e6ace9d5 Merge "interconnect: qcom: Add QoS config support" 2020-01-27 20:21:00 -08:00
qctecmdr
d129a56a31 Merge "PM / devfreq: Make governor registration less verbose" 2020-01-27 20:20:59 -08:00
qctecmdr
468d86d1fd Merge "wil6210: fix vendor command policy for vendor unspec commands" 2020-01-27 20:20:59 -08:00
qctecmdr
bfab88fcd6 Merge "arm64: defconfig: Enable CMA performance optimizations on Lahaina" 2020-01-27 20:20:59 -08:00
Mike Tipton
f9fea2da9a clk: qcom: clk-rpmh: Mark rfclka2 as optional for Lahaina
Mark rfclka2 as an optional clock for Lahaina. This clock is currently
unused on our internal development boards and thus isn't populated in
cmd_db. It could be used on future boards, so don't remove it entirely.

Change-Id: I0f216e14e675196d4817c89db730d40f1e20aba1
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
2020-01-27 15:33:56 -08:00
Pavankumar Kondeti
9db84311e7 tracing: rework sched_preempt_disable trace point implementation
The current implementation of sched_preempt_disable trace point
fails to detect the preemption disable time inside spin_lock_bh()
and spin_unlock_bh(). This is because __local_bh_disable_ip() calls
directly __preempt_count_add() which skips the preemption disable
tracking. Instead of relying on the updates to preempt count, it
is better to write the preemption disable tracking directly to
preemptsoff tracer. This is similar to how irq disable tracking
is done.

The current code handles the false positives coming from __schedule()
by directly resetting the time stamp. This requires an interface
from the scheduler to preemptsoff tracer. To avoid this additional
interface, the current patch detects the same condition by comparing
the task pid and context switch count. If they are not matching
at the time of preemption disable to enable, don't track the preemption
disable time as it involved a context switch.

Due to this rework. the sched_preempt_disable trace point location is
changed to

/sys/kernel/debug/tracing/events/preemptirq/sched_preempt_disable/enable

Change-Id: I7f58d316b7c54bc7a54102bfeb678404bda010d4
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: port to 5.4 and resolve trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-01-27 15:30:25 -08:00
Lingutla Chandrasekhar
617f2e7fe2 sched: core: reset preemption/irqsoff disable timestamp
Preempt/irqsoff tracer notes down preemption/irqs disabled timestamp
and compares it with enable timestamp to report prolonged disabling
callers at latency tracking. But they don't reset the time stamp at
re-enable time. The time stamp could be stale and possible to report
same latency multiple times or false positive. This could be possible
when callsites uses notrace API (__preempt_) for preemption disable
and tracable API (preempt_) for enable (ex: softirq).

Fix it by resetting the preempt/irqsoff disable timestamp at
re-enable time.

Change-Id: I6790227998881922a9339869ce9ee2dab6202567
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
2020-01-27 15:30:22 -08:00
Shaleen Agrawal
ac4fd2f97f defconfig: enable schedutil governor on Lahaina
Enable schedutil governor as part of lahaina port.

Change-Id: I8b04c587fb217fe0333593c95b4e9afc4af83427
Signed-off-by: Shaleen Agrawal <shalagra@codeaurora.org>
2020-01-27 13:59:47 -08:00
qctecmdr
1bf7671f03 Merge "defconfig: lahaina-gki: enable the qcom_pm8008-regulator driver" 2020-01-27 13:53:31 -08:00
qctecmdr
57241317ab Merge "defconfig: lahaina: enable the battery charger driver" 2020-01-27 13:53:30 -08:00
qctecmdr
9f3b06dc62 Merge "arm64: defconfig: Enable SG support in Lahaina GKI" 2020-01-27 13:53:29 -08:00
qctecmdr
3ee13ad157 Merge "usb: gadget: f_cdev: Fix func_suspend" 2020-01-27 13:41:00 -08:00
qctecmdr
6b47c82f48 Merge "mhi: Export more symbols" 2020-01-27 13:41:00 -08:00
qctecmdr
786200ca58 Merge "arm64: defconfig: Enable CFI_PERMISSIVE flag" 2020-01-27 13:41:00 -08:00
Ruofei Ma
fc665a4e64 msm: cvp: Use compiler data type in uapi
Move to use compiler data type instead of C keyword in
uapi.

Change-Id: I814863cbd1969654fd6c4203d863679874cc7892
Signed-off-by: Ruofei Ma <ruofeim@codeaurora.org>
2020-01-27 13:00:11 -08:00