* pci/host-designware:
PCI: designware: Fold struct pcie_port_info into struct pcie_port
* pci/host-imx6:
PCI: imx6: Delay enabling reference clock for SS until it stabilizes
* pci/host-keystone:
PCI: keystone: Set device ID based on SoC to support multiple ports
PCI: keystone: Assume controller is already in RC mode
PCI: keystone: Limit MRSS for all downstream devices
* pci/host-tegra:
PCI: tegra: Add Tegra124 support
PCI: tegra: Make sure the PCIe PLL is really reset
PCI: tegra: Fix extended configuration space mapping
PCI: tegra: Clear CLKREQ# enable on port disable
* pci/host-xilinx:
PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
* pci/enumeration:
PCI: Enable CRS Software Visibility for root port if it is supported
PCI: Check only the Vendor ID to identify Configuration Request Retry
* pci/misc:
PCI: Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters
PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size
PCI/AER: Make <linux/aer.h> standalone includable
* pci/virtualization:
PCI: Use device flag helper functions
xen/pciback: Use PCI device flag helper functions
KVM: Use PCI device flag helper functions
PCI: Add device flag helper functions
PCI: Assume all Mellanox devices have broken INTx masking
We should be testing "hwirq" instead of "irq". "irq" is unsigned so it's
never less than zero. Also it's uninitialized.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Srikanth Thokala <sthokal@xilinx.com>
Add parentheses around parameters in PCI_DEVID and PCI_VPD_LRDT_ID macros
to prevent possible expansion errors as described by the CERT Secure Coding
Standard: PRE01-C: Use parentheses within macros around parameter names
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Megan Kamiya <megan.a.kamiya@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The PCIe controller on Tegra124 has two root ports that can be used in a
x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to
5 GT/s). The PHY programming has been moved into a separate controller, so
the driver now needs to request an external PHY referenced using the device
tree.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Depending on the prior state of the controller, the PLL reset may not be
pulsed. Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space. This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
When a root port is disabled, disable the CLKREQ# signal if available.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The Crocodile chip occasionally comes up with 4k and 8k BAR sizes. Due to
an erratum, setting the SR-IOV page size causes the physical function BARs
to expand to the system page size. Since ppc64 uses 64k pages, when Linux
tries to assign the smaller resource sizes to the now 64k BARs the address
will be truncated and the BARs will overlap.
Force Linux to allocate the resource as a full page, which avoids the
overlap.
[bhelgaas: print expanded resource, too]
Signed-off-by: Douglas Lehr <dllehr@us.ibm.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Milton Miller <miltonm@us.ibm.com>
CC: stable@vger.kernel.org
The header file references u16 and u32 types, but they are not defined in
the header nor does the header pull in the necessary includes for them.
This causes build breakage when the file is included without any of the
dependencies being satisfied from somewhere else.
Fix this by including linux/types.h (for u16 and u32).
[bhelgaas: removed pci_dev declaration (already added by 5ccb8225ab)]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Use PCI device flag helper functions when checking whether a device is
assigned. No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Use PCI device flag helper functions when assigning or releasing device.
No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Acked-by: David Vrabel <david.vrabel@citrix.com>
Use PCI device flag helper functions when assigning or releasing device.
No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
K2E SoC has two PCI ports. The SATA controller is connected to second PCI
port (port 1). To support multiple port handling in Keystone PCI driver,
read the PCI device ID dynamically by iomap/read/unmap during probe and
save it in driver's private data and update it in host init code. The PCI
device ID field in the RC's config space is not filled by default by the
hardware and has to be updated by the PCI driver by reading the same from
the SoC register indicated by reg index #2 in DT bindings.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Keystone PCI hardware supports both RC and EP modes and devcfg register has
bits to boot strap the device to either of these modes. It seems proper to
add this functionality to the boot loader rather than in the driver as
device will be operating in either mode, not both any time. Currently the
driver supports only RC mode and hence register configuration in the driver
is not needed and the driver can assume the hardware is in RC mode.
Also update the DT documentation accordingly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Keystone PCIe controller has a limitation that memory read request size
must not exceed 256 bytes. This is a hardware limitation. Add a quirk to
force this limit on all downstream devices by updating MRRS.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Per PCIe r3.0, sec 2.3.2, an endpoint may respond to a Configuration
Request with a Completion with Configuration Request Retry Status (CRS).
This terminates the Configuration Request.
When the CRS Software Visibility feature is disabled (as it is by default),
a Root Complex must handle a CRS Completion by re-issuing the Configuration
Request. This is invisible to software. From the CPU's point of view, an
endpoint that always responds with CRS causes a hang because the Root
Complex never supplies data to complete the CPU read.
When CRS Software Visibility is enabled, a Root Complex that receives a CRS
Completion for a read of the Vendor ID must return data of 0x0001. The
Vendor ID of 0x0001 indicates to software that the endpoint is not ready.
We now have more devices that require CRS Software Visibility. For
example, a PLX 8713 NT bridge may respond with CRS until it has been
configured via I2C, and the I2C configuration is completely independent of
PCI enumeration.
Enable CRS Software Visibility if it is supported. This allows a system
with such a device to work (though the PCI core times out waiting for it to
become ready, and we have to rescan the bus after it is ready).
This essentially reverts ad7edfe049 ("[PCI] Do not enable CRS Software
Visibility by default"). The failures that led to ad7edfe049 should be
addressed by 89665a6a71 ("PCI: Check only the Vendor ID to identify
Configuration Request Retry").
[bhelgaas: changelog]
Link: http://lkml.kernel.org/r/20071029061532.5d10dfc6@snowcone
Link: http://lkml.kernel.org/r/alpine.LFD.0.9999.0712271023090.21557@woody.linux-foundation.org
Signed-off-by: Rajat Jain <rajatxjain@gmail.com>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Per PCIe r3.0, sec 2.3.2, if a Root Complex
- has Configuration Request Retry Status Software Visibility enabled,
- issues a Configuration Read of both bytes of the Vendor ID, and
- receives a Completion with Configuration Request Retry Status (CRS),
it must complete the request to the host by fabricating data of 0x0001 for
the Vendor ID and 0xff for any additional bytes in the request.
Linux issues a single config read for the four bytes containing the Vendor
ID and the Device ID. Previously we checked all four bytes for 0xffff0001
to identify CRS.
However, it is only the Vendor ID that really indicates CRS, because it's
sufficient to read only those two bytes. Checking the Device ID verifies
spec compliance but doesn't add any information.
Some Root Complexes appear to indicate CRS by returning 0x0001 for the
Vendor ID along with the actual the Device ID. Previously we interpreted
that as a valid Vendor/Device ID pair, although 0x0001 is reserved and
cannot be a valid Vendor ID.
[bhelgaas: changelog]
Link: http://lkml.kernel.org/r/4729FC36.3040000@gmail.com
Signed-off-by: Rajat Jain <rajatxjain@gmail.com>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The VFIO driver routes LSI interrupts by capturing, masking, and then
delivering. When passing though Mellanox adapters from host to guest,
interrupt storm are reported from host and guest. That's because the PCI
command register INTx Disable bit doesn't work on Mellanox devices.
# lspci | grep Mellanox
0001:05:00.0 Ethernet controller: Mellanox Technologies MT27500 Family [ConnectX-3]
0005:01:00.0 Ethernet controller: Mellanox Technologies MT26448 [ConnectX EN 10GigE, PCIe 2.0 5GT/s] (rev b0)
Amir Vadai confirmed that all Mellanox devices have same problem.
The patch marks broken INTx masking for all Mellanox adapters.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Amir Vadai <amirv@mellanox.com>
The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port. So, keeping a separate
structure does not seem very logical. Therefore remove this struct and
embed its elements directly into struct pcie_port.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.
Delay enabling the reference clock for the SS function until it has
stabilized. This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.
[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
* pci/misc:
PCI/AER: Make <linux/aer.h> standalone includable
PCI: Remove unnecessary variable in pci_add_dynid()
* pci/pm:
PCI/PM: Allow PCI devices to be put into D3cold during system suspend
PCI/PM: Drop unused runtime PM support code for PCIe ports
* pci/host-designware:
PCI: designware: Check private_data validity in single place
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: designware: Add support for v3.65 hardware
* pci/host-imx6:
PCI: imx6: Probe in module_init(), not fs_initcall()
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: imx6: Put LTSSM in "Detect" state before disabling it
MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
PCI: designware: Add support for v3.65 hardware
* pci/host-keystone:
PCI: keystone: Add TI Keystone PCIe driver
PCI: designware: Add support for v3.65 hardware
* pci/host-tegra:
PCI: tegra: Implement a proper resource hierarchy
PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
resources: Add device-managed request/release_resource()
* pci/host-xilinx:
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
Conflicts:
drivers/pci/host/Kconfig
drivers/pci/host/Makefile
The driver had checks for this sprinkled all over. As we call
sys_to_pcie() before every instance of this check, we can move the
check to this single location to make things clear.
Removing the statements after BUG[_ON]() is safe as the kernel is halted at
this point anyway.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
This effectively reverts f216f57ffe ("PCI: imx6: Probe the PCIe in
fs_initcall()") as the resource allocation issue that prevented the driver
from working properly at module_initcall level is now fixed in
pcie-designware.c.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
* pci/host-designware:
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: designware: Add support for v3.65 hardware
The header file references u16 and u32 types, but they are not defined in
the header nor does the header pull in the necessary includes for them.
This causes build breakage when the file is included without any of the
dependencies being satisfied from somewhere else.
Fix this by including linux/types.h (for u16 and u32).
[bhelgaas: removed pci_dev declaration (already added by 5ccb8225ab)]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Use pci_create_root_bus() similar to other PCI host controller drivers.
The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus. This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.
To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered. Switching to pci_create_root_bus() allows us to get rid of
this special handling.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The Keystone PCIe controller is based on v3.65 version of the Designware
h/w. Main differences are:
1. No ATU support
2. Legacy and MSI IRQ functions are implemented in application register
space
3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.
All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver. Also add necessary DT documentation and
update the MAINTAINERS file for the driver.
[bhelgaas: spelling and whitespace fixes]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
Currently the resource hierarchy generated from the PCIe host bridge is
completely flat:
$ cat /proc/iomem
00000000-00000fff : /pcie-controller@00003000/pci@1,0
00003000-000037ff : pads
00003800-000039ff : afi
10000000-1fffffff : cs
28000000-28003fff : r8169
28004000-28004fff : r8169
...
The host bridge driver doesn't request all the resources that are used.
Windows allocated to each of the root ports aren't tracked, so there is no
way for resources allocated to individual devices to be matched up with the
correct parent resource by the PCI core.
This patch addresses this in two steps. It first takes the union of all
regions associated with the PCIe host bridge (control registers, root port
registers, configuration space, I/O and prefetchable as well as non-
prefetchable memory regions) and uses it as the new root of the resource
hierarchy.
Subsequently, regions are allocated from within this new root resource so
that the resource tree looks much more like what's expected:
# cat /proc/iomem
00000000-3fffffff : /pcie-controller@00003000
00000000-00000fff : /pcie-controller@00003000/pci@1,0
00003000-000037ff : pads
00003800-000039ff : afi
10000000-1fffffff : cs
20000000-27ffffff : non-prefetchable
28000000-3fffffff : prefetchable
28000000-280fffff : PCI Bus 0000:01
28000000-28003fff : 0000:01:00.0
28000000-28003fff : r8169
28004000-28004fff : 0000:01:00.0
28004000-28004fff : r8169
...
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
We should call tegra_msi_free() to free the MSI bit if irq_create_mapping()
fails. And we need to dispose the IRQ mapping during IRQ teardown.
[bhelgaas: made irqd_to_hwirq() change suggested by Thierry]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Provide device-managed implementations of the request_resource() and
release_resource() functions. Upon failure to request a resource, the new
devm_request_resource() function will output an error message for
consistent error reporting.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tejun Heo <tj@kernel.org>
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use. The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.
According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do. Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.
As a workaround, force LTSSM into detect state right before hitting the
disable switch. There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.
[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Also drop Shawn Guo per his request.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Richard Zhu <r65037@freescale.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The variable "retval" in pci_add_dynid() is only used to store the return
value of driver_attach() and is then directly returned. Remove the
variable and directly pass on driver_attach()'s return value.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.
1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.
2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.
3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
Commit 448bd857d4 ("PCI/PM: add PCIe runtime D3cold support") added a
check to prevent PCI devices from being put into D3cold during system
suspend without giving any particular reason.
Also the check isn't really necessary, because acpi_pci_set_power_state()
maps PCI_D3hot to ACPI_STATE_D3_COLD anyway.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Since commit de7d5f729c ("PCI/PM: Disable runtime PM of PCIe ports") the
runtime PM support code for PCIe ports in portdrv_pci.c has never been
used, so drop it entirely.
If we are to support runtime PM of PCIe ports, it will have to be done in a
different way most likely anyway.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Highlights:
- More fixes for read/write codepath regressions
- Sleeping while holding the inode lock
- Stricter enforcement of page contiguity when coalescing requests
- Fix up error handling in the page coalescing code
- Don't busy wait on SIGKILL in the file locking code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT+0LpAAoJEGcL54qWCgDyWfsP/imrpge47aZywi95chV8vgjM
O85ITZbupTFwXbB7kE63CrcaxRGhFrSStk4UDhDCDkHfFb1ksjZaPR1mnkwvkR2p
4+JUoq0fkPfeX21+rqKCYmnhstpne/N8K8FJBsEs3/TqiCBWxWOelLXdyWun4H5B
9JBYQ7FYitUazeSiSiDXcl7Di/E09cFPi0H5VPKRyuNdYxySabnsBOELBE/28iXr
egW1I9UKQR2EtBrvgazBbWE5XmB9XAm4X3sD1l0QD65mfSNkbnNhPFSiCdT7f/d6
9uxECR0Y4wNYgYAfVLBew5/MXJajcv03BFMKmTUeGj9fOQzycpBT4Dx2KxEWqfnt
Xk2nNbISxBnO0koMflmo+LPv2lv+Br3kQ+eZCHHKknvBrX2a6bJdTCZkwACVtND9
LdbAveFQpdaeLrm/28TnRoE927r+VeAVM19yOSG8sNAskFFg4Yy51tR0e1GivkJT
+qmmTRx+l78HjHvoPXOYdNgBC954r6APH5ST7su/7WxNClM36fEK6XxA9xbDLJWm
wUzlGKvpwEeBJJhgjbQLwuU8BiksjFz/CaiObNvPOpc/d2GoKIhnTg19kNhg2R//
UCDa2d5fep4z0Bo9p0s1KZm9pSBkkLjvRp9dm8WEIxLcdaF1jBK3dJECepm6ccvw
dmEmEfjbMudVdt/ZhapJ
=2wRt
-----END PGP SIGNATURE-----
Merge tag 'nfs-for-3.17-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
Pull NFS client fixes from Trond Myklebust:
"Highlights:
- more fixes for read/write codepath regressions
* sleeping while holding the inode lock
* stricter enforcement of page contiguity when coalescing requests
* fix up error handling in the page coalescing code
- don't busy wait on SIGKILL in the file locking code"
* tag 'nfs-for-3.17-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs:
nfs: Don't busy-wait on SIGKILL in __nfs_iocounter_wait
nfs: can_coalesce_requests must enforce contiguity
nfs: disallow duplicate pages in pgio page vectors
nfs: don't sleep with inode lock in lock_and_join_requests
nfs: fix error handling in lock_and_join_requests
nfs: use blocking page_group_lock in add_request
nfs: fix nonblocking calls to nfs_page_group_lock
nfs: change nfs_page_group_lock argument
* Confine SH_INTC to platforms that need it
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT+oswAAoJENfPZGlqN0++/A8QAK2yp96zl7gABtddgkunNJiV
xWCm4wcP+7dIrLpwizxtt/6HMPj9ZJHYtcxRRKVlzquwcukeVCIkfZ3Qvn2JilWM
+b4rVRGzQ+z0M7SCpNGjtgFc1IFrVrzuxZpPwgseQ5I6HQsZJKUi3qn5rRJSEax2
w+ANis2eZfmSBdu3Qsx2QBDXvS7ZPlLpimoAE+rjr60dZnljcrvBrVHQvSgpEHxn
4rXPbYrrkIee32J4lxLRDPtn5fvAsrr+vcLXEYqyFr2292U2PAxIrjZgrRzZYNtD
L6xmhZAhdmIpC0gLDLyKQhwj/9pfGFxFErZX9jeGdPT2KTEEYPkSxb75kdTwmxP4
DEtZG9Nuu6CQCBldrMt6kpujn+XCYRl94cSyUffJ5KVhNUiqB+e+JP80Yj9HB7QU
nGUfs2hQ/azY8XEiwvnls0314thkB5gN7KHxmlaFa9Wz7cgYFwWAguHH8qrq839U
+i+7dUg7nlmVoIAvzYIIA+L7x3xX4gEwsf88x3i04DPp0A8/oDAwGrqM5QzsaZpD
ghodnKRG7foc+29RLYka5CxF/MqKzpJu675sSBCVB3uW9NZpoGSwml/NN9yUu1JD
uvU2FECcbxF5OU6RHfq8FFql0fAOVeVWsMCEXgkjpZOXynKU15VTf1K2d+qkUZ/Y
gV45Jj+yCZhYs0wbXUml
=QSyy
-----END PGP SIGNATURE-----
Merge tag 'renesas-sh-drivers-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas
Pull SH driver fix from Simon Horman:
"Confine SH_INTC to platforms that need it"
* tag 'renesas-sh-drivers-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
sh: intc: Confine SH_INTC to platforms that need it
Pull MIPS fixes from Ralf Baechle:
"Pretty much all across the field so with this we should be in
reasonable shape for the upcoming -rc2"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: OCTEON: make get_system_type() thread-safe
MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores
MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'
MIPS: EVA: Add new EVA header
MIPS: scall64-o32: Fix indirect syscall detection
MIPS: syscall: Fix AUDIT value for O32 processes on MIPS64
MIPS: Loongson: Fix COP2 usage for preemptible kernel
MIPS: NL: Fix nlm_xlp_defconfig build error
MIPS: Remove race window in page fault handling
MIPS: Malta: Improve system memory detection for '{e, }memsize' >= 2G
MIPS: Alchemy: Fix db1200 PSC clock enablement
MIPS: BCM47XX: Fix reboot problem on BCM4705/BCM4785
MIPS: Remove duplicated include from numa.c
MIPS: Add common plat_irq_dispatch declaration
MIPS: MSP71xx: remove unused plat_irq_dispatch() argument
MIPS: GIC: Remove useless parens from GICBIS().
MIPS: perf: Mark pmu interupt IRQF_NO_THREAD
separate trampolines had a design flaw with the interaction between
the function and function_graph tracers.
The main flaw was the simplification of the use of multiple tracers having
the same filter (like function and function_graph, that use the
set_ftrace_filter file to filter their code). The design assumed that the
two tracers could never run simultaneously as only one tracer can be
used at a time. The problem with this assumption was that the function
profiler could be implemented on top of the function graph tracer, and
the function profiler could run at the same time as the function tracer.
This caused the assumption to be broken and when ftrace detected this
failed assumpiton it would spit out a nasty warning and shut itself down.
Instead of using a single ftrace_ops that switches between the function
and function_graph callbacks, the two tracers can again use their own
ftrace_ops. But instead of having a complex hierarchy of ftrace_ops,
the filter fields are placed in its own structure and the ftrace_ops
can carefully use the same filter. This change took a bit to be able
to allow for this and currently only the global_ops can share the same
filter, but this new design can easily be modified to allow for any
ftrace_ops to share its filter with another ftrace_ops.
The first four patches deal with the change of allowing the ftrace_ops
to share the filter (and this needs to go to 3.16 as well).
The fifth patch fixes a bug that was also caused by the new changes
but only for archs other than x86, and only if those archs implement
a direct call to the function_graph tracer which they do not do yet
but will in the future. It does not need to go to stable, but needs
to be fixed before the other archs update their code to allow direct
calls to the function_graph trampoline.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJT+hqSAAoJEKQekfcNnQGulvcH/0O4NMXX4HH1dQlYgKEaSYxE
Nh8WdiewopF5iaeNvo+8Nzdq8D2k3KgMOqSlzJ4JVmzd7gjOBSGeKDfqFwR+IbTk
9LcaJJCI3oG3MEf6m7gZMdjKPKyxkeYHDtG7kRHo8z94eliV9pKC6fUnEWayQO3o
Kv6IBupdkF8ICAiKRae5Uo0c9wjZ9YP0bZS7fxI2hJw3h/NMFnhnhUL03URIx8e3
dqgpweYg+P3KPfp2Jz6safdJqLTPK9rqqhkZhylbDl7o78xEzRN7wCyB6Nak00xz
swRgsW6vFP7ci/YSNx+B6HCIf7NTm3WLDrrIhitNHcJUZwUMU3CRO9IJHGsTuEE=
=J5lZ
-----END PGP SIGNATURE-----
Merge tag 'trace-fixes-v3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace
Pull fix for ftrace function tracer/profiler conflict from Steven Rostedt:
"The rewrite of the ftrace code that makes it possible to allow for
separate trampolines had a design flaw with the interaction between
the function and function_graph tracers.
The main flaw was the simplification of the use of multiple tracers
having the same filter (like function and function_graph, that use the
set_ftrace_filter file to filter their code). The design assumed that
the two tracers could never run simultaneously as only one tracer can
be used at a time. The problem with this assumption was that the
function profiler could be implemented on top of the function graph
tracer, and the function profiler could run at the same time as the
function tracer. This caused the assumption to be broken and when
ftrace detected this failed assumpiton it would spit out a nasty
warning and shut itself down.
Instead of using a single ftrace_ops that switches between the
function and function_graph callbacks, the two tracers can again use
their own ftrace_ops. But instead of having a complex hierarchy of
ftrace_ops, the filter fields are placed in its own structure and the
ftrace_ops can carefully use the same filter. This change took a bit
to be able to allow for this and currently only the global_ops can
share the same filter, but this new design can easily be modified to
allow for any ftrace_ops to share its filter with another ftrace_ops.
The first four patches deal with the change of allowing the ftrace_ops
to share the filter (and this needs to go to 3.16 as well).
The fifth patch fixes a bug that was also caused by the new changes
but only for archs other than x86, and only if those archs implement a
direct call to the function_graph tracer which they do not do yet but
will in the future. It does not need to go to stable, but needs to be
fixed before the other archs update their code to allow direct calls
to the function_graph trampoline"
* tag 'trace-fixes-v3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
ftrace: Use current addr when converting to nop in __ftrace_replace_code()
ftrace: Fix function_profiler and function tracer together
ftrace: Fix up trampoline accounting with looping on hash ops
ftrace: Update all ftrace_ops for a ftrace_hash_ops update
ftrace: Allow ftrace_ops to use the hashes from other ops
Pull x86 fixes from Ingo Molnar:
"A couple of EFI fixes, plus misc fixes all around the map"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/arm64: Store Runtime Services revision
firmware: Do not use WARN_ON(!spin_is_locked())
x86_32, entry: Clean up sysenter_badsys declaration
x86/doc: Fix the 'tlb_single_page_flush_ceiling' sysconfig path
x86/mm: Fix sparse 'tlb_single_page_flush_ceiling' warning and make the variable read-mostly
x86/mm: Fix RCU splat from new TLB tracepoints
Pull perf fixes from Ingo Molnar:
"A kprobes and a perf compat ioctl fix"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf: Handle compat ioctl
kprobes: Skip kretprobe hit in NMI context to avoid deadlock
A collection of fixes from this week, it's been pretty quiet and nothing
really stands out as particularly noteworthy here -- mostly minor fixes
across the field:
- ODROID booting was fixed due to PMIC interrupts missing in DT
- A collection of i.MX fixes
- Minor Tegra fix for regulators
- Rockchip fix and addition of SoC-specific mailing list to make it
easier to find posted patches.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJT+jEaAAoJEIwa5zzehBx3gPIP/2EMvkRiFL73z6u67d6AhqCR
UPpv65Lk0FzvKZYvpNdNDdPatS48SpEh4Ppj58HegK31jaZIYhsvGHFsAwrHpZXF
2D2H8Vqy6wl+UL+BQGTHJ2rhqgg40PSZQh1KksaBrjb9MDWUbAI0V9AysoT6ecIP
/02mzRkNPL7V5ISikksa82FWbZwI36KJGTM19ZDp6CYQnV2L4eG0LefGjgEzdE07
iur1PO/TUi0ibQex3It9D+ynNlza0sZJDR0AsGFTS/96fvtX6SQzvxtEsr4jUfyT
jceqD5KIWS9N1OmRudJ+e3awpzGGuRIkdq36eiJbhSe426LHgDNbIS4RU+YRNFIf
9/bK4blcxGNnddsDTLUIyi+vykAm1ObAfGNNrKeA4z9lDw0QVuoG5VwrgNKcIk3J
kugj3RLUQ5yd9iIFJyrPxlpB5mTo5SaPCSxjuDKzftwDQtF+SJI58V//Nde0Ocfw
K7VpmY26uYUmf6AltiyFxOCUASzUC3Bp+/cf0lYTWE1+iIuOTJRlYmYwKDMrJ+c0
mtz3uCiQhTzaHje6AksA1wlKhv3KS/opGN1oNVSILgjExiRGh94MSkROLqtJ35cE
WV/nuzZUPdmZ6tGQ6b7FEa0elbEElaioDiQraOeSehKijEjfhK+tHNJczoO94s2R
Swfff4NwRe346ZMk/L/2
=+oYu
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A collection of fixes from this week, it's been pretty quiet and
nothing really stands out as particularly noteworthy here -- mostly
minor fixes across the field:
- ODROID booting was fixed due to PMIC interrupts missing in DT
- a collection of i.MX fixes
- minor Tegra fix for regulators
- Rockchip fix and addition of SoC-specific mailing list to make it
easier to find posted patches"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
bus: arm-ccn: Fix warning message
ARM: shmobile: koelsch: Remove non-existent i2c6 pinmux
ARM: tegra: apalis/colibri t30: fix on-module 5v0 supplies
MAINTAINERS: add new Rockchip SoC list
ARM: dts: rockchip: readd missing mmc0 pinctrl settings
ARM: dts: ODROID i2c improvements
ARM: dts: Enable PMIC interrupts on ODROID
ARM: dts: imx6sx: fix the pad setting for uart CTS_B
ARM: dts: i.MX53: fix apparent bug in VPU clks
ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
ARM: dts: imx6: edmqmx6: change enet reset pin
ARM: dts: vf610-twr: Fix pinctrl_esdhc1 pin definitions.
ARM: imx: remove unnecessary ARCH_HAS_OPP select
ARM: imx: fix TLB missing of IOMUXC base address during suspend
ARM: imx6: fix SMP compilation again
ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes
- A largeish fix for the IRQ handling in the new Zynq driver.
The quite verbose commit message gives the exact details.
- Move some defines for gpiod flags outside an ifdef to make
stub functions work again.
- Various minor fixes that we can accept for -rc1.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT+ZCiAAoJEEEQszewGV1zOZEQALkGrQacC9pZdhw93+wumj/d
goA4B1VSwi+vlQ3DcF7oXbTcbaYfGu58ZAlShc9XhVINaWEkVfc1GnBCq9rsnjNh
/rPaqDpqqBo7tfghjsMIZFdlNH151u/4rCAFMUB/STOAlUckSCiqWdxd7wMhAPlZ
yLD5oKqm3mWu/PX2n334rkLb1UxT1vIniB3DgQRhUtrKeYarH9OpzJnWnCCmspCr
GeVWpq4Z851fHMok5D76EbLL57JykTCC7VjHyK9jrmbjpMFX6+lYmWWMCOgUHypi
zA5ZEL7PjhhrZlwTN5yn8QbuSfbmT14tTUP/OLtItE0CYjF1nheyxueKErHT+DP4
piLDZgdv79ZYBSbvfbpjeO5VLkZz3m7EAGp/0kWy89uGcwjVsk+zsDSDc0v09tTk
hYRhu5/gc8zp3rd7v4DspSBbpxK+iI7uMzaGuv32AEdPvFzDVy4SJmRN/qTt/W9E
KVAdk4OJdx7xb9ee9Z2OfdbteOt0zFQjmTIneZ0urlqOZCbvbFH4PvuPB4L81SCV
XQ023OZqbBYb72Kz3Fw46NjMvRql3rkDph62oikEtfSKmSziMDY9z6bY42b0PCTq
mSovoQduN06wRDy5VQA8H1h7VF3k8NXjTI2hMEV85VhxlCzhabukBf+HY37TQIhT
pLQp0fwKmf8iZWtuF4Of
=7iYA
-----END PGP SIGNATURE-----
Merge tag 'gpio-v3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull gpio fixes from Linus Walleij:
- a largeish fix for the IRQ handling in the new Zynq driver. The
quite verbose commit message gives the exact details.
- move some defines for gpiod flags outside an ifdef to make stub
functions work again.
- various minor fixes that we can accept for -rc1.
* tag 'gpio-v3.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio-lynxpoint: enable input sensing in resume
gpio: move GPIOD flags outside #ifdef
gpio: delete unneeded test before of_node_put
gpio: zynq: Fix IRQ handlers
gpiolib: devres: use correct structure type name in sizeof
MAINTAINERS: Change maintainer for gpio-bcm-kona.c
