mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
22d1e081df
Add coolings cells property for all the CPU devicetree node for yupik, as for qultivate variant any two of the CPU cores can be fused out, So, remaining gold cores can be mitigated. Change-Id: Iccf902818f1d8587ff9b88b725817ff0d5d2ee0e
299 lines
6.3 KiB
Devicetree
299 lines
6.3 KiB
Devicetree
/ {
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/delete-node/ cpus;
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// /delete-node/ energy-costs;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_2>;
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#cooling-cells = <2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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next-level-cache = <&L2_3>;
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#cooling-cells = <2>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_4>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_5>;
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#cooling-cells = <2>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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next-level-cache = <&L2_6>;
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#cooling-cells = <2>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1964>;
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dynamic-power-coefficient = <520>;
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qcom,freq-domain = <&cpufreq_hw 2 4>;
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next-level-cache = <&L2_7>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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};
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&soc {
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qcom,cpu0-cpugrp {
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qcom,cpu4-cpu-llcc-latmon {
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 300, 16) >,
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< 940800 MHZ_TO_MBPS( 466, 16) >,
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< 1228800 MHZ_TO_MBPS( 600, 16) >,
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< 1651200 MHZ_TO_MBPS( 806, 16) >;
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};
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qcom,cpu4-llcc-ddr-latmon {
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ddr4-map {
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 451, 4) >,
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< 940800 MHZ_TO_MBPS( 547, 4) >,
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< 1228800 MHZ_TO_MBPS(1017, 4) >,
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< 1651200 MHZ_TO_MBPS(1555, 4) >;
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};
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ddr5-map {
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 451, 4) >,
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< 940800 MHZ_TO_MBPS( 547, 4) >,
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< 1228800 MHZ_TO_MBPS( 768, 4) >,
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< 1651200 MHZ_TO_MBPS(1555, 4) >,
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< 1900800 MHZ_TO_MBPS(1708, 4) >;
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};
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};
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qcom,cpu4-computemon {
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ddr4-map {
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 451, 4) >,
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< 1228800 MHZ_TO_MBPS( 547, 4) >,
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< 1516800 MHZ_TO_MBPS( 768, 4) >,
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< 1651200 MHZ_TO_MBPS(1017, 4) >,
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< 1900800 MHZ_TO_MBPS(1555, 4) >;
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};
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ddr5-map {
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qcom,core-dev-table =
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< 691200 MHZ_TO_MBPS( 451, 4) >,
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< 1228800 MHZ_TO_MBPS( 547, 4) >,
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< 1516800 MHZ_TO_MBPS( 768, 4) >,
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< 1651200 MHZ_TO_MBPS(1555, 4) >,
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< 1900800 MHZ_TO_MBPS(1708, 4) >;
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};
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};
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qcom,cpu4-llcc-computemon {
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qcom,core-dev-table =
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< 1900800 MHZ_TO_MBPS( 150, 16) >;
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};
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};
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qcom,cpu4_grp {
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qcom,cpu4-rimps-l3-latmon {
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qcom,core-dev-table =
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< 940800 556800000 >,
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< 1228800 768000000 >,
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< 1651200 1190400000 >,
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< 1900800 1401600000 >;
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};
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};
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};
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&cpu4_llcc_computemon {
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qcom,core-dev-table =
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< 1900800 MHZ_TO_MBPS( 150, 16) >;
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};
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&cpu7_computemon {
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ddr4-map {
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qcom,core-dev-table =
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< 2380800 MHZ_TO_MBPS( 451, 4) >;
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};
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ddr5-map {
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qcom,core-dev-table =
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< 2380800 MHZ_TO_MBPS( 451, 4) >;
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};
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};
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&cpu7_l3_computemon {
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qcom,core-dev-table =
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< 2035200 300000000 >;
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};
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&cpu7_qoslatmon {
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qcom,core-dev-table =
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< 2035200 1 >;
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};
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&cpu7_rimps_l3_latmon {
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qcom,core-dev-table =
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< 1056000 556800000 >,
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< 1324800 768000000 >,
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< 1766400 1190400000 >;
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};
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