mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
a240e221b8
Correct SSCTL instance ID to register the SSCTL QMI service. Change-Id: If7b82c8e4ed50df52184972c9eca77e5a53f859d
1260 lines
28 KiB
Devicetree
1260 lines
28 KiB
Devicetree
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sdxnightjar.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sdxnightjar.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
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#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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/ {
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model = "Qualcomm Technologies, Inc. SDXNIGHTJAR";
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compatible = "qcom,sdxnightjar";
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qcom,msm-id = <484 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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chosen { };
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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reserved_memory: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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peripheral1_mem: peripheral1_region@0x87800000 {
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no-map;
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reg = <0x87800000 0x400000>;
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label = "peripheral1_mem";
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};
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peripheral2_mem: peripheral2_region@0x87d00000 {
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no-map;
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reg = <0x87d00000 0x100000>;
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label = "peripheral2_mem";
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};
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smem_mem: smem_region@0x87e80000 {
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no-map;
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reg = <0x87e80000 0xc0000>;
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label = "smem_mem";
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};
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mss_mem: mss_region@0x88000000 {
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no-map;
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reg = <0x88000000 0x6600000>;
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label = "mss_mem";
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};
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common_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00000000 0xffffffff>;
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reusable;
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alignment = <0x400000>;
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size = <0xc00000>;
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linux,cma-default;
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};
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};
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aliases { };
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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qcom,dload-mode = <&tcsr 0x6100>;
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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qcom,custom-bridge-size = <256>;
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};
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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wakegic: wake-gic {
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compatible = "qcom,mpm-gic-sdxnightjar", "qcom,mpm";
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interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
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reg = <0x601b8 0x1000>,
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<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
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reg-names = "vmpm", "ipc";
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qcom,num-mpm-irqs = <96>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <2>;
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};
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system_pm_rpm {
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compatible = "qcom,system-pm-rpm";
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};
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qcom,mpm2-sleep-counter@4a3000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0x004a3000 0x1000>;
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clock-frequency = <32768>;
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};
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qcom,msm-imem@8600000 {
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compatible = "qcom,msm-imem";
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reg = <0x8600000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x8600000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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};
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mss: qcom,mss@4080000{
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compatible = "qcom,pil-q6v55-mss";
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reg = <0x4080000 0x100>,
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<0x194e000 0x400>,
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<0x4180000 0x040>,
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<0x1810000 0x004>;
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reg-names = "qdsp6_base", "halt_base", "rmb_base",
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"restart_reg";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_MSS_CFG_AHB_CLK>,
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<&gcc GCC_MSS_Q6_BIMC_AXI_CLK >,
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<&gcc GCC_BOOT_ROM_AHB_CLK>,
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<&gcc GCC_MSS_GPLL0_CLK_SRC>,
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<&rpmcc RPM_SMD_QPIC_CLK>;
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clock-names = "xo", "iface_clk", "bus_clk", "mem_clk",
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"gpll0_mss_clk", "qpic";
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qcom,proxy-clock-names = "xo";
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qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
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"gpll0_mss_clk";
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vdd_cx-supply = <&pmd9650_s5_level>;
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interrupts = <0 24 1>;
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vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
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vdd_mx-supply = <&pmd9650_l9_level>;
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vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
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vdd_pll-supply = <&pmd9650_l5>;
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qcom,vdd_pll = <1800000>;
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qcom,firmware-name = "modem";
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qcom,pil-self-auth;
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qcom,sysmon-id = <0>;
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qcom,ssctl-instance-id = <0x22>;
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qcom,override-acc;
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qcom,qdsp6v61-1-1;
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memory-region = <&mss_mem>;
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qcom,reset-clk;
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qcom,sequential-fw-load;
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interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<&modem_smp2p_in 0 0>,
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<&modem_smp2p_in 2 0>,
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<&modem_smp2p_in 1 0>,
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<&modem_smp2p_in 3 0>,
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<&modem_smp2p_in 7 0>;
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interrupt-names = "qcom,wdog",
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"qcom,err-fatal",
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"qcom,proxy-unvote",
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"qcom,err-ready",
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"qcom,stop-ack",
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"qcom,shutdown-ack";
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qcom,smem-states = <&modem_smp2p_out 0>;
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qcom,smem-state-names = "qcom,force-stop";
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status = "ok"
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "chip_sleep_clk";
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#clock-cells = <0>;
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};
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};
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rpmcc: qcom,rpmcc {
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compatible = "qcom,rpmcc-sdxnightjar";
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#clock-cells = <1>;
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};
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gcc: qcom,gcc@1800000 {
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compatible = "qcom,sdxnightjar-gcc", "syscon";
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reg = <0x1800000 0x80000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&rpmcc RPM_SMD_XO_A_CLK_SRC>;
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clock-names = "bi_tcxo", "bi_tcxo_ao";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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cpucc: syscon@b01101c {
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compatible = "syscon";
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reg = <0xb01101c 0x4>;
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};
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debugcc: qcom,cc-debug@1874000 {
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compatible = "qcom,sdxnightjar-debugcc";
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qcom,gcc = <&gcc>;
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qcom,cpucc = <&cpucc>;
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clock-names = "xo_clk_src";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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#clock-cells = <1>;
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};
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gdsc_usb30: qcom,gdsc@fc401e84 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_usb30";
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reg = <0x185e078 0x4>;
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};
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gdsc_pcie: qcom,gdsc@0xfc401e18 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_pcie";
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reg = <0x0185d044 0x4>;
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};
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apsscc: clock-controller@b010008 {
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compatible = "qcom,sdxnightjar-apsscc";
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clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&gcc GPLL0_AO>;
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clock-names = "bi_tcxo_ao", "gpll0_out_even";
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reg = <0xb010008 0x8>, <0xb008018 0x28>;
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reg-names = "apcs_cmd", "apcs_pll";
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vdd-pll-supply = <&VDD_CX_LEVEL_AO>;
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cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
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qcom,speed0-bin-v0 =
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< 0 RPM_SMD_REGULATOR_LEVEL_NONE>,
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< 200000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS>,
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< 384000000 RPM_SMD_REGULATOR_LEVEL_SVS>,
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< 787200000 RPM_SMD_REGULATOR_LEVEL_NOM>,
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< 1286400000 RPM_SMD_REGULATOR_LEVEL_TURBO>;
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#clock-cells = <1>;
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};
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qcom,msm-cpufreq {
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compatible = "qcom,msm-cpufreq";
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clocks = <&apsscc APCS_MUX_CLK>;
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clock-names = "cpu0_clk";
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qcom,cpufreq-table =
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< 200000 >,
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< 300000 >,
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< 384000 >,
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< 600000 >,
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< 787200 >,
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< 998400 >,
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< 1190400 >,
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< 1286400 >;
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};
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ahb_bw_opp_table: ahb-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 19, 8); /* 144 MB/s */
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BW_OPP_ENTRY( 50, 8); /* 381 MB/s */
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BW_OPP_ENTRY( 100, 8); /* 762 MB/s */
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BW_OPP_ENTRY( 133, 8); /* 1014 MB/s */
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};
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ahb_clk: qcom,ahb-clk-src {
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compatible = "devfreq-simple-dev";
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clocks = <&gcc APSS_AHB_CLK_SRC>;
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clock-names = "devfreq_clk";
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governor = "powersave";
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qcom,bus-width = <8>;
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operating-points-v2 = <&ahb_bw_opp_table>;
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};
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cpubw: qcom,cpubw {
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compatible = "qcom,devfreq-icc";
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governor = "cpufreq";
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interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;
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qcom,active-only;
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operating-points-v2 = <&ddr_bw_opp_table>;
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};
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ddr_bw_opp_table: ddr-bw-opp-table {
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compatible = "operating-points-v2";
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BW_OPP_ENTRY( 202, 8); /* 1541 MB/s */
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BW_OPP_ENTRY( 404, 8); /* 3082 MB/s */
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BW_OPP_ENTRY( 518, 8); /* 3952 MB/s */
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};
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devfreq-cpufreq {
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cpubw-cpufreq {
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target-dev = <&cpubw>;
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cpu-to-dev-map =
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< 600000 1541 >,
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< 787200 3082 >,
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< 1286400 3952 >;
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};
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cpuahb-cpufreq {
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target-dev = <&ahb_clk>;
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cpu-to-dev-map =
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< 200000 144 >,
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< 384000 381 >,
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< 787200 762 >,
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< 1286400 1014 >;
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};
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>,
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<0x0193d100 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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timer@b020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb020000 0x1000>;
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clock-frequency = <19200000>;
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frame@b021000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0xb021000 0x1000>,
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<0xb022000 0x1000>;
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};
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frame@b023000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0xb023000 0x1000>;
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status = "disabled";
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};
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frame@b024000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0xb024000 0x1000>;
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status = "disabled";
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};
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frame@b025000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0xb025000 0x1000>;
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status = "disabled";
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};
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frame@b026000 {
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frame-number = <4>;
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interrupts = <0 11 0x4>;
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reg = <0xb026000 0x1000>;
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status = "disabled";
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};
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frame@b027000 {
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frame-number = <5>;
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interrupts = <0 12 0x4>;
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reg = <0xb027000 0x1000>;
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status = "disabled";
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};
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frame@b028000 {
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frame-number = <6>;
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interrupts = <0 13 0x4>;
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reg = <0xb028000 0x1000>;
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status = "disabled";
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};
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frame@b029000 {
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frame-number = <7>;
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interrupts = <0 14 0x4>;
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reg = <0xb029000 0x1000>;
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status = "disabled";
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};
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};
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mem_dump {
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compatible = "qcom,mem-dump";
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memory-region = <&common_cma>;
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c0_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x0>;
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};
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etr_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x100>;
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};
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tmc_etf {
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qcom,dump-size = <0x2000>;
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qcom,dump-id = <0xf0>;
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};
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etf_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x101>;
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};
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dbgui_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe5>;
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};
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etm_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xa0>;
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};
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log_buf {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x110>;
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};
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log_idx {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x111>;
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};
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misc_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe8>;
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};
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pmic_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe4>;
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};
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vsense_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe9>;
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};
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rpm_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xea>;
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};
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};
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qcom,sps {
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compatible = "qcom,msm-sps-4k";
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qcom,pipe-attr-ee;
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};
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qcom-secure-buffer {
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compatible = "qcom,secure-buffer";
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};
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|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom_rng: qrng@e3000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0xe3000 0x1000>;
|
|
qcom,msm-rng-iface-clk;
|
|
qcom,no-qrng-config;
|
|
qcom,msm-bus,name = "msm-rng-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 618 0 0>, /* No vote */
|
|
<1 618 0 800>; /* 100 MB/s */
|
|
/*TODO: Fix the clock when tree is available*/
|
|
clock-names = "iface_clk";
|
|
};
|
|
|
|
qcom_tzlog: tz-log@08600720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x08600720 0x2000>;
|
|
};
|
|
|
|
qcom,qcedev@720000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x720000 0x20000>,
|
|
<0x704000 0x20000>;
|
|
reg-names = "crypto-base","crypto-bam-base";
|
|
interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bam-pipe-pair = <1>;
|
|
qcom,ce-hw-instance = <0>;
|
|
qcom,ce-device = <0>;
|
|
qcom,ce-hw-shared;
|
|
qcom,msm-bus,name = "qcedev-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<47 512 0 0>,
|
|
<47 512 393600 393600>;
|
|
/*TODO: Fix the clock when tree is available*/
|
|
clock-names = "core_clk", "iface_clk",
|
|
"bus_clk","core_clk_src";
|
|
qcom,ce-opp-freq = <171430000>;
|
|
};
|
|
|
|
qcom,qcrypto@720000 {
|
|
compatible = "qcom,qcrypto";
|
|
reg = <0x720000 0x20000>,
|
|
<0x704000 0x20000>;
|
|
reg-names = "crypto-base","crypto-bam-base";
|
|
interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bam-pipe-pair = <2>;
|
|
qcom,ce-hw-instance = <0>;
|
|
qcom,ce-device = <0>;
|
|
qcom,ce-hw-shared;
|
|
qcom,msm-bus,name = "qcrypto-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<47 512 0 0>,
|
|
<47 512 393600 393600>;
|
|
/*TODO: Fix the clock when tree is available*/
|
|
clock-names = "core_clk", "iface_clk",
|
|
"bus_clk","core_clk_src";
|
|
qcom,use-sw-aes-cbc-ecb-ctr-algo;
|
|
qcom,use-sw-aes-xts-algo;
|
|
qcom,use-sw-aes-ccm-algo;
|
|
qcom,use-sw-ahash-algo;
|
|
qcom,use-sw-hmac-algo;
|
|
qcom,use-sw-aead-algo;
|
|
qcom,ce-opp-freq = <171430000>;
|
|
};
|
|
|
|
qcom_seecom: qseecom@87800000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x87800000 0x200000>;
|
|
reg-names = "secapp-region";
|
|
memory-region = <&common_cma>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
qcom,support-bus-scaling;
|
|
interconnect-names = "data_path";
|
|
interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>;
|
|
/*TODO: Fix the clock when tree is available*/
|
|
clock-names = "core_clk", "iface_clk",
|
|
"bus_clk","core_clk_src";
|
|
clocks =
|
|
<&rpmcc RPM_SMD_CE1_CLK>,
|
|
<&rpmcc RPM_SMD_CE1_CLK>,
|
|
<&rpmcc RPM_SMD_CE1_CLK>,
|
|
<&rpmcc RPM_SMD_CE1_CLK>;
|
|
qcom,ce-opp-freq = <100000000>;
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
};
|
|
|
|
blsp1_uart1: serial@78af000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78af000 0x200>;
|
|
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_uart2: serial@78b0000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78b0000 0x200>;
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_uart3: serial@78b1000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78b1000 0x200>;
|
|
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
rpm_bus: qcom,rpm-smd {
|
|
compatible = "qcom,rpm-smd";
|
|
rpm-channel-name = "rpm_requests";
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
|
rpm-channel-type = <15>; /* SMD_APPS_RPM */
|
|
};
|
|
|
|
qcom,wdt@b017000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0xb017000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <1 3 IRQ_TYPE_EDGE_RISING>,
|
|
<1 2 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <10000>;
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
jtag_mm0: jtagmm@842000 {
|
|
compatible = "qcom,jtag-mm";
|
|
reg = <0x842000 0x1000>,
|
|
<0x840000 0x1000>;
|
|
reg-names = "etm-base","debug-base";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU0>;
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
|
|
clock-names = "apb_pclk";
|
|
|
|
};
|
|
|
|
tcsr_mutex_regs: syscon@1905000 {
|
|
compatible = "syscon";
|
|
reg = <0x1905000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_regs 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@0x1937000 {
|
|
compatible = "syscon";
|
|
reg = <0x1937000 0x21000>;
|
|
};
|
|
|
|
apcs_glb: mailbox@0xb011008 {
|
|
compatible = "qcom,sdxnightjar-apcs-gcc";
|
|
reg = <0xb011008 0x4>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
rpm_msg_ram: memory@60000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x60000 0x6000>;
|
|
};
|
|
|
|
qcom,ipc-spinlock@1905000 {
|
|
compatible = "qcom,ipc-spinlock-sfpb";
|
|
reg = <0x1905000 0x8000>;
|
|
qcom,num-locks = <8>;
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qcom,smd {
|
|
compatible = "qcom,smd";
|
|
|
|
modem {
|
|
qcom,smd-edge = <0>;
|
|
mboxes = <&apcs_glb 12>;
|
|
qcom,remote-pid = <1>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
|
|
label = "mpss";
|
|
|
|
qcom,smd-channels = "IPCRTR";
|
|
qcom,modem_qrtr {
|
|
qcom,low-latency;
|
|
};
|
|
};
|
|
|
|
rpm {
|
|
qcom,smd-edge = <15>;
|
|
mboxes = <&apcs_glb 0>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
|
label = "rpm";
|
|
|
|
rpm_requests: rpm_requests@0 {
|
|
compatible = "qcom,rpm-smd";
|
|
qcom,smd-channels = "rpm_requests";
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 15>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-data5-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA5_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl0";
|
|
};
|
|
|
|
qcom,glinkpkt-data6-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA6_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl1";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-data21 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA21";
|
|
qcom,glinkpkt-dev-name = "smd21";
|
|
};
|
|
|
|
qcom,glinkpkt-data22 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA22";
|
|
qcom,glinkpkt-dev-name = "smd22";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
};
|
|
|
|
qnand_1: nand@7980000 {
|
|
compatible = "qcom,msm-nand";
|
|
reg = <0x07980000 0x1000>,
|
|
<0x07984000 0x1a000>;
|
|
reg-names = "nand_phys",
|
|
"bam_phys";
|
|
qcom,reg-adjustment-offset = <0x4000>;
|
|
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "bam_irq";
|
|
|
|
clock-names = "core_clk";
|
|
clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
|
|
|
|
interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>;
|
|
interconnect-names = "nand-ddr";
|
|
qcom,msm-bus,name = "qpic_nand";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<0 0>,
|
|
/* Voting for max b/w on PNOC bus for now */
|
|
<400000 400000>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc_1: sdhci@7824000 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x07824900 0x500>, <0x07824000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
qcom,devfreq,freq-table = <50000000 200000000>;
|
|
|
|
interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
|
|
interconnect-names = "sdhc-ddr";
|
|
qcom,msm-bus,name = "sdhc1";
|
|
qcom,msm-bus,num-cases = <7>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
|
|
qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */
|
|
<1600 3200>, /* 400 KB/s*/
|
|
<100000 200000>, /* 25 MB/s */
|
|
<200000 400000>, /* 50 MB/s */
|
|
<400000 800000>, /* 100 MB/s */
|
|
<400000 800000>, /* 200 MB/s */
|
|
<2048000 4096000>; /* Max. bandwidth */
|
|
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
|
|
100000000 200000000 4294967295>;
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
|
|
bus-width = <4>;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0x1>;
|
|
vote = <70>;
|
|
};
|
|
};
|
|
|
|
thermal_zones: thermal-zones {};
|
|
|
|
spmi_bus: qcom,spmi@200f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x200f000 0x1000>,
|
|
<0x2400000 0x800000>,
|
|
<0x2c00000 0x800000>,
|
|
<0x3800000 0x200000>,
|
|
<0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts-extended = <&wakegic 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
#interrupt-cells = <4>;
|
|
interrupt-controller;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
bimc: interconnect@400000 {
|
|
reg = <0x400000 0x62000>;
|
|
compatible = "qcom,sdxnightjar-bimc";
|
|
qcom,util-factor = <153>;
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
|
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
|
};
|
|
|
|
pc_noc: interconnect@500000 {
|
|
reg = <0x500000 0x11000>;
|
|
compatible = "qcom,sdxnightjar-pcnoc";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
|
|
<&rpmcc RPM_SMD_PCNOC_A_CLK>;
|
|
};
|
|
|
|
system_noc: interconnect@580000 {
|
|
reg = <0x580000 0x14000>;
|
|
compatible = "qcom,sdxnightjar-snoc";
|
|
qcom,keepalive;
|
|
#interconnect-cells = <1>;
|
|
clock-names = "bus", "bus_a";
|
|
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
|
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
};
|
|
|
|
ipa_hw: qcom,ipa@07B00000 {
|
|
compatible = "qcom,ipa";
|
|
reg = <0x07B00000 0x34000>,
|
|
<0x07B84000 0x31FFFF>,
|
|
<0x07B04000 0x2C000>;
|
|
reg-names = "ipa-base", "bam-base", "gsi-base";
|
|
interrupts =
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
|
|
qcom,ipa-hw-ver = <10>; /* IPA core version = IPAv3.0 */
|
|
qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
|
|
qcom,platform-type = <0>; /* MDM platform */
|
|
qcom,ee = <0>;
|
|
qcom,use-rg10-limitation-mitigation;
|
|
qcom,use-wrapper-pm-support;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
clock-names = "core_clk";
|
|
clocks = <&rpmcc RPM_SMD_IPA_CLK>;
|
|
qcom,interconnect,num-cases = <5>;
|
|
qcom,interconnect,num-paths = <3>;
|
|
interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>,
|
|
<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
|
|
<&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_IPA_CFG>;
|
|
interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa";
|
|
/* No vote */
|
|
qcom,no-vote =
|
|
<0 0 0 0 0 0>;
|
|
/* SVS2 */
|
|
qcom,svs2 =
|
|
<80000 64000 80000 64000 80000 16000>;
|
|
/* SVS */
|
|
qcom,svs =
|
|
<80000 640000 80000 640000 80000 160000>;
|
|
/* NOMINAL */
|
|
qcom,nominal =
|
|
<206000 960000 206000 960000 206000 400000>;
|
|
/* TURBO */
|
|
qcom,turbo =
|
|
<206000 3600000 206000 3600000 206000 960000>;
|
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
|
|
|
|
qcom,throughput-threshold = <310 600 1000>;
|
|
qcom,scaling-exceptions = <>;
|
|
|
|
/* ipa tz unlock registers */
|
|
qcom,ipa-tz-unlock-reg =
|
|
<0x4043583c 0x1000>; /* 32-bit reg addr and size */
|
|
/* smp2p gpio information */
|
|
qcom,smp2p_map_ipa_1_out {
|
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
|
qcom,smem-states = <&smp2p_ipa_1_out 0>;
|
|
qcom,smem-state-names = "ipa-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_map_ipa_1_in {
|
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
|
interrupts-extended = <&smp2p_ipa_1_in 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ipa-smp2p-in";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "pmd9650.dtsi"
|
|
#include "pmd9650-rpm-regulator.dtsi"
|
|
#include "sdxnightjar-regulator.dtsi"
|
|
#include "sdxnightjar-usb.dtsi"
|
|
#include "sdxnightjar-coresight.dtsi"
|
|
#include "sdxnightjar-pinctrl.dtsi"
|
|
#include "sdxnightjar-ion.dtsi"
|
|
#include "sdxnightjar-pm.dtsi"
|
|
#include "sdxnightjar-blsp.dtsi"
|
|
#include "sdxnightjar-cnss.dtsi"
|
|
#include "sdxnightjar-pcie.dtsi"
|
|
#include "sdxnightjar-audio.dtsi"
|
|
#include "sdxnightjar-audio-overlay.dtsi"
|
|
#include "sdxnightjar-thermal.dtsi"
|
|
|
|
&pmd9650_gpios {
|
|
ambient_therm {
|
|
ambient_therm_default: ambient_therm_default {
|
|
pins = "gpio2";
|
|
bias-high-impedance;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pmd9650_vadc {
|
|
case_therm {
|
|
reg = <ADC5_AMUX_THM1_100K_PU>;
|
|
label = "case_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
pa_therm1 {
|
|
reg = <ADC5_AMUX_THM2_100K_PU>;
|
|
label = "pa_therm1";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
pa_therm2 {
|
|
reg = <ADC5_AMUX_THM3_100K_PU>;
|
|
label = "pa_therm2";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
|
|
ambient_therm {
|
|
reg = <ADC5_GPIO2_100K_PU>;
|
|
label = "ambient_therm";
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
qcom,pre-scaling = <1 1>;
|
|
};
|
|
};
|
|
|
|
&spmi_bus {
|
|
qcom,pmd9650@0 {
|
|
pmd9650_adc_tm_iio: adc_tm@3400 {
|
|
compatible = "qcom,adc-tm5-iio";
|
|
reg = <0x3400>;
|
|
#thermal-sensor-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
io-channels = <&pmd9650_vadc ADC5_XO_THERM_100K_PU>,
|
|
<&pmd9650_vadc ADC5_AMUX_THM1_100K_PU>,
|
|
<&pmd9650_vadc ADC5_AMUX_THM2_100K_PU>,
|
|
<&pmd9650_vadc ADC5_AMUX_THM3_100K_PU>,
|
|
<&pmd9650_vadc ADC5_GPIO2_100K_PU>;
|
|
|
|
xo_therm {
|
|
reg = <ADC5_XO_THERM_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
case_therm {
|
|
reg = <ADC5_AMUX_THM1_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
pa_therm1 {
|
|
reg = <ADC5_AMUX_THM2_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
pa_therm2 {
|
|
reg = <ADC5_AMUX_THM3_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
|
|
ambient_therm {
|
|
reg = <ADC5_GPIO2_100K_PU>;
|
|
qcom,ratiometric;
|
|
qcom,hw-settle-time = <200>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&thermal_zones {
|
|
xo-therm-usr {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <&pmd9650_adc_tm_iio ADC5_XO_THERM_100K_PU>;
|
|
wake-capable-sensor;
|
|
trips {
|
|
active-config0 {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
case-therm-usr {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM1_100K_PU>;
|
|
wake-capable-sensor;
|
|
trips {
|
|
active-config0 {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pa-therm1-usr {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM2_100K_PU>;
|
|
wake-capable-sensor;
|
|
trips {
|
|
active-config0 {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pa-therm2-usr {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM3_100K_PU>;
|
|
wake-capable-sensor;
|
|
trips {
|
|
active-config0 {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ambient-therm-usr {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-governor = "user_space";
|
|
thermal-sensors = <&pmd9650_adc_tm_iio ADC5_GPIO2_100K_PU>;
|
|
wake-capable-sensor;
|
|
trips {
|
|
active-config0 {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c_3 {
|
|
status = "ok"
|
|
smb1351_otg_supply: smb1351-charger@55 {
|
|
compatible = "qcom,smb1351-charger";
|
|
reg = <0x55>;
|
|
interrupt-parent = <&tlmm_pinmux>;
|
|
interrupts = <83 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupts-extended = <&tlmm_pinmux 83 IRQ_TYPE_LEVEL_LOW>, <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "smb1351_chg_stat_irq","smb1351_usb_id_irq";
|
|
qcom,usb-id-gpio = <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>;
|
|
qcom,float-voltage-mv = <4200>;
|
|
qcom,charging-timeout = <1536>;
|
|
qcom,recharge-thresh-mv = <200>;
|
|
qcom,iterm-ma = <100>;
|
|
regulator-name = "smb1351_otg_supply";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&smb_stat_active>, <&usb_id_detect>;
|
|
qcom,switch-freq = <2>;
|
|
qcom,id-line-not-connected;
|
|
dpdm-supply = <&qusb_phy>;
|
|
};
|
|
};
|
|
|
|
&usb3 {
|
|
extcon = <&smb1351_otg_supply>;
|
|
};
|