mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
bbd1fae265
"non-fatal" -> smmu will not bug_on for s1 fault. Avoid system crash when CVP SMMU fault happens. CVP SSR can recover SMMU fault now "stall-disable" -> smmu terminates pending transaction Invokes smmu_fault_handler and triggers vnoc interrupt independently. So firmware can quickly write sys_error pkt(previous transactions were not stalled for that CB) to message queue. Change-Id: I749741801dcf2599ccd3b51b53c326629adaebfb
99 lines
2.6 KiB
Devicetree
99 lines
2.6 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/interconnect/qcom,shima.h>
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#include <dt-bindings/clock/qcom,videocc-shima.h>
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&soc {
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,shima-cvp";
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status = "ok"
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* Supply */
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cvp-supply = <&video_cc_mvs1c_gdsc>;
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cvp-core-supply = <&video_cc_mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi1", "cvp_clk", "core_clk";
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clocks = <&gcc GCC_VIDEO_AXI1_CLK>,
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<&videocc VIDEO_CC_MVS1C_CLK>,
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<&videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi1",
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"cvp_clk", "core_clk";
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qcom,clock-configs = <0x0 0x1 0x1>;
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qcom,allowed-clock-rates = <280000000 366000000 444000000>;
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resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
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<&videocc VIDEO_CC_MVS1C_CLK_ARES>;
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reset-names = "cvp_axi_reset", "cvp_core_reset";
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reset-power-status = <0x2 0x1>;
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qcom,reg-presets = <0xB0088 0x0>;
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qcom,ipcc-reg = <0x400000 0x100000>;
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/* CVP Firmware ELF image name */
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cvp,firmware-name = "evass-lt";
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/* Buses */
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cvp_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cvp-cnoc";
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qcom,bus-master = <MASTER_APPSS_PROC>;
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qcom,bus-slave = <SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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cvp_bus_ddr {
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compatible = "qcom,msm-cvp,bus";
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label = "cvp-ddr";
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qcom,bus-master = <MASTER_VIDEO_PROC>;
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qcom,bus-slave = <SLAVE_EBI1>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 6533000>;
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};
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/* MMUs */
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cvp_non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus =
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<&apps_smmu 0x2920 0x400>;
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buffer-types = <0xfff>;
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dma-coherent-hint-cached;
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qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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cvp_secure_nonpixel_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_sec_nonpixel";
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iommus =
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<&apps_smmu 0x2924 0x400>;
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buffer-types = <0x741>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
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qcom,iommu-vmid = <0xB>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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cvp_secure_pixel_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_sec_pixel";
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iommus =
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<&apps_smmu 0x2923 0x400>;
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buffer-types = <0x106>;
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qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
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qcom,iommu-vmid = <0xA>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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};
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