A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Filename Latest commit message Latest commit date
Tony Truong ab0460954f ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur 
On sdxlemur, PCIe L1.2 exit is about 150us. Therefore update PCIe
so that it will program all PCI devices LTR register with 150us.
Devices can use this value to deterine if L1.2 should be entered
or not based on their latency requirement.

Change-Id: Ife11959879bd7c09b9cbe256b5e46933124ad6b1
2021-03-09 18:19:44 -08:00
bindings Merge "ARM: dts: msm: Add veth ipa documentation for device node" 2021-03-09 02:40:38 -08:00
qcom ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur 2021-03-09 18:19:44 -08:00
Makefile ARM: dts: vendor: Add an initial Makefile to the vendor 2019-06-04 16:50:48 -07:00