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ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur

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On sdxlemur, PCIe L1.2 exit is about 150us. Therefore update PCIe
so that it will program all PCI devices LTR register with 150us.
Devices can use this value to deterine if L1.2 should be entered
or not based on their latency requirement.

Change-Id: Ife11959879bd7c09b9cbe256b5e46933124ad6b1
This commit is contained in:
Tony Truong 2021-03-09 18:19:44 -08:00
commit ab0460954f
2 changed files with 2 additions and 2 deletions
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2
qcom/sdxlemur-mtp-mbb.dtsi
View file

@ -30,8 +30,6 @@
&pcie0 {
qcom,boot-option = <0x1>;
qcom,l1-2-th-scale = <2>; /* 1us */
qcom,l1-2-th-value = <70>;
};
&pm7250b_vadc {

2
qcom/sdxlemur-pcie.dtsi
View file

@ -109,6 +109,8 @@
<0x100 &apps_smmu 0x0201 0x1>;
qcom,aux-clk-freq = <17>; /* 16.6 MHz */
qcom,l1-2-th-scale = <2>; /* 1us */
qcom,l1-2-th-value = <150>;
qcom,eq-fmdc-t-min-phase23 = <1>;
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;