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Merge commit '5ce01ccf3e' into remote

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Change-Id: Ie235ac169bf551dd89f714471fe4595a7d4bc099
This commit is contained in:
Naveen Kumar 2020-10-22 01:24:52 +05:30
commit 09045d2068
93 changed files with 8835 additions and 382 deletions
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5
bindings/arm/msm/msm.txt
View file

@ -83,6 +83,9 @@ SoCs:
- SDXLEMUR
compatible = "qcom,sdxlemur"
- SCUBA
compatible = "qcom,scuba-iot"
- SDMMAGPIE
compatible = "qcom,sdmmagpie"
@ -235,6 +238,7 @@ compatible = "qcom,sdxprairie-cdp"
compatible = "qcom,sdxlemur-rumi"
compatible = "qcom,sdxlemur-mtp"
compatible = "qcom,sdxlemur-cdp"
compatible = "qcom,sdxlemur-rcm"
compatible = "qcom,sdmmagpie-rumi"
compatible = "qcom,sdmmagpie-idp"
compatible = "qcom,sdmmagpie-qrd"
@ -243,3 +247,4 @@ compatible = "qcom,holi-mtp"
compatible = "qcom,holi-cdp"
compatible = "qcom,holi-qrd"
compatible = "qcom,holi-atp"
compatible = "qcom,scuba-idp"

36
bindings/arm/msm/qcom,qfprom-sys.yaml Normal file
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@ -0,0 +1,36 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/arm/msm/qcom,qfprom-sys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. QFPROM_SYS driver binding
maintainers:
description: |+
QFPROM_SYS provides access to the nvmem cells to the user space.
The driver exports the cell values as sysfs entries.
properties:
compatible:
const: qcom,qfprom-sys
nvmem-cell-name:
description: array of strings for cell names
nvmem-cells:
description: phandle to particular cell from provider
required:
- compatible
- nvmem-cell-name
- nvmem-cells
example:
- |
qfprom@0 {
compatible = "qcom,qfprom-sys";
nvmem-cells = <&tsens_calibration1>, <&tsens_calibration2>;
nvmem-cell-names = "calibration1", "calibration2";
};
...

2
bindings/bluetooth/btpower.txt
View file

@ -11,6 +11,7 @@ Required properties:
qcom,qca6390
qcom,qca6490
- qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset
- qcom,wl-reset-gpio: GPIO pin for WL_EN toggle
Optional properties:
- qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle
@ -38,6 +39,7 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */
qcom,bt-vdd-aon-supply = <&pm8150_s6>;
qcom,bt-vdd-dig-supply = <&pm8009_s2>;
qcom,bt-vdd-rfa1-supply = <&pm8150_s5>;

3
bindings/cnss/cnss-wlan.txt
View file

@ -87,6 +87,9 @@ Optional properties:
regulator used in internal power amplifier for QCA6490
- cnss-enable-self-recovery: Boolean property to enable self recovery when
recovery is trigeered with reason link down.
- qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO
enable to resolve PMU power up issues. Provide BT GPIO using
this config param.
Example:

42
bindings/dma/qcom-sps-dma.txt Normal file
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@ -0,0 +1,42 @@
* Qualcomm technologies inc, DMA engine driver for BAM (Bus Access Manager).
Required properties:
- compatible: Should be "qcom,sps-dma".
- reg: Should contain DMA registers location and length. This should include
all of the per-channel registers.
- interrupts: Should contain the BAM interrupt number.
- qcom,summing-threshold: Should contain the BAM event threshold of
the sum of descriptors' sizes in bytes.
Optional properties:
- qcom,managed-locally : Use when BAM global device control is managed locally
by the application processor.
Example:
dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0xf9904000 0x19000>;
interrupts = <0 238 0>;
qcom,summing-threshold = <10>;
};
DMA clients connected to the qcom-sps-dma DMA controller must use the format
described in the dma.txt file, using a five-cell specifier for each channel,
a phandle plus four integer cells, as shown below:
dmas = <[phandle of the dma controller] [pipe index] [number of descriptors]
[sps_connect flags] [sps_register_event flags]>;
Example:
i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */
.
.
.
/* <&phandle pipe-idx n-descs connect-flags event-flags> */
dmas = <&dma_blsp1 14 32 0x20000020 0x20>,
<&dma_blsp1 15 64 0x20000020 0x20>;
dma-names = "tx", "rx";
};

59
bindings/i2c/i2c-msm-v2.txt Normal file
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@ -0,0 +1,59 @@
Qualcomm Technologies, Inc. I2C controller
Required properties:
- reg : Offset and length of the register region for the device named in
reg-names and has the same index.
- reg-names : Register region name(s) referenced in reg above
"qup_phys_addr" : Physical address of QUP register space.
- compatible : should be "qcom,i2c-msm-v2"
- interrupts : Interrupt number which correspond to the entry with the same
index in interrupt-names.
- interrupt-names: QUP core interrupt name(s) referenced in interrupts above
"qup_irq" : QUP interrupt used by the controller.
- dmas : DMA engine API's parameters for blsp.
<[phandle of the dma controller] [pipe index] [number of descriptors]
[sps_connect flags] [sps_register_event flags]>;
- dma-names : dma channel names.
- qcom,clk-freq-out : Desired I2C bus clock frequency in Hz
- qcom,clk-freq-in : Supplied core clock frequency in Hz.
- qcom,i2c-dat : specifies GPIO which corresponds to the I2C data line.
- qcom,i2c-clk : specifies GPIO which corresponds to the I2C clock line.
Required alias:
- The desired bus-number is specified by an alias with the following format:
'i2c{n}' where n is the bus number.
Optional property:
- qcom,noise-rjct-scl : number of low samples on clock line to consider it low.
When missing default to 0.
- qcom,noise-rjct-sda : number of low samples on data line to consider it low.
When missing default to 0.
- qcom,disable-dma : disables DMA transfer mode.
- qcom,master-id : Master-port value used on voting for the clock path.
- qcom,high-time-clk-div : high time divider value to configure clk-ctl
register. When missing, default to the value given in driver.
- qcom,fs-clk-div: fs divider value to configure clk-ctl register. When
missing, default to the value given in driver.
Example:
aliases {
i2c10 = &i2c_10;
};
i2c_10: i2c@f9966000 {
compatible = "qcom,i2c-msm-v2";
reg-names = "qup_phys_addr", "dma_phys_addr";
reg = <0xf9966000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 104 0>;
dmas = <&dma_blsp1 14 32 0x20000020 0x20>,
<&dma_blsp1 15 64 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,clk-freq-out = <100000>;
qcom,clk-freq-in = <24000000>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
qcom,i2c-dat = <&tlmm 67 0x00>;
qcom,i2c-clk = <&tlmm 68 0x00>;
};

0
qcom/leds-qpnp-vibrator-ldo.txt → bindings/leds/leds-qpnp-vibrator-ldo.txt
View file

1
bindings/media/video/msm-vidc.txt
View file

@ -9,6 +9,7 @@ Required properties:
- "qcom,lahaina-vidc" : Invokes driver-specific data for LAHAINA.
- "qcom,shima-vidc" : Invokes driver-specific data for SHIMA.
- "qcom,holi-vidc" : Invokes driver-specific data for HOLI.
- "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK.
Optional properties:
- vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL

195
bindings/pinctrl/qcom,scuba-pinctrl.yaml Normal file
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@ -0,0 +1,195 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,scuba-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SCUBA TLMM block
description: |
This binding describes the Top Level Mode Multiplexer block found in the
SCUBA platform.
properties:
compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,scuba-pinctrl"
reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
#interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
#gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
wakeup-parent:
Usage: optional
Value type: <phandle>
Definition: A phandle to the wakeup interrupt controller for the SoC.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins:
gpio0-gpio155
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven high.
Not valid for sdc pins.
output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven low.
Not valid for sdc pins.
drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
examples:
- |
tlmm: pinctrl@400000 {
compatible = "qcom,scuba-pinctrl";
reg = <0x400000 0x800000>;
interrupts = <0 227 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

2
bindings/platform/msm/ipa.txt
View file

@ -74,6 +74,8 @@ memory allocation over a PCIe bridge
using wdi-2.0 or not
- qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether
using wdi-3.0 or not
- qcom,gsi_wdi_db_polling: Boolean context flag to indicate whether
using gsi wdi db polling or not
- qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether
ipa clock voting is done by bandwidth
voting via msm-bus-scale driver or not

122
bindings/power/supply/qcom/smb1351-charger.txt Normal file
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@ -0,0 +1,122 @@
Qualcomm Technologies, Inc. SMB1351 Charger Specific Bindings
SMB1351 is a single-cell battery charger. It can charge
the battery and power the system via the USB/AC adapter input.
The smb1351 interface is via I2C bus.
Required Properties:
- compatible Must be "qcom,smb1351-charger".
- reg The device 7-bit I2C address.
Required Properties for standalone charger:
- regulator-name A string used as a descriptive name for OTG regulator.
- pinctrl-names The state name of the pin configuration. Only
support "default".
- pinctrl-0 The phandle of the pin configuration node in
pinctrl for smb_int_pin.
Optional Properties:
- interrupts This indicates the IRQ number of the GPIO
connected to the STAT pin.
- qcom,fastchg-current-max-ma Fast Charging current in mA. Supported range is
from 1000mA to 4500mA.
- qcom,chg-autonomous-mode This is a bool property and it indicates that the
charger is configured for autonomous operation and
does not require any software configuration.
- qcom,disable-apsd This is a bool property which disables automatic
power source detection (APSD). If this is set
charger detection is done by DCIN UV irq.
- qcom,charging-disabled This is a bool property which disables charging
by suspending usb.
- qcom,batt-charging-disabled This is a bool property which disables battery
charging.
- qcom,using-pmic-therm This property indicates thermal pin connected to pmic or smb.
- qcom,bms-psy-name This is a string and it points to the bms
power supply name.
- qcom,iterm-ma Specifies the termination current to indicate end-of-charge.
Possible values in mA - 70, 100, 200, 300, 400, 500, 600, 700.
- qcom,iterm-disabled Disables the termination current feature. This is a bool
property.
- qcom,float-voltage-mv Float Voltage in mV - the maximum voltage up to which
the battery is charged. Supported range 3500mV to 4500mV
- qcom,recharge-mv Recharge threshold in mV - the offset from the float-volatge
as which the charger restarts charging. Possible
values are 50mV and 100mV.
- qcom,recharge-disabled Boolean value which disables the auto-recharge.
- qcom,bms-controlled-charging This property enables BMS to control EOC and
recharge. BMS and charger communicates with each
other via power_supply framework. This
property should be used with 'qcom,iterm-disabled'
to ensure EOC detection in charger is disabled.
- qcom,force-hvdcp-2p0 Boolean value which allows to force hvdcp working on 2.0 mode.
- qcom,parallel-charger Boolean value which enables the parallel charger.
- qcom,chg-vadc Corresponding VADC device's phandle.
- qcom,chg-adc_tm phandle to the corresponding VADC device to read the ADC channels.
- qcom,batt-cold-decidegc Cold battery temperature in decidegC.
- qcom,batt-hot-decidegc Hot battery temperature in decidegC.
- qcom,batt-missing-decidegc This is a property indicating battery missing temperature, if
higher than it, battery should exist.
- qcom,batt-warm-decidegc: Warm battery temperature in decidegC. After hitting this threshold,
"qcom,warm-bat-ma" defines maximum charging current and
"qcom,warm-bat-mv" defines maximum target voltage.
- qcom,batt-cool-decidegc: Cool battery temperature in decidegC. After hitting this threshold,
"qcom,cool-bat-ma" defines maximum charging current and
"qcom,cool-bat-mv" defines maximum target voltage.
- qcom,batt-warm-ma: Maximum warm battery charge current in milli-amps.
- qcom,batt-cool-ma: Maximum cool battery charge current in milli-amps.
- qcom,batt-warm-mv: Maximum warm battery target voltage in milli-volts.
- qcom,batt-cool-mv: Maximum cool battery target voltage in milli-volts.
- qcom,parallel-en-pin-polarity Specify the polarity of enable signal controlled
via pin in a parallel-charger configuration.
0 - Active low and 1 - Active high.
If not specified the default value is active-low.
- qcom,parallel-external-current-sense If present specifies external rsense is
used for charge current sensing.
- qcom,stacked-batfet: Boolean flag. Specifies if parallel charger has stacked BATFET
cofiguration.
- qcom,otg-enable: Boolean value which enables OTG(On-The-Go)
functionality.
Example for standalone charger:
&i2c_4 {
smb1351_otg_supply: smb1351-charger@57 {
compatible = "qcom,smb1351-charger";
reg = <0x57>;
interrupt-parent = <&msm_gpio>;
interrupts = <62 2>;
pinctrl-names = "default";
pinctrl-0 = <&smb_int_default>;
qcom,float-voltage-mv = <4350>;
qcom,iterm-ma = <100>;
qcom,recharge-mv = <100>;
qcom,bms-psy-name = "bms";
regulator-name = "smb1351_otg_vreg";
qcom,using-pmic-therm;
qcom,chg-adc_tm = <&pm8916_adc_tm>;
qcom,chg-vadc = <&pm8916_vadc>;
qcom,batt-hot-decidegc = <550>;
qcom,batt-cold-decidegc = <0>;
qcom,batt-missing-decidegc = <(-200)>;
qcom,batt-warm-decidegc = <500>;
qcom,batt-cool-decidegc = <50>;
qcom,batt-warm-ma = <350>;
qcom,batt-cool-ma = <350>;
qcom,batt-warm-mv = <4200>;
qcom,batt-cool-mv = <4200>;
};
};
Example for parallel charger:
&i2c_11 {
smb1351-charger@1d {
compatible = "qcom,smb1351-charger";
reg = <0x1d>;
qcom,parallel-charger;
qcom,float-voltage-mv = <4400>;
qcom,recharge-mv = <100>;
};
};

119
bindings/power/supply/qcom/smb1390-charger-psy.txt Normal file
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@ -0,0 +1,119 @@
Qualcomm Technologies, Inc. SMB1390 Charger Specific Bindings
SMB1390 charge pump is paired with QTI family of standalone chargers to
enable a high current, high efficiency Li+ battery charging system.
=======================
Required Node Structure
=======================
SMB1390 Charger must be described in two levels of device nodes.
==================================
First Level Node - SMB1390 Charger
==================================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,smb1390-charger-psy" for master SMB1390 and
"qcom,smb1390-slave" for slave SMB1390.
- qcom,pmic-revid
Usage: required
Value type: phandle
Definition: Should specify the phandle of SMB's revid module. This is used
to identify the SMB subtype.
- io-channels
- io-channel-names
Usage: required
Value type: <phandle>
Definition: For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,min-ilim-ua
Usage: optional
Value type: <u32>
Definition: Minimum ILIM supported, if requested ILIM goes below this value
disable SMB1390. If this values is not specified default minimum
ILIM is 1A.
- qcom,max-temp-alarm-degc
Usage: optional
Value type: <u32>
Definition: Maximum die temperature to trigger temp alarm. The value
must be one of the following:
80, 90, 105, 115.
If this value is not specified or is not one of the above
then default value is 105.
- qcom,max-cutoff-soc
Usage: optional
Value type: <u32>
Definition: SOC beyond which SMB1390 is kept disabled.
If this value is not specified then default value is 85%.
- qcom,parallel-output-mode
Usage: optional
Value type: <u32>
Definition: Defines the SMB1390 output connection topology.
This should be one of the following:
0 - If SMB1390 output is not connected to anything;
1 - If SMB1390 output is connected to VPH_PWR;
2 - If SMB1390 output is connected to VBATT.
If this value is not specified then default value is 1.
- qcom,parallel-input-mode
Usage: optional
Value type: <u32>
Definition: Defines the SMB1390 input connection topology.
This should be one of the following:
0 - If SMB1390 input is not connected to anything;
1 - If SMB1390 input is connected to USBIN;
3 - If SMB1390 input is connected to USBMID.
If this value is not specified then default value is 3.
================================================
Second Level Nodes - SMB1390 Charger Peripherals
================================================
Peripheral specific properties:
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names
Usage: required
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
=======
Example
=======
smb1390_charger: qcom,charge_pump {
compatible = "qcom,smb1390-charger-psy";
qcom,pmic-revid = <&smb1390_revid>;
interrupt-parent = <&smb1390>;
status = "disabled";
io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
io-channel-names = "cp_die_temp";
qcom,core {
interrupts = <0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x10 0x2 IRQ_TYPE_EDGE_RISING>,
<0x10 0x3 IRQ_TYPE_EDGE_RISING>,
<0x10 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "switcher-off-window",
"switcher-off-fault",
"vph-ov-soft",
"ilim",
"temp-alarm";
};
};

120
bindings/serial/msm_serial_hs.txt Normal file
View file

@ -0,0 +1,120 @@
* Qualcomm Technologies Inc, BLSP MSM HSUART
Required properties:
- compatible :
- "qcom,msm-hsuart-v14" to be used for UARTDM Core v1.4
- reg : offset and length of the register set for both the device,
uart core and bam core
- reg-names :
- "core_mem" to be used as name of the uart core
- "bam_mem" to be used as name of the bam core
- interrupts : interrupts for both the device,uart core and bam core
- interrupt-names :
- "core_irq" to be used as uart irq
- "bam irq" to be used as bam irq
- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
source. The type shall be a <u32> and the value shall be 1
- #address-cells: Specifies the number of cells needed to encode an address.
The type shall be <u32> and the value shall be 0
- interrupt-parent = It is needed for interrupt mapping
- bam-tx-ep-pipe-index : BAM TX Endpoint Pipe Index for HSUART
- bam-rx-ep-pipe-index : BAM RX Endpoint Pipe Index for HSUART
BLSP has a static pipe allocation and assumes a pair-pipe for each uart core.
Pipes [2*i : 2*i+1] are allocated for UART cores where i = [0 : 5].
Hence, Minimum and Maximum permitted value of endpoint pipe index to be used
with uart core is 0 and 11 respectively.
There is one HSUART block used in MSM devices,
"qcom,msm-hsuart-v14". The msm-serial-hs driver is
able to handle this, and matches against the "qcom,msm-hsuart-v14"
as the compatibility.
The registers for the "qcom,msm-hsuart-v14" device need to specify both
register blocks - uart core and bam core.
Example:
uart7: uart@f995d000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0xf995d000 0x1000>,
<0xf9944000 0x5000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq";
#address-cells = <0>;
interrupt-parent = <&uart7>;
interrupts = <0 1>;
#interrupt-cells = <1>;
interrupt-map = <0 &intc 0 113 0
1 &intc 0 239 0>
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
};
Optional properties:
- qcom,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" in
Documentation/devicetree/bindings/gpio/gpio.txt.
"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs
need to configured.
Gpio's are optional if it is required to be not configured by UART driver or
case where there is nothing connected and we want to use internal loopback mode
for uart.
- qcom, wakeup_irq : UART RX GPIO IRQ line to be configured as wakeup source.
- qcom,inject-rx-on-wakeup : inject_rx_on_wakeup enables feature where on
receiving interrupt with UART RX GPIO IRQ line (i.e. above wakeup_irq property),
HSUART driver injects provided character with property rx_to_inject.
- qcom, rx-char-to-inject : The character to be inserted on wakeup.
- qcom, no-suspend-delay : This decides system to go to suspend immediately
or not
- interconnects: pairs of phandles and interconnect provider specifier
to denote the edge source and destination ports of
the interconnect path. Please refer to
Documentation/devicetree/bindings/interconnect/
for more details.
- interconnect-names: List of interconnect path name strings sorted in the same
order as the interconnects property. Consumers drivers will use
interconnect-names to match interconnect paths with interconnect
specifiers. Please refer to Documentation/devicetree/bindings/
interconnect/ for more details.
Aliases :
An alias may be optionally used to bind the UART device to a TTY device
(ttyHS<alias_num>) with a given alias number. Aliases are of the form
uart<n> where <n> is an integer representing the alias number to use.
On systems with multiple UART devices present, an alias may optionally be
defined for such devices. The alias value should be from 0 to 255.
Example:
aliases {
uart4 = &uart7; // This device will be enumerated as ttyHS4
};
uart7: uart@f995d000 {
compatible = "qcom,msm-hsuart-v14"
reg = <0x19c40000 0x1000">,
<0xf9944000 0x5000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&uart7>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 113 0
1 &intc 0 239 0
2 &msmgpio 42 0>;
qcom,tx-gpio = <&msmgpio 41 0x00>;
qcom,rx-gpio = <&msmgpio 42 0x00>;
qcom,cts-gpio = <&msmgpio 43 0x00>;
qcom,rfr-gpio = <&msmgpio 44 0x00>;
qcom,inject-rx-on-wakeup = <1>;
qcom,rx-char-to-inject = <0xFD>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
};

89
bindings/sound/qcom-audio-dev.txt
View file

@ -2398,3 +2398,92 @@ Example:
};
};
Required properties:
- compatible : "qcom,spf-core-platform"
Required properties:
- compatible : "qcom,audio-pkt-core-platform"
Required properties:
- compatible : "qcom,swr-wcd"
Required properties:
- compatible : "qcom,tavil-i2c"
Required properties:
- compatible : "qcom,wcd-pinctrl"
Required properties:
- compatible : "qcom,gpr"
Required properties:
- compatible : "qcom,spf_core"
Required properties:
- compatible : "qcom,audio-pkt"
Required properties:
- compatible : "qcom,audio_prm"
* SDX ASoC Machine driver
Required properties:
- compatible : "qcom,sdx-asoc-snd-tavil"
- qcom,model : The user-visible name of this sound card.
- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations
- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations
- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations
- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations
- asoc-platform: This is phandle list containing the references to platform device
nodes that are used as part of the sound card dai-links.
- asoc-platform-names: This property contains list of platform names. The order of
the platform names should match to that of the phandle order
given in "asoc-platform".
- asoc-cpu: This is phandle list containing the references to cpu dai device nodes
that are used as part of the sound card dai-links.
- asoc-cpu-names: This property contains list of cpu dai names. The order of the
cpu dai names should match to that of the phandle order give
in "asoc-cpu". The cpu names are in the form of "%s.%d" form,
where the id (%d) field represents the back-end AFE port id that
this CPU dai is associated with.
Example:
sound-tavil {
compatible = "qcom,sdx-asoc-snd-tavil";
qcom,model = "sdx-tavil-i2s-snd-card";
qcom,prim_mi2s_aux_master = <&prim_master>;
qcom,prim_mi2s_aux_slave = <&prim_slave>;
qcom,sec_mi2s_aux_master = <&sec_master>;
qcom,sec_mi2s_aux_slave = <&sec_slave>;
asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>,
<&loopback>, <&hostless>, <&afe>, <&routing>,
<&pcm_dtmf>, <&host_pcm>, <&compress>;
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
"msm-voip-dsp", "msm-pcm-voice",
"msm-pcm-loopback", "msm-pcm-hostless",
"msm-pcm-afe", "msm-pcm-routing",
"msm-pcm-dtmf", "msm-voice-host-pcm",
"msm-compress-dsp";
asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>,
<&dtmf_tx>,
<&rx_capture_tx>, <&rx_playback_rx>,
<&tx_capture_tx>, <&tx_playback_rx>,
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
<&afe_proxy_tx>, <&incall_record_rx>,
<&incall_record_tx>, <&incall_music_rx>,
<&dai_sec_auxpcm>, <&incall2_record_rx>,
<&incall_music_2_rx>, <&incall_music_dl_rx>;
asoc-cpu-names = "msm-dai-q6-auxpcm.1",
"msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
"msm-dai-stub-dev.4", "msm-dai-stub-dev.5",
"msm-dai-stub-dev.6", "msm-dai-stub-dev.7",
"msm-dai-stub-dev.8", "msm-dai-q6-dev.224",
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
"msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769",
"msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774";
};

106
bindings/spi/spi_qsd.txt Normal file
View file

@ -0,0 +1,106 @@
Qualcomm Technologies, Inc. Serial Peripheral Interface (SPI)
Required properties:
- compatible : Should be "qcom,spi-qup-v2".
- reg : Offset and length of the register regions for the device
- reg-names : Register region names referenced in reg above.
Required register resource entries are:
"spi_physical" : Physical address of controller register blocks.
- interrupts : Interrupt numbers used by this controller
- interrupt-names : Interrupt resource names referenced in interrupts above.
Required interrupt resource entries are:
"spi_irq" : QUP-core interrupt.
- spi-max-frequency : Specifies maximum SPI clock frequency, Units - Hz.
Required alias:
- The desired bus-number is specified via an alias with the following format
'spi{n}' where n is the bus number.
Optional properties:
- qcom,gpio-mosi : GPIO pin number of the MOSI bus line.
- qcom,gpio-miso : GPIO pin number of the MISO bus line.
- qcom,gpio-clk : GPIO pin number of the CLK bus line.
- qcom,gpio-cs0 : GPIO pin number of the chipselect0 bus line.
- qcom,gpio-cs1 : GPIO pin number of the chipselect1 bus line.
- qcom,gpio-cs2 : GPIO pin number of the chipselect2 bus line.
- qcom,gpio-cs3 : GPIO pin number of the chipselect3 bus line.
- qcom,infinite-mode: When missing or set to zero, QUP uses infinite-mode. When
value is non-zero, the value is the number of words in maximum transfer
length.
- qcom,active-only : Vote for core clock when the application processor goes
to active state and remove that vote when it goes to idle state. This flag may
improve service time of first spi request at the expense of power consumption.
When this entry is not present, voting is done by the runtime-pm callbacks.
- qcom,master-id : Master endpoint number used for voting on clocks using the
bus-scaling driver.
- qcom,rt-priority : whether spi message queue is set to run as a realtime task.
With this spi transaction message pump with high (realtime) priority to reduce
the transfer latency on the bus by minimising the delay between a transfer request
- qcom,shared : whether this qup is shared with other ee's
Optional properties which are required for support of BAM-mode:
- qcom,ver-reg-exists : Boolean. When present, allows driver to verify if HW
version support latest features (e.g. BAM) and then enable them. Should be
removed for legacy HW.
- qcom,use-bam : Boolean. When present, enables BAM-mode.
- qcom,use-pinctrl : Boolean. When present, enables pinctrl frame work to configure GPIO's
instead of existing gpio mux hence gpio entries are no more required if present.
- pinctrl-names : Property must contain "spi_default" and "spi_sleep" if
pinctrl is to be used.
instead of existing gpio mux hence gpio entries are no more required if present.
- qcom,bam-consumer-pipe-index : BAM consumer-pipe index.
- qcom,bam-producer-pipe-index : BAM producer-pipe index.
- reg-names : register region names referenced in reg.
Required register resource for BAM are:
"spi_bam_physical" : Physical address of BAM for this controller.
- interrupt-names : interrupt resource names referenced in interrupts.
Required interrupt resource from BAM are:
"spi_bam_irq" : BAM interrupt used by the controller.
Optional SPI slave nodes must be children of the SPI master node and contain
the following properties.
- reg: (required) chip-select address of the device.
- compatible : (required) Name of SPI device following generic names.
- spi-max-frequency : (required) Maximum SPI clocking speed of device in Hz
- interrupts : (recommended) Should contain the SPI slave interrupt number
encoded depending on the type of the interrupt controller.
- interrupt-parent : (recommended) The phandle for the interrupt controller
that services interrupts for this device.
- spi-cpol : (optional) Empty property indicating device requires inverse
clock polarity (CPOL) mode
- spi-cpha : (optional) Empty property indicating device requires shifted
clock phase (CPHA) mode
- spi-cs-high : (optional) Empty property indicating device requires
chip select active high
Example:
aliases {
spi0 = &spi_0;
};
spi_0: spi@f9923000 {
compatible = "qcom,spi-qup-v2";
reg-names = "spi_physical", "spi_bam_physical";
reg = <0xf9923000 0x1000>,
<0xf9904000 0x10000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 95 0>, <0 238 0>;
spi-max-frequency = <19200000>;
#address-cells = <1>;
#size-cells = <0>;
qcom,gpio-mosi = <&msmgpio 0 0>;
qcom,gpio-miso = <&msmgpio 1 0>;
qcom,gpio-clk = <&msmgpio 3 0>;
qcom,gpio-cs2 = <&msmgpio 9 0>;
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,bam-consumer-pipe-index = <12>;
qcom,bam-producer-pipe-index = <13>;
qcom,ver-reg-exists;
qcom,master-id = <86>;
qcom,rt-priority;
};

4
bindings/thermal/qti-qmi-cdev.txt
View file

@ -41,6 +41,9 @@ Subsystem properties:
"modem" -> for processor passive cooling device,
"modem_current" -> for current limiting device,
"modem_bw" -> for bus bandwidth limiting device,
"modem_bw_backoff" -> for bus bandwidth limit device with
absolute bandwidth reduction from max bandwidth
in 100mbbs resolution,
"vbatt_low" -> BCL vbat mitigation device,
"mmw0" -> Millimeter wave limiting device 0,
"mmw1" -> Millimeter wave limiting device 1,
@ -53,6 +56,7 @@ Subsystem properties:
"mmw_skin3" -> MMW skin mitigation device3,
"cpr_cold" -> for cpr restriction,
"wlan" -> for modem wlan mitigation device,
"wlan_bw" -> for bus bandwidth limiting device,
"cdsp_sw" -> for CDSP DCVS mitigation device,
"cdsp_hw" -> for CDSP hardware mitigation device,
"mmw_skin0_dsc" -> DSC based MMW skin mitigation

1
bindings/thermal/qti-qmi-sensor.txt
View file

@ -61,6 +61,7 @@ Subsystem properties:
28. mmw_pa2
29. mmw_pa3
30. sdr_mmw_therm
31. msm_skin_therm
Example:

29
qcom/Makefile
View file

@ -75,6 +75,12 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \
lahaina-mtp-v2.1.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SCUBA) += scuba-iot-idp-overlay.dtbo
scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
holi-mtp-overlay.dtbo \
@ -104,22 +110,28 @@ endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SHIMA) += \
shima-rumi-overlay.dtbo \
shima-idp-overlay.dtbo \
shima-idp-overlay.dtbo \
shima-idp-120fps-overlay.dtbo \
shima-atp-overlay.dtbo \
shima-qrd-overlay.dtbo \
shima-idps-digital-mics-overlay.dtbo
shima-idps-digital-mics-overlay.dtbo \
shima-idps-digital-mics-120fps-overlay.dtbo
shima-rumi-overlay.dtbo-base := shima.dtb
shima-idp-overlay.dtbo-base := shima.dtb
shima-idp-120fps-overlay.dtbo-base := shima.dtb
shima-atp-overlay.dtbo-base := shima.dtb
shima-qrd-overlay.dtbo-base := shima.dtb
shima-idps-digital-mics-overlay.dtbo-base := shima.dtb
shima-idps-digital-mics-120fps-overlay.dtbo-base := shima.dtb
else
dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \
shima-idp.dtb \
shima-idp-120fps.dtb \
shima-atp.dtb \
shima-qrd.dtb \
shima-idps-digital-mics.dtb
shima-idps-digital-mics.dtb \
shima-idps-digital-mics-120fps.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
@ -165,7 +177,16 @@ endif
dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \
sdxlemur-cdp.dtb \
sdxlemur-mtp.dtb
sdxlemur-mtp.dtb \
sdxlemur-mtp-mbb.dtb \
sdxlemur-mtp-cpe.dtb \
sdxlemur-mtp-mbb-ntn3-pcie.dtb \
sdxlemur-mtp-mbb-pcie-ep.dtb \
sdxlemur-mtp-mbb-pcie-rc-ep.dtb \
sdxlemur-mtp-mbb.dtb \
sdxlemur-rcm-pcie-ep.dtb \
sdxlemur-rcm-rc.dtb
ifeq ($(CONFIG_ARCH_SHIMA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)

4
qcom/holi-cdp-lcd.dtsi
View file

@ -47,6 +47,8 @@
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
panel = <&dsi_sharp_qsync_fhd_video>;
panel = <&dsi_sharp_qsync_fhd_video
&dsi_sharp_qsync_fhd_cmd
&dsi_sharp_qsync_fhd_60hz_cmd>;
};
};

8
qcom/holi-mtp-usbc.dtsi
View file

@ -95,7 +95,7 @@
};
&holi_snd {
qcom,model = "holi-mtp-usbc-snd-card";
qcom,model = "holi-usbc-snd-card";
qcom,msm-mbhc-usbc-audio-supported = <1>;
qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>;
@ -236,9 +236,9 @@
"cycle_count",
"charge_full_design",
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_parallel_mode",
"cp_parallel_output_mode",
"cp_min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",

6
qcom/holi-mtp.dtsi
View file

@ -217,9 +217,9 @@
"cycle_count",
"charge_full_design",
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_parallel_mode",
"cp_parallel_output_mode",
"cp_min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",

2
qcom/holi-pmic-overlay.dtsi
View file

@ -482,7 +482,7 @@
reg = <0x4300>;
regulator-name = "pm8008_l4";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-max-microvolt = <2880000>;
qcom,min-dropout-voltage = <160000>;
qcom,hpm-min-load = <10000>;
};

10
qcom/holi-qrd.dtsi
View file

@ -294,9 +294,9 @@
"cycle_count",
"charge_full_design",
"time_to_full_now",
"parallel_mode",
"parallel_output_mode",
"min_icl",
"cp_parallel_mode",
"cp_parallel_output_mode",
"cp_min_icl",
"cp_switcher_en",
"cp_enable",
"cp_ilim",
@ -414,7 +414,7 @@
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x15 0x198 /* PLL_BIAS_CONTROL_2 */
0x17 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
@ -435,7 +435,7 @@
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x15 0x198 /* PLL_BIAS_CONTROL_2 */
0x17 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */

92
qcom/holi-thermal-modem.dtsi
View file

@ -20,8 +20,8 @@
#cooling-cells = <2>;
};
modem_bw: modem_bw {
qcom,qmi-dev-name = "modem_bw";
modem_bw_backoff: modem_bw_backoff {
qcom,qmi-dev-name = "modem_bw_backoff";
#cooling-cells = <2>;
};
@ -127,9 +127,16 @@
"qfe_wtr_pa1",
"qfe_wtr_pa2",
"qfe_wtr_pa3",
"sys_therm1",
"sys_therm2",
"modem_tsens1";
"modem_tsens1",
"beamer_n_therm",
"beamer_e_therm",
"beamer_w_therm",
"qfe_ret_pa0_fr1",
"qfe_wtr_pa0_fr1",
"qfe_wtr_pa1_fr1",
"qfe_wtr_pa2_fr1",
"qfe_wtr_pa3_fr1",
"qfe_wtr0_fr1";
};
};
};
@ -240,36 +247,6 @@
};
};
modem-wifi-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-ambient-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
@ -374,4 +351,49 @@
};
};
};
beamer-n-therm-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BEAMER_N_THERM)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
beamer-e-therm-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BEAMER_E_THERM)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
beamer-w-therm-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BEAMER_W_THERM)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

3
qcom/holi-usb.dtsi
View file

@ -47,6 +47,7 @@
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,pm-qos-latency = <61>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
@ -66,8 +67,6 @@
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;

37
qcom/holi.dtsi
View file

@ -448,7 +448,7 @@
};
chosen {
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1";
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1 kpti=off";
};
};
@ -1786,6 +1786,18 @@
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
};
};
@ -2170,6 +2182,8 @@
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
@ -2177,6 +2191,10 @@
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
@ -2556,7 +2574,7 @@
vdd-1.3-rfa-supply = <&L2E>;
vdd-3.3-ch1-supply = <&L11E>;
vdd-3.3-ch0-supply = <&L10E>;
qcom,vdd-cx-mx-config = <0 0>;
qcom,vdd-cx-mx-config = <640000 640000>;
qcom,vdd-3.3-ch1-config = <3000000 3312000>;
qcom,vdd-3.3-ch0-config = <3000000 3312000>;
qcom,smp2p_map_wlan_1_in {
@ -2719,6 +2737,21 @@
reg = <0x6028 0x4>;
};
};
qfprom_sys: qfprom@0 {
compatible = "qcom,qfprom-sys";
nvmem-cells = <&gpu_speed_bin>,
<&adsp_variant>,
<&feat_conf8>,
<&gpu_gaming_bin>,
<&feat_conf9>;
nvmem-cell-names = "gpu_speed_bin",
"adsp_variant",
"feat_conf8",
"gpu_gaming_bin",
"feat_conf9";
};
};
#include "holi-gpu.dtsi"

5
qcom/lahaina-audio-overlay.dtsi
View file

@ -72,6 +72,11 @@
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <5>;
qcom,swr-phy-dev-addr = <0x0D 0x01170223>,
<0x08 0x58350223>,
<0x08 0x58350222>,
<0x08 0x58350221>,
<0x08 0x58350220>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
wcd938x_tx_slave: wcd938x-tx-slave {

1
qcom/lahaina-cdp.dtsi
View file

@ -189,7 +189,6 @@
vcc-supply = <&pm8350_l7>;
vcc-voltage-level = <2504000 2950000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
vccq-supply = <&pm8350_l9>;

1
qcom/lahaina-mtp.dtsi
View file

@ -144,7 +144,6 @@
vcc-supply = <&pm8350_l7>;
vcc-voltage-level = <2504000 2950000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
vccq-supply = <&pm8350_l9>;

1
qcom/lahaina-qrd-common.dtsi
View file

@ -24,7 +24,6 @@
vcc-supply = <&pm8350_l7>;
vcc-voltage-level = <2504000 2950000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
vccq-supply = <&pm8350_l9>;

6
qcom/lahaina-usb.dtsi
View file

@ -1,5 +1,6 @@
#include <dt-bindings/clock/qcom,gcc-lahaina.h>
#include <dt-bindings/phy/qcom,lahaina-qmp-usb3.h>
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-combo.h>
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
&soc {
usb0: ssusb@a600000 {
@ -177,7 +178,8 @@
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_CLAMP_ENABLE>;
USB3_DP_PCS_CLAMP_ENABLE
USB3_DP_COM_TYPEC_STATUS>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */

5
qcom/lahaina-v2.dtsi
View file

@ -22,6 +22,11 @@
dynamic-power-coefficient = <760>;
};
&kryo_erp {
/delete-property/ qcom,disable-panic-on-ce;
};
&sde_dp {
/delete-node/ qcom,pll-supply-entries;
};

9
qcom/lahaina-vm.dtsi
View file

@ -167,6 +167,15 @@
qcom,label = <0x0000001>;
};
display-message-queue-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/display-msgq-pair";
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
peer-default;
qcom,label = <0x0000002>;
};
neuron-ch1-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/neuron-ch1-shm";

10
qcom/lahaina.dtsi
View file

@ -3237,11 +3237,12 @@
};
};
kryo-erp {
kryo_erp: erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
qcom,disable-panic-on-ce;
};
tcsr_mutex_block: syscon@1f40000 {
@ -4336,7 +4337,7 @@
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <60>;
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
@ -4422,6 +4423,8 @@
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,firmware-name = "modem";
memory-region = <&pil_modem_mem>;
qcom,proxy-timeout-ms = <10000>;
@ -4630,6 +4633,7 @@
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,ipa-uc-holb-monitor;
qcom,gsi_wdi_db_polling;
qcom,ipa-holb-monitor-poll-period = <5>;
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
@ -5352,6 +5356,7 @@
<0xb2e5510 0x690>;
reg-names = "smmu_iova_ipa", "tcs_cmd";
wlan-en-gpio = <&tlmm 64 0>;
qcom,bt-en-gpio = <&tlmm 65 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
@ -5615,6 +5620,7 @@
/* offset=(0xC8*6) + (0x10*2) */
qcom,tcs_offset_ipa = <0x4D0>;
qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */
qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */
qcom,bt-vdd-aon-supply = <&S11B>;
qcom,bt-vdd-dig-supply = <&S11B>;

198
qcom/msm-arm-smmu-scuba.dtsi Normal file
View file

@ -0,0 +1,198 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@0x59a0000 {
status = "disabled";
compatible = "qcom,qsmmu-v500";
reg = <0x59a0000 0x10000>,
<0x59c2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,no-dynamic-asid;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
qcom,regulator-names = "vdd";
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
qcom,actlr =
/* ALL CBs of GFX: +15 deep PF */
<0x0 0x3ff 0x30B>;
gfx_0_tbu: gfx_0_tbu@0x59c5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x59c5000 0x1000>,
<0x59c2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
};
};
apps_smmu: apps-smmu@0xc600000 {
status = "disabled";
compatible = "qcom,qsmmu-v500";
reg = <0xc600000 0x80000>,
<0xc782000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,actlr =
/* For rt TBU +3 deep PF */
<0x400 0x3ff 0x103>,
/* For nrt TBU +3 deep PF */
<0x800 0x3ff 0x103>;
anoc_1_tbu: anoc_1_tbu@0xc785000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc785000 0x1000>,
<0xc782200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
mm_rt_tbu: mm_rt_tbu@0xc789000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc789000 0x1000>,
<0xc782208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
qcom,regulator-names = "vdd";
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0xc78d000 0x1000>,
<0xc782210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
qcom,regulator-names = "vdd";
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <2>;
};
};
kgsl_iommu_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&kgsl_smmu 0x7 0x0>;
status = "disabled";
};
apps_iommu_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&apps_smmu 0x1E0 0x0>;
status = "disabled";
};
apps_iommu_coherent_test_device {
compatible = "iommu-debug-test";
qcom,iommu-dma = "disabled";
iommus = <&apps_smmu 0x1E1 0x0>;
dma-coherent;
status = "disabled";
};
};

439
qcom/pm2250-rpm-regulator.dtsi Normal file
View file

@ -0,0 +1,439 @@
&rpm_bus {
rpm-regulator-smpa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s1";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <2>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <3>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s3";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-smpa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <4>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
status = "disabled";
regulator-s4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s4";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <1>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <2>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l2";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa3 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <3>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l3";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa4 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <4>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l4";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa5 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <5>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l5 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l5";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa6 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <6>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l6 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l6";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa7 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <7>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l7 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l7";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa8 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <8>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l8 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l8";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa9 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <9>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l9 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l9";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa10 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <10>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l10 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l10";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa11 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <11>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l11 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l11";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa12 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <12>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l12 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l12";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa13 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <13>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l13 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l13";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa14 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <14>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l14 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l14";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa15 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <15>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l15 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l15";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa16 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <16>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l16 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l16";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa17 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <17>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l17 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l17";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa18 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <18>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l18 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l18";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa19 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <19>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l19 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l19";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa20 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <20>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l20 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l20";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa21 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <21>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l21 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l21";
qcom,set = <3>;
status = "disabled";
};
};
rpm-regulator-ldoa22 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <22>;
qcom,regulator-type = <0>;
qcom,regulator-hw-type = "pmic5-ldo";
qcom,hpm-min-load = <10000>;
status = "disabled";
regulator-l22 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l22";
qcom,set = <3>;
status = "disabled";
};
};
};

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#include <dt-bindings/input/input.h>
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm2250@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
pm2250_revid: qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100 0x100>;
};
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800 0x100>;
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,pon-dbc-delay = <15625>;
qcom,kpdpwr-sw-debounce;
qcom,system-reset;
qcom,store-hard-reset-reason;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
qcom,pull-up = <1>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
qcom,pull-up = <1>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
pm2250_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400 0x100>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pm2250_vadc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
qcom,temperature-threshold-set = <1>;
};
pm2250_vadc: vadc@3100 {
compatible = "qcom,spmi-adc5-lite";
reg = <0x3100 0x100>;
reg-names = "adc5-usr-base";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>;
io-channel-ranges;
/* Channel nodes */
ref_gnd {
reg = <ADC5_REF_GND>;
label = "ref_gnd";
qcom,pre-scaling = <1 1>;
};
vref_1p25 {
reg = <ADC5_1P25VREF>;
label = "vref_1p25";
qcom,pre-scaling = <1 1>;
};
die_temp {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
qcom,pre-scaling = <1 1>;
};
vph_pwr {
reg = <ADC5_VPH_PWR>;
label = "vph_pwr";
qcom,pre-scaling = <1 3>;
};
vbat_sns {
reg = <ADC5_VBAT_SNS>;
label = "vbat_sns";
qcom,pre-scaling = <1 3>;
};
usb_in_v_div_16 {
reg = <ADC5_USB_IN_V_16>;
label = "usb_in_v_div_16";
qcom,pre-scaling = <1 16>;
};
chg_temp {
reg = <ADC5_CHG_TEMP>;
label = "chg_temp";
qcom,pre-scaling = <1 1>;
};
bat_therm {
reg = <ADC5_BAT_THERM_100K_PU>;
label = "bat_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_30k {
reg = <ADC5_BAT_THERM_30K_PU>;
label = "bat_therm_30k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_400k {
reg = <ADC5_BAT_THERM_400K_PU>;
label = "bat_therm_400k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
i_parallel {
reg = <ADC5_PARALLEL_ISENSE>;
label = "i_parallel";
qcom,pre-scaling = <1 1>;
};
bat_id {
reg = <ADC5_BAT_ID_100K_PU>;
label = "bat_id";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
pm2250_gpios: pinctrl@c000 {
compatible = "qcom,spmi-gpio";
reg = <0xc000 0xa00>;
interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
<0x0 0xc1 0 IRQ_TYPE_NONE>,
<0x0 0xc2 0 IRQ_TYPE_NONE>,
<0x0 0xc3 0 IRQ_TYPE_NONE>,
<0x0 0xc4 0 IRQ_TYPE_NONE>,
<0x0 0xc5 0 IRQ_TYPE_NONE>,
<0x0 0xc6 0 IRQ_TYPE_NONE>,
<0x0 0xc7 0 IRQ_TYPE_NONE>,
<0x0 0xc8 0 IRQ_TYPE_NONE>,
<0x0 0xc9 0 IRQ_TYPE_NONE>;
interrupt-names = "pm2250_gpio1", "pm2250_gpio2",
"pm2250_gpio3", "pm2250_gpio4",
"pm2250_gpio5", "pm2250_gpio6",
"pm2250_gpio7", "pm2250_gpio8",
"pm2250_gpio9", "pm2250_gpio10";
gpio-controller;
#gpio-cells = <2>;
};
pm2250_rtc: qcom,pm2250_rtc {
compatible = "qcom,pm8941-rtc";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
};
pm2250_qg: qpnp,qg {
compatible = "qcom,qpnp-qg-lite";
#address-cells = <1>;
#size-cells = <1>;
qcom,vbatt-cutoff-mv = <3400>;
qcom,vbatt-low-mv = <3500>;
qcom,vbatt-low-cold-mv = <3800>;
qcom,vbatt-empty-mv = <3200>;
qcom,vbatt-empty-cold-mv = <3000>;
qcom,s3-entry-fifo-length = <2>;
qcom,pmic-revid = <&pm2250_revid>;
io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>,
<&pm2250_vadc ADC5_BAT_ID_100K_PU>;
io-channel-names = "batt-therm", "batt-id";
qcom,qgauge@4800 {
status = "okay";
reg = <0x4800 0x100>;
interrupts =
<0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "qg-vbat-empty",
"qg-fifo-done",
"qg-good-ocv";
};
qcom,qg-sdam@b600 {
status = "okay";
reg = <0xb600 0x100>;
};
};
pm2250_charger: qcom,qpnp-smblite {
compatible = "qcom,qpnp-smblite";
#address-cells = <1>;
#size-cells = <1>;
#cooling-cells = <2>;
qcom,pmic-revid = <&pm2250_revid>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts =
<0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chgr-error",
"chg-state-change",
"buck-oc",
"vph-ov";
};
qcom,dcdc@1100 {
reg = <0x1100 0x100>;
interrupts =
<0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "otg-fail",
"otg-fault",
"skip-mode",
"input-current-limiting",
"switcher-power-ok";
};
qcom,batif@1200 {
reg = <0x1200 0x100>;
interrupts =
<0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "bat-temp",
"bat-therm-or-id-missing",
"bat-low",
"bat-ov",
"bsm-active";
};
qcom,usb@1300 {
reg = <0x1300 0x100>;
interrupts =
<0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usbin-plugin",
"usbin-collapse",
"usbin-uv",
"usbin-ov",
"usbin-gtvt",
"usbin-icl-change";
};
qcom,typec@1500 {
reg = <0x1500 0x100>;
interrupts =
<0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "typec-or-rid-detect-change",
"typec-vpd-detect",
"typec-cc-state-change",
"typec-vbus-change",
"typec-attach-detach",
"typec-legacy-cable-detect",
"typec-try-snk-src-detect";
};
qcom,misc@1600 {
reg = <0x1600 0x100>;
interrupts =
<0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"imp-trigger",
"all-chnl-cond-done",
"temp-change";
};
qcom,schgm-flashlite@a600 {
reg = <0xa600 0x100>;
interrupts =
<0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "flash-state-change",
"ilim1-s1",
"ilim2-s2",
"vreg-ok";
};
};
};
pm2250_1: qcom,pm2250@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
pm2250_vib: qcom,vibrator@5600 {
compatible = "qcom,qpnp-vibrator-ldo";
reg = <0x5600 0x100>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
};
pm2250_pwm1: qcom,pwms@bc00 {
compatible = "qcom,pwm-lpg";
reg = <0xbc00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm2250_pwm2: qcom,pwms@bd00 {
compatible = "qcom,pwm-lpg";
reg = <0xbd00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm2250_pwm3: qcom,pwms@be00 {
compatible = "qcom,pwm-lpg";
reg = <0xbe00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
};
};

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&soc {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
system_heap: qcom,ion-heap@25 {
reg = <25>;
qcom,ion-heap-type = "SYSTEM";
};
system_secure_heap: qcom,ion-heap@9 {
reg = <9>;
qcom,ion-heap-type = "SYSTEM_SECURE";
};
qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
reg = <10>;
memory-region = <&secure_display_memory>;
qcom,ion-heap-type = "HYP_CMA";
};
qcom,ion-heap@27 { /* QSEECOM HEAP */
reg = <27>;
memory-region = <&qseecom_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@19 { /* QSEECOM HEAP */
reg = <19>;
memory-region = <&qseecom_ta_mem>;
qcom,ion-heap-type = "DMA";
};
};
};

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/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "scuba-iot-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Scuba IDP";
compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
qcom,msm-id = <441 0x10000>, <471 0x10000>;
qcom,board-id = <34 0>;
};

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#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&soc {
scuba_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
#include "qg-batterydata-alium-3600mah.dtsi"
#include "qg-batterydata-atl466271_3300mAh.dtsi"
};
};
&pm2250_qg {
qcom,battery-data = <&scuba_batterydata>;
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
qcom,tcss-enable;
qcom,fvss-enable;
qcom,fvss-vbatt-mv = <3500>;
qcom,bass-enable;
};
&pm2250_charger {
interrupts-extended = <&tlmm 89 0>;
interrupt-names = "usb_id_irq";
qcom,usb-id-gpio = <&tlmm 89 0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_interrupt>;
qcom,auto-recharge-soc = <98>;
qcom,suspend-input-on-debug-batt;
qcom,battery-data = <&scuba_batterydata>;
io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>,
<&pm2250_vadc ADC5_CHG_TEMP>;
io-channel-names = "usb_in_voltage",
"chg_temp";
qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
};

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/dts-v1/;
#include "scuba-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Scuba IOT SoC";
compatible = "qcom,scuba-iot";
qcom,board-id = <0 0>;
};

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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm Technologies, Inc. SCUBA";
compatible = "qcom,scuba";
qcom,msm-id = <441 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_1: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_2: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_3: l1-dcache {
compatible = "arm,arch-cache";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_region: hyp_region@45700000 {
no-map;
reg = <0x0 0x45700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@45e00000 {
no-map;
reg = <0x0 0x45e00000 0x0 0x100000>;
};
sec_apps_mem: sec_apps_region@45fff000 {
no-map;
reg = <0x0 0x45fff000 0x0 0x1000>;
};
smem_region: smem@46000000 {
no-map;
reg = <0x0 0x46000000 0x0 0x200000>;
};
pil_modem_mem: modem_region@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x6900000>;
};
pil_video_mem: pil_video_region@51400000 {
no-map;
reg = <0x0 0x51400000 0x0 0x500000>;
};
wlan_msa_mem: wlan_msa_region@51900000 {
no-map;
reg = <0x0 0x51900000 0x0 0x100000>;
};
pil_adsp_mem: adsp_regions@51a00000 {
no-map;
reg = <0x0 0x51a00000 0x0 0x1c00000>;
};
pil_ipa_fw_mem: ips_fw_region@53600000 {
no-map;
reg = <0x0 0x53600000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi_region@53610000 {
no-map;
reg = <0x0 0x53610000 0x0 0x5000>;
};
pil_gpu_mem: gpu_region@53615000 {
no-map;
reg = <0x0 0x53615000 0x0 0x2000>;
};
removed_region: removed_region@60000000 {
no-map;
reg = <0x0 0x60000000 0x0 0x3900000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x800000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x800000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x5c00000>;
};
cont_splash_memory: cont_splash_region@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@5cf00000 {
reg = <0x0 0x5cf00000 0x0 0x0100000>;
label = "dfps_data_region";
};
disp_rdump_memory: disp_rdump_region@5c000000 {
reg = <0x0 0x5c000000 0x0 0x00f00000>;
label = "disp_rdump_region";
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
};
chosen {
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0xf200000 0x10000>, /* GICD */
<0xf300000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@f120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf120000 0x1000>;
clock-frequency = <19200000>;
frame@f121000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0xf121000 0x1000>,
<0xf122000 0x1000>;
};
frame@f123000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0xf123000 0x1000>;
status = "disabled";
};
frame@f124000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0xf124000 0x1000>;
status = "disabled";
};
frame@f125000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0xf125000 0x1000>;
status = "disabled";
};
frame@f126000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0xf126000 0x1000>;
status = "disabled";
};
frame@f127000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0xf127000 0x1000>;
status = "disabled";
};
frame@f128000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0xf128000 0x1000>;
status = "disabled";
};
};
qcom,msm-imem@c125000 {
compatible = "qcom,msm-imem";
reg = <0xc125000 0x1000>;
ranges = <0x0 0xc125000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
restart@440b000 {
compatible = "qcom,pshold";
reg = <0x440b000 0x4>,
<0x03d3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
status="disabled";
};
qcom,mpm2-sleep-counter@4403000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4403000 0x1000>;
clock-frequency = <32768>;
status="disabled";
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
status="disabled";
};
qcom,chd_silver {
compatible = "qcom,core-hang-detect";
label = "silver";
qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
0x0f1a80b0 0x0f1b80b0>;
qcom,config-arr = <0x0f1880b8 0x0f1980b8
0x0f1a80b8 0x0f1b80b8>;
status="disabled";
};
qfprom: qfprom@1b40000 {
compatible = "qcom,qfprom";
reg = <0x1b40000 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
status="disabled";
feat_conf5: feat_conf5@6018 {
reg = <0x6018 0x4>;
};
};
wdog: qcom,wdt@f017000 {
compatible = "qcom,msm-watchdog";
reg = <0xf017000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
status = "disabled";
};
dcc: dcc_v2@1be2000 {
compatible = "qcom,dcc-v2";
reg = <0x1be2000 0x1000>,
<0x1bee000 0x2000>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x2000>;
status = "disabled";
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c1_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c2_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c3_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
l1_icache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x60>;
};
l1_icache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x61>;
};
l1_icache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x62>;
};
l1_icache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x63>;
};
l1_dcache0 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x80>;
};
l1_dcache1 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x81>;
};
l1_dcache2 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x82>;
};
l1_dcache3 {
qcom,dump-size = <0x9040>;
qcom,dump-id = <0x83>;
};
l2_tlb0 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x120>;
};
l2_tlb1 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x121>;
};
l2_tlb2 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x122>;
};
l2_tlb3 {
qcom,dump-size = <0x2000>;
qcom,dump-id = <0x123>;
};
};
spmi_bus: qcom,spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x1c40000 0x1100>,
<0x1e00000 0x2000000>,
<0x3e00000 0x100000>,
<0x3f00000 0xa0000>,
<0x1c0a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
};
#include "pm2250.dtsi"
#include "pm2250-rpm-regulator.dtsi"
#include "scuba-regulator.dtsi"
#include "scuba-iot-pinctrl.dtsi"
#include "scuba-ion.dtsi"
#include "msm-arm-smmu-scuba.dtsi"
&pm2250_vadc {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&conn_therm_default &skin_therm_default>;
xo_therm {
reg = <ADC5_XO_THERM_100K_PU>;
label = "xo_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pa_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "pa_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
quiet_therm {
reg = <ADC5_AMUX_THM2_100K_PU>;
label = "quiet_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
msm_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "msm_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
label = "skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
conn_therm {
reg = <ADC5_GPIO4_100K_PU>;
label = "conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pm2250_gpios {
skin_therm {
skin_therm_default: skin_therm_default {
pins = "gpio5";
bias-high-impedance;
};
};
conn_therm {
conn_therm_default: conn_therm_default {
pins = "gpio6";
bias-high-impedance;
};
};
};
&spmi_bus {
qcom,pm2250@0 {
pm2250_adc_tm_iio: adc_tm@3400 {
compatible = "qcom,adc-tm5-iio";
reg = <0x3400 0x100>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM2_100K_PU>,
<&pm2250_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm2250_vadc ADC5_GPIO3_100K_PU>,
<&pm2250_vadc ADC5_GPIO4_100K_PU>,
<&pm2250_vadc ADC5_SBUx>;
xo_therm {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pa_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
quiet_therm {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
msm_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
conn_therm {
reg = <ADC5_GPIO4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
s3_die_temp {
reg = <ADC5_SBUx>;
};
};
};
};

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#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
&rpm_bus {
/* PM2250 S2 - VDD_CX supply */
rpm-regulator-smpa2 {
status = "okay";
qcom,resource-name = "rwcx";
qcom,resource-id = <0>;
VDD_CX_LEVEL:
VDD_GFX_LEVEL:
VDD_MSS_LEVEL:
S2A_LEVEL: pm2250_s2_level: regulator-s2-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
VDD_CX_FLOOR_LEVEL:
VDD_MSS_FLOOR_LEVEL:
S2A_FLOOR_LEVEL:
pm2250_s2_floor_level: regulator-s2-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
VDD_CX_LEVEL_AO:
VDD_MSS_LEVEL_AO:
S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_s2_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
/* PM2250 L1 - VDD_MX/WCSS_MX supply */
rpm-regulator-ldoa1 {
status = "okay";
qcom,resource-name = "rwmx";
qcom,resource-id = <0>;
VDD_MX_LEVEL:
L1A_LEVEL: pm2250_l1_level: regulator-l1-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
VDD_MX_FLOOR_LEVEL:
L1A_FLOOR_LEVEL:
pm2250_l1_floor_level: regulator-l1-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
VDD_MX_LEVEL_AO:
L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l1_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
rpm-regulator-smpa3 {
status = "okay";
S3A: pm2250_s3: regulator-s3 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1662500>;
qcom,init-voltage = <400000>;
status = "okay";
};
};
rpm-regulator-smpa4 {
status = "okay";
S4A: pm2250_s4: regulator-s4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2350000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
/* VDD_LPI_CX supply */
rpm-regulator-ldoa8 {
status = "okay";
qcom,resource-name = "rwlc";
qcom,resource-id = <0>;
VDD_LPI_CX_LEVEL:
L8A_LEVEL: pm2250_l8_level: regulator-l8-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l8_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
/* VDD_LPI_MX supply */
rpm-regulator-ldoa9 {
status = "okay";
qcom,resource-name = "rwlm";
qcom,resource-id = <0>;
VDD_LPI_MX_LEVEL:
L9A_LEVEL: pm2250_l9_level: regulator-l9-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm2250_l9_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_BINNING>;
qcom,use-voltage-level;
};
};
rpm-regulator-ldoa2 {
status = "okay";
L2A: pm2250_l2: regulator-l2 {
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1300000>;
qcom,init-voltage = <1060000>;
status = "okay";
};
};
rpm-regulator-ldoa3 {
status = "okay";
L3A: pm2250_l3: regulator-l3 {
regulator-min-microvolt = <570000>;
regulator-max-microvolt = <650000>;
qcom,init-voltage = <570000>;
status = "okay";
};
};
rpm-regulator-ldoa4 {
status = "okay";
L4A: pm2250_l4: regulator-l4 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3050000>;
qcom,init-voltage = <1650000>;
status = "okay";
};
};
rpm-regulator-ldoa5 {
status = "okay";
L5A: pm2250_l5: regulator-l5 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1312000>;
qcom,init-voltage = <1100000>;
status = "okay";
};
};
rpm-regulator-ldoa6 {
status = "okay";
L6A: pm2250_l6: regulator-l6 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <488000>;
status = "okay";
};
};
/* WCSS_CX */
rpm-regulator-ldoa7 {
status = "okay";
WCSS_CX:
L7A: pm2250_l7: regulator-l7 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <728000>;
qcom,init-voltage = <400000>;
status = "okay";
};
};
rpm-regulator-ldoa10 {
status = "okay";
L10A: pm2250_l10: regulator-l10 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1380000>;
qcom,init-voltage = <1150000>;
status = "okay";
};
};
rpm-regulator-ldoa11 {
status = "okay";
L11A: pm2250_l11: regulator-l11 {
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,init-voltage = <950000>;
status = "okay";
};
};
rpm-regulator-ldoa12 {
status = "okay";
L12A: pm2250_l12: regulator-l12 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <488000>;
status = "okay";
};
};
rpm-regulator-ldoa13 {
status = "okay";
L13A: pm2250_l13: regulator-l13 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1650000>;
status = "okay";
};
};
rpm-regulator-ldoa14 {
status = "okay";
L14A: pm2250_l14: regulator-l14 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1700000>;
status = "okay";
};
};
rpm-regulator-ldoa15 {
status = "okay";
L15A: pm2250_l15: regulator-l15 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
rpm-regulator-ldoa16 {
status = "okay";
L16A: pm2250_l16: regulator-l16 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1500000>;
status = "okay";
};
};
rpm-regulator-ldoa17 {
status = "okay";
L17A: pm2250_l17: regulator-l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
qcom,init-voltage = <3000000>;
status = "okay";
};
};
rpm-regulator-ldoa18 {
status = "okay";
L18A: pm2250_l18: regulator-l18 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
status = "okay";
};
};
rpm-regulator-ldoa19 {
status = "okay";
L19A: pm2250_l19: regulator-l19 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
status = "okay";
};
};
rpm-regulator-ldoa20 {
status = "okay";
L20A: pm2250_l20: regulator-l20 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3600000>;
qcom,init-voltage = <2400000>;
status = "okay";
};
};
rpm-regulator-ldoa21 {
status = "okay";
L21A: pm2250_l21: regulator-l21 {
regulator-min-microvolt = <2921000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2921000>;
status = "okay";
};
};
rpm-regulator-ldoa22 {
status = "okay";
L22A: pm2250_l22: regulator-l22 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3400000>;
qcom,init-voltage = <2850000>;
status = "okay";
};
};
};

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&soc {
spf_core_platform: spf_core_platform {
compatible = "qcom,spf-core-platform";
};
audio_pkt_core_platform: audio-pkt-platform {
compatible = "qcom,audio-pkt-core-platform";
};
qcom,msm-adsp-loader {
compatible = "qcom,adsp-loader";
qcom,adsp-state = <0>;
qcom,proc-img-to-load = "modem";
};
qcom,msm-audio-ion {
compatible = "qcom,msm-audio-ion";
memory-region = <&audio_mem>;
};
pcm0: qcom,msm-pcm {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <0>;
};
routing: qcom,msm-pcm-routing {
compatible = "qcom,msm-pcm-routing";
};
pcm1: qcom,msm-pcm-low-latency {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <1>;
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
qcom,msm-compr-dsp {
compatible = "qcom,msm-compr-dsp";
};
voip: qcom,msm-voip-dsp {
compatible = "qcom,msm-voip-dsp";
};
voice: qcom,msm-pcm-voice {
compatible = "qcom,msm-pcm-voice";
qcom,destroy-cvd;
};
stub_codec: qcom,msm-stub-codec {
compatible = "qcom,msm-stub-codec";
};
qcom,msm-dai-fe {
compatible = "qcom,msm-dai-fe";
};
afe: qcom,msm-pcm-afe {
compatible = "qcom,msm-pcm-afe";
};
hostless: qcom,msm-pcm-hostless {
compatible = "qcom,msm-pcm-hostless";
};
audio_apr: qcom,msm-audio-apr {
compatible = "qcom,msm-audio-apr";
qcom,subsys-name = "apr_modem";
};
host_pcm: qcom,msm-voice-host-pcm {
compatible = "qcom,msm-voice-host-pcm";
};
loopback: qcom,msm-pcm-loopback {
compatible = "qcom,msm-pcm-loopback";
};
compress: qcom,msm-compress-dsp {
compatible = "qcom,msm-compress-dsp";
qcom,adsp-version = "MDSP 1.2";
};
qcom,msm-dai-stub {
compatible = "qcom,msm-dai-stub";
dtmf_tx: qcom,msm-dai-stub-dtmf-tx {
compatible = "qcom,msm-dai-stub-dev";
qcom,msm-dai-stub-dev-id = <4>;
};
rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx {
compatible = "qcom,msm-dai-stub-dev";
qcom,msm-dai-stub-dev-id = <5>;
};
rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx {
compatible = "qcom,msm-dai-stub-dev";
qcom,msm-dai-stub-dev-id = <6>;
};
tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx {
compatible = "qcom,msm-dai-stub-dev";
qcom,msm-dai-stub-dev-id = <7>;
};
tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx {
compatible = "qcom,msm-dai-stub-dev";
qcom,msm-dai-stub-dev-id = <8>;
};
};
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <224>;
};
afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <225>;
};
afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <241>;
};
afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <240>;
};
incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32771>;
};
incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32772>;
};
incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32773>;
};
};
pcm_dtmf: qcom,msm-pcm-dtmf {
compatible = "qcom,msm-pcm-dtmf";
};
dai_pri_auxpcm: qcom,msm-pri-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "primary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
dai_sec_auxpcm: qcom,msm-sec-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "secondary";
qcom,msm-cpudai-afe-clk-ver = <2>;
};
qcom,msm-dai-tdm-pri-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37120>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36864>;
qcom,msm-cpudai-tdm-clk-rate = <12288000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <0>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <0>;
qcom,msm-cpudai-tdm-data-delay = <1>;
qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>;
dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36864>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
qcom,msm-dai-tdm-pri-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37121>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36865>;
qcom,msm-cpudai-tdm-clk-rate = <12288000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <0>;
qcom,msm-cpudai-tdm-sync-src = <1>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <0>;
qcom,msm-cpudai-tdm-data-delay = <1>;
qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>;
dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36865>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
qcom,msm-dai-tdm-sec-rx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37136>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36880>;
qcom,msm-cpudai-tdm-clk-rate = <12288000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <0>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <0>;
qcom,msm-cpudai-tdm-data-delay = <0>;
dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36880>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
qcom,msm-dai-tdm-sec-tx {
compatible = "qcom,msm-dai-tdm";
qcom,msm-cpudai-tdm-group-id = <37137>;
qcom,msm-cpudai-tdm-group-num-ports = <1>;
qcom,msm-cpudai-tdm-group-port-id = <36881>;
qcom,msm-cpudai-tdm-clk-rate = <12288000>;
qcom,msm-cpudai-tdm-clk-internal = <1>;
qcom,msm-cpudai-tdm-sync-mode = <1>;
qcom,msm-cpudai-tdm-sync-src = <0>;
qcom,msm-cpudai-tdm-data-out = <0>;
qcom,msm-cpudai-tdm-invert-sync = <0>;
qcom,msm-cpudai-tdm-data-delay = <0>;
dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 {
compatible = "qcom,msm-dai-q6-tdm";
qcom,msm-cpudai-tdm-dev-id = <36881>;
qcom,msm-cpudai-tdm-data-align = <0>;
};
};
qcom,msm-dai-mi2s {
compatible = "qcom,msm-dai-mi2s";
mi2s_prim: qcom,msm-dai-q6-mi2s-prim {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <0>;
qcom,msm-mi2s-rx-lines = <2>;
qcom,msm-mi2s-tx-lines = <1>;
};
mi2s_sec: qcom,msm-dai-q6-mi2s-sec {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <1>;
qcom,msm-mi2s-rx-lines = <2>;
qcom,msm-mi2s-tx-lines = <1>;
};
};
prim_master: prim_master_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&pri_ws_active_master
&pri_sck_active_master
&pri_dout_active
&pri_din_active>;
pinctrl-1 = <&pri_ws_sleep
&pri_sck_sleep
&pri_dout_sleep
&pri_din_sleep>;
qcom,mi2s-auxpcm-cdc-gpios;
};
prim_slave: prim_slave_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&pri_ws_active_slave
&pri_sck_active_slave
&pri_dout_active
&pri_din_active>;
pinctrl-1 = <&pri_ws_sleep
&pri_sck_sleep
&pri_dout_sleep
&pri_din_sleep>;
qcom,mi2s-auxpcm-cdc-gpios;
};
sec_master: sec_master_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&sec_ws_active_master
&sec_sck_active_master
&sec_dout_active
&sec_din_active>;
pinctrl-1 = <&sec_ws_sleep
&sec_sck_sleep
&sec_dout_sleep
&sec_din_sleep>;
qcom,mi2s-auxpcm-cdc-gpios;
};
sec_slave: sec_slave_pinctrl {
status = "disabled";
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&sec_ws_active_slave
&sec_sck_active_slave
&sec_dout_active
&sec_din_active>;
pinctrl-1 = <&sec_ws_sleep
&sec_sck_sleep
&sec_dout_sleep
&sec_din_sleep>;
qcom,mi2s-auxpcm-cdc-gpios;
};
};

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&soc {
tavil_codec {
swr_master {
compatible = "qcom,swr-wcd";
#address-cells = <2>;
#size-cells = <0>;
wsa881x_0211: wsa881x@20170211 {
status = "disabled";
compatible = "qcom,wsa881x";
reg = <0x00 0x20170211>;
qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>;
};
wsa881x_0212: wsa881x@20170212 {
status = "disabled";
compatible = "qcom,wsa881x";
reg = <0x00 0x20170212>;
qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>;
};
wsa881x_0213: wsa881x@21170213 {
status = "disabled";
compatible = "qcom,wsa881x";
reg = <0x00 0x21170213>;
qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>;
};
wsa881x_0214: wsa881x@21170214 {
compatible = "qcom,wsa881x";
reg = <0x00 0x21170214>;
qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>;
};
};
};
};

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#include "sdxlemur-wcd.dtsi"
#include "sdx-wsa881x.dtsi"
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
&snd_934x {
qcom,audio-routing =
"RX_BIAS", "MCLK",
"MADINPUT", "MCLK",
"AMIC2", "MIC BIAS2",
"MIC BIAS2", "Headset Mic",
"AMIC3", "MIC BIAS2",
"MIC BIAS2", "ANCRight Headset Mic",
"AMIC4", "MIC BIAS2",
"MIC BIAS2", "ANCLeft Headset Mic",
"AMIC5", "MIC BIAS3",
"MIC BIAS3", "Handset Mic",
"DMIC1", "MIC BIAS1",
"MIC BIAS1", "Digital Mic1",
"DMIC2", "MIC BIAS3",
"MIC BIAS3", "Digital Mic2",
"DMIC3", "MIC BIAS3",
"MIC BIAS3", "Digital Mic3",
"DMIC4", "MIC BIAS4",
"MIC BIAS4", "Digital Mic4",
"DMIC5", "MIC BIAS4",
"MIC BIAS4", "Digital Mic5",
"SpkrRight IN", "SPK2 OUT";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>;
qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>;
qcom,cdc-ext-clk-rate = <19200000>;
qcom,tavil-mclk-clk-freq = <9600000>;
asoc-codec = <&stub_codec>;
asoc-codec-names = "msm-stub-codec.1";
qcom,wsa-max-devs = <2>;
qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
<&wsa881x_0213>, <&wsa881x_0214>;
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
"SpkrLeft", "SpkrRight";
};
&soc {
wcd9xxx_intc: wcd9xxx-irq {
status = "ok"
compatible = "qcom,wcd9xxx-irq";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tlmm>;
qcom,gpio-connect = <&tlmm 96 0>;
pinctrl-names = "default";
pinctrl-0 = <&wcd_intr_default>;
};
clock_audio_up: audio_ext_clk_up {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
qcom,codec-lpass-clk-id = <770>;
qcom,codec-lpass-ext-clk-freq = <9600000>;
qcom,use-pinctrl = <1>;
pinctrl-names = "sleep", "active";
pinctrl-0 = <&i2s_mclk_sleep>;
pinctrl-1 = <&i2s_mclk_active>;
#clock-cells = <1>;
};
wcd_rst_gpio: msm_cdc_pinctrl@92 {
compatible = "qcom,msm-cdc-pinctrl";
qcom,cdc-rst-n-gpio = <&tlmm 92 0>;
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_reset_active>;
pinctrl-1 = <&cdc_reset_sleep>;
};
};
&soc {
wcd934x_cdc: tavil_codec {
compatible = "qcom,tavil-i2c";
reg = <0x0d>;
interrupt-parent = <&wcd9xxx_intc>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
30 31>;
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
clock-names = "wcd_clk";
clocks = <&clock_audio_up 0>;
cdc-vdd-buck-supply = <&pmxprairie_l6>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-buck-sido-supply = <&pmxprairie_l6>;
qcom,cdc-buck-sido-voltage = <1800000 1800000>;
qcom,cdc-buck-sido-current = <250000>;
cdc-vdd-tx-h-supply = <&pmxprairie_l6>;
qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
qcom,cdc-vdd-tx-h-current = <25000>;
cdc-vdd-rx-h-supply = <&pmxprairie_l6>;
qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
qcom,cdc-vdd-rx-h-current = <25000>;
cdc-vddpx-1-supply = <&pmxprairie_l6>;
qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
qcom,cdc-vddpx-1-current = <10000>;
qcom,cdc-static-supplies = "cdc-vdd-buck",
"cdc-buck-sido",
"cdc-vdd-tx-h",
"cdc-vdd-rx-h",
"cdc-vddpx-1";
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-micbias4-mv = <1800>;
qcom,cdc-mclk-clk-rate = <9600000>;
qcom,cdc-dmic-sample-rate = <4800000>;
qcom,wdsp-cmpnt-dev-name = "tavil_codec";
};
};

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#include "sdx-audio-lpass.dtsi"
&soc {
snd_934x: sound-tavil {
compatible = "qcom,sdx-asoc-snd-tavil";
qcom,model = "sdx-tavil-i2s-snd-card";
qcom,prim_mi2s_aux_master = <&prim_master>;
qcom,prim_mi2s_aux_slave = <&prim_slave>;
qcom,sec_mi2s_aux_master = <&sec_master>;
qcom,sec_mi2s_aux_slave = <&sec_slave>;
asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>,
<&loopback>, <&hostless>, <&afe>, <&routing>,
<&pcm_dtmf>, <&host_pcm>, <&compress>;
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
"msm-voip-dsp", "msm-pcm-voice",
"msm-pcm-loopback", "msm-pcm-hostless",
"msm-pcm-afe", "msm-pcm-routing",
"msm-pcm-dtmf", "msm-voice-host-pcm",
"msm-compress-dsp";
asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>,
<&dtmf_tx>,
<&rx_capture_tx>, <&rx_playback_rx>,
<&tx_capture_tx>, <&tx_playback_rx>,
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
<&afe_proxy_tx>, <&incall_record_rx>,
<&incall_record_tx>, <&incall_music_rx>,
<&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
<&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
<&dai_sec_auxpcm>;
asoc-cpu-names = "msm-dai-q6-auxpcm.1",
"msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
"msm-dai-stub-dev.4", "msm-dai-stub-dev.5",
"msm-dai-stub-dev.6", "msm-dai-stub-dev.7",
"msm-dai-stub-dev.8", "msm-dai-q6-dev.224",
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
"msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
"msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
"msm-dai-q6-auxpcm.2";
};
};

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#include "sdxlemur-pinctrl.dtsi"
/ {
aliases {
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &i2c_4;
i2c5 = &i2c_5;
i2c6 = &i2c_6;
i2c7 = &i2c_7;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
};
};
&soc {
dma_blsp1: qcom,sps-dma@804000 { /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0x804000 0x23000>;
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
qcom,summing-threshold = <0x10>;
};
i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x835000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
<&dma_blsp1 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_1_active>;
pinctrl-1 = <&i2c_1_sleep>;
status = "disabled";
};
i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x836000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
<&dma_blsp1 11 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_2_active>;
pinctrl-1 = <&i2c_2_sleep>;
status = "disabled";
};
i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x837000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
<&dma_blsp1 13 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_3_active>;
pinctrl-1 = <&i2c_3_sleep>;
status = "disabled";
};
i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 84,85 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x838000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
<&dma_blsp1 15 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_4_active>;
pinctrl-1 = <&i2c_4_sleep>;
status = "disabled";
};
i2c_5: i2c@835000 { /* BLSP1 QUP1: GPIO: 82,83 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x835000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
<&dma_blsp1 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_5_active>;
pinctrl-1 = <&i2c_5_sleep>;
status = "disabled";
};
i2c_6: i2c@836000 { /* BLSP1 QUP2: GPIO: 65,66 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x836000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
<&dma_blsp1 11 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_6_active>;
pinctrl-1 = <&i2c_6_sleep>;
status = "disabled";
};
i2c_7: i2c@838000 { /* BLSP1 QUP4 GPIO: 18,19 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x838000 0x600>;
reg-names = "qup_phys_addr";
interrupt-names = "qup_irq";
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
<&dma_blsp1 15 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <3>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_7_active>;
pinctrl-1 = <&i2c_7_sleep>;
status = "disabled";
};
spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x835000 0x600>,
<0x804000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>,
<0 58 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <8>;
qcom,bam-producer-pipe-index = <9>;
qcom,master-id = <3>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_1_active>;
pinctrl-1 = <&spi_1_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
status = "disabled";
};
spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x836000 0x600>,
<0x804000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
<0 58 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <10>;
qcom,bam-producer-pipe-index = <11>;
qcom,master-id = <3>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_2_active>;
pinctrl-1 = <&spi_2_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
status = "disabled";
};
spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x837000 0x600>,
<0x804000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>,
<0 58 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <12>;
qcom,bam-producer-pipe-index = <13>;
qcom,master-id = <3>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_3_active>;
pinctrl-1 = <&spi_3_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
status = "disabled";
};
spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x838000 0x600>,
<0x804000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>,
<0 58 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
qcom,use-bam;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <14>;
qcom,bam-producer-pipe-index = <15>;
qcom,master-id = <3>;
qcom,use-pinctrl;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi_4_active>;
pinctrl-1 = <&spi_4_sleep>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
status = "disabled";
};
blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x82f000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart1a_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart1a_tx_sleep>,
<&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>;
pinctrl-1 = <&blsp1_uart1a_tx_active>,
<&blsp1_uart1a_rxcts_active>,
<&blsp1_uart1a_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 48,49,80,81 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x82f000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart1b_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart1b_tx_sleep>,
<&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>;
pinctrl-1 = <&blsp1_uart1b_tx_active>,
<&blsp1_uart1b_rxcts_active>,
<&blsp1_uart1b_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2: GPIO: 4,5,6,7 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x830000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart2a_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart2a_tx_sleep>,
<&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>;
pinctrl-1 = <&blsp1_uart2a_tx_active>,
<&blsp1_uart2a_rxcts_active>,
<&blsp1_uart2a_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2: GPIO: 63,64,65,66 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x830000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart2b_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>,
<&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>;
pinctrl-1 = <&blsp1_uart2b_tx_active>,
<&blsp1_uart2b_rxcts_active>,
<&blsp1_uart2b_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x831000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart3_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 26 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <4>;
qcom,bam-rx-ep-pipe-index = <5>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart3_tx_sleep>,
<&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>;
pinctrl-1 = <&blsp1_uart3_tx_active>,
<&blsp1_uart3_rxcts_active>,
<&blsp1_uart3_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4: GPIO: 22,23,48,49 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x832000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart4a_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <6>;
qcom,bam-rx-ep-pipe-index = <7>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart4a_tx_sleep>,
<&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>;
pinctrl-1 = <&blsp1_uart4a_tx_active>,
<&blsp1_uart4a_rxcts_active>,
<&blsp1_uart4a_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4: GPIO: 16,17,18,19 */
compatible = "qcom,msm-hsuart-v14";
reg-names = "core_mem", "bam_mem";
reg = <0x832000 0x200>,
<0x80400 0x23000>;
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart4b_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH
1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH
2 &tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <6>;
qcom,bam-rx-ep-pipe-index = <7>;
clock-names = "iface_clk", "core_clk";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_UART1_APPS_CLK>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart4b_tx_sleep>,
<&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>;
pinctrl-1 = <&blsp1_uart4b_tx_active>,
<&blsp1_uart4b_rxcts_active>,
<&blsp1_uart4b_rfr_active>;
interconnect-names = "blsp-ddr";
interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
status = "disabled";
};
};

4
qcom/sdxlemur-cdp.dtsi
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@ -7,3 +7,7 @@
&qnand_1 {
status = "ok"
};
&usb {
extcon = <&vbus_detect>;
};

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qcom/sdxlemur-mtp-cpe.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-cpe.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE";
compatible = "qcom,sdxlemur-mtp",
"qcom,sdxlemur", "qcom,mtp";
qcom,board-id = <0x6010008 0>;
};

5
qcom/sdxlemur-mtp-cpe.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

11
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE";
compatible = "qcom,sdxlemur-mtp",
"qcom,sdxlemur", "qcom,mtp";
qcom,board-id = <0x5010008 0>;
};

5
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

11
qcom/sdxlemur-mtp-mbb-pcie-ep.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-pcie-ep.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP";
compatible = "qcom,sdxlemur-mtp",
"qcom,sdxlemur", "qcom,mtp";
qcom,board-id = <0x4010008 0>;
};

5
qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

11
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP";
compatible = "qcom,sdxlemur-mtp",
"qcom,sdxlemur", "qcom,mtp";
qcom,board-id = <0x3010008 0>;
};

5
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

11
qcom/sdxlemur-mtp-mbb.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB";
compatible = "qcom,sdxlemur-mtp",
"qcom,sdxlemur", "qcom,mtp";
qcom,board-id = <0x2010008 0>;
};

5
qcom/sdxlemur-mtp-mbb.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

4
qcom/sdxlemur-mtp.dtsi
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@ -7,3 +7,7 @@
&qnand_1 {
status = "ok"
};
&usb {
extcon = <&vbus_detect>;
};

1259
qcom/sdxlemur-pinctrl.dtsi
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File diff suppressed because it is too large Load diff

11
qcom/sdxlemur-rcm-pcie-ep.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-rcm-pcie-ep.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP";
compatible = "qcom,sdxlemur-rcm",
"qcom,sdxlemur", "qcom,rcm";
qcom,board-id = <0x1010015 0>;
};

5
qcom/sdxlemur-rcm-pcie-ep.dtsi Normal file
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@ -0,0 +1,5 @@
&soc {
};

11
qcom/sdxlemur-rcm-rc.dts Normal file
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@ -0,0 +1,11 @@
/dts-v1/;
#include "sdxlemur.dtsi"
#include "sdxlemur-rcm-rc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex";
compatible = "qcom,sdxlemur-rcm",
"qcom,sdxlemur", "qcom,rcm";
qcom,board-id = <0x1010015 0>;
};

5
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@ -0,0 +1,5 @@
&soc {
};

515
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/gpio/gpio.h>
/* RPMh regulators: */
&apps_rsc {
rpmh-regulator-msslvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mss.lvl";
VDD_MODEM_LEVEL:
VDD_MSS_LEVEL:
S1B_LEVEL: pmx65_s1_level: regulator-pmx65-s1-level {
regulator-name = "pmx65_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-smpb2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb2";
S2B: pmx65_s2: regulator-pmx65-s2 {
regulator-name = "pmx65_s2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
qcom,init-voltage = <1224000>;
};
};
rpmh-regulator-smpb3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb3";
S3B: pmx65_s3: regulator-pmx65-s3 {
regulator-name = "pmx65_s3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1040000>;
qcom,init-voltage = <776000>;
};
};
rpmh-regulator-smpb4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb4";
S4B: pmx65_s4: regulator-pmx65-s4 {
regulator-name = "pmx65_s4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2024000>;
qcom,init-voltage = <1824000>;
};
};
rpmh-regulator-mxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mx.lvl";
proxy-supply = <&VDD_MXA_LEVEL>;
VDD_MXA_LEVEL: VDD_MX_LEVEL:
L19B_LEVEL: pmx65_l19_level: regulator-pmx65-l19-level {
regulator-name = "pmx65_l19_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MXA_LEVEL_AO: VDD_MX_LEVEL_AO: L19B_LEVEL_AO:
pmx65_l19_level_ao: regulator-pmx65-l19-level_ao {
regulator-name = "pmx65_l19_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-cxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "cx.lvl";
proxy-supply = <&VDD_CX_LEVEL>;
VDD_CX_LEVEL:
S5B_LEVEL: pmx65_s5_level: regulator-pmx65-s5-level {
regulator-name = "pmx65_s5_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
pmx65_s5_level-parent-supply = <&VDD_MXA_LEVEL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,min-dropout-voltage-level = <(-1)>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO:
S5B_LEVEL_AO: pmx65_s5_level_ao: regulator-pmx65-s5-level_ao {
regulator-name = "pmx65_s5_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
vin-supply = <&VDD_MXA_LEVEL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,min-dropout-voltage-level = <(-1)>;
};
};
rpmh-regulator-smpb7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb7";
S7B: pmx65_s7: regulator-pmx65-s7 {
regulator-name = "pmx65_s7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1040000>;
qcom,init-voltage = <936000>;
};
};
rpmh-regulator-smpb8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb8";
S8B: pmx65_s8: regulator-pmx65-s8 {
regulator-name = "pmx65_s8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <304000>;
regulator-max-microvolt = <1300000>;
qcom,init-voltage = <824000>;
};
};
rpmh-regulator-ldob1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L1B: pmx65_l1: regulator-pmx65-l1 {
regulator-name = "pmx65_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob2";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L2B: pmx65_l2: regulator-pmx65-l2 {
regulator-name = "pmx65_l2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1128000>;
regulator-max-microvolt = <1128000>;
qcom,init-voltage = <1128000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L3B: pmx65_l3: regulator-pmx65-l3 {
regulator-name = "pmx65_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <960000>;
qcom,init-voltage = <800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L4B: pmx65_l4: regulator-pmx65-l4 {
regulator-name = "pmx65_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob5";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L5B: pmx65_l5: regulator-pmx65-l5 {
regulator-name = "pmx65_l5";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L6B: pmx65_l6: regulator-pmx65-l6 {
regulator-name = "pmx65_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-mxclvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mxc.lvl";
VDD_MXC_LEVEL:
L7B_LEVEL: pmx65_l7_level: regulator-pmx65-l7-level {
regulator-name = "pmx65_l7_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ldob8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob8";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L8B: pmx65_l8: regulator-pmx65-l8 {
regulator-name = "pmx65_l8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob9";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L9B: pmx65_l9: regulator-pmx65-l9 {
regulator-name = "pmx65_l9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob10 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob10";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L10B: pmx65_l10: regulator-pmx65-l10 {
regulator-name = "pmx65_l10";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
qcom,init-voltage = <3088000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob11 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob11";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L11B: pmx65_l11: regulator-pmx65-l11 {
regulator-name = "pmx65_l11";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
qcom,init-voltage = <1808000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob12 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob12";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L12B: pmx65_l12: regulator-pmx65-l12 {
regulator-name = "pmx65_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob13 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob13";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L13B: pmx65_l13: regulator-pmx65-l13 {
regulator-name = "pmx65_l13";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
qcom,init-voltage = <1808000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob14 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob14";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L14B: pmx65_l14: regulator-pmx65-l14 {
regulator-name = "pmx65_l14";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <624000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob15 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob15";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L15B: pmx65_l15: regulator-pmx65-l15 {
regulator-name = "pmx65_l15";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob16 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob16";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L16B: pmx65_l16: regulator-pmx65-l16 {
regulator-name = "pmx65_l16";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1776000>;
regulator-max-microvolt = <1776000>;
qcom,init-voltage = <1776000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob17 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob17";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L17B: pmx65_l17: regulator-pmx65-l17 {
regulator-name = "pmx65_l17";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <960000>;
qcom,init-voltage = <744000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob20 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob20";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L20B: pmx65_l20: regulator-pmx65-l20 {
regulator-name = "pmx65_l20";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob21 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob21";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L21B: pmx65_l21: regulator-pmx65-l21 {
regulator-name = "pmx65_l21";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
vreg_vddpx_2: vddpx2-gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "vddpx_2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2850000>;
enable-gpio = <&tlmm 98 GPIO_ACTIVE_HIGH>;
gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
states = <1800000 0>,
<2850000 1>;
startup-delay-us = <200000>;
enable-active-high;
};
vreg_sd_vdd: sd-vdd-fixed-regulator {
compatible = "qcom,stub-regulator";
regulator-name = "sd_vdd";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
parent-supply = <&vreg_vddpx_2>;
};
};

265
qcom/sdxlemur-stub-regulator.dtsi
View file

@ -1,265 +0,0 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
&soc {
VDD_MSS_LEVEL:
S1E_LEVEL:
pmx65_s1_level: regulator-pmx65-s1-level {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s1_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S2E:
pmx65_s2: regulator-pmx65-s2 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1560000>;
};
S4E:
pmx65_s4: regulator-pmx65-s4 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s4";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <2040000>;
};
VDD_CX_LEVEL:
S5E_LEVEL:
pmx65_s5_level: regulator-pmx65-s5-level {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s5_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO:
S5E_LEVEL_AO:
pmx65_s5_level_ao: regulator-pmx65-s5-level-ao {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s5_level_ao";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S7E:
pmx65_s7: regulator-pmx65-s7 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_s7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <775000>;
regulator-max-microvolt = <1150000>;
};
L1E:
pmx65_l1: regulator-pmx65-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l1";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
};
L2E:
pmx65_l2: regulator-pmx65-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l2";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <1170000>;
};
L3E:
pmx65_l3: regulator-pmx65-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l3";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <800000>;
};
L4E:
pmx65_l4: regulator-pmx65-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l4";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
};
L5E:
pmx65_l5: regulator-pmx65-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l5";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1615000>;
regulator-max-microvolt = <1980000>;
};
L6E:
pmx65_l6: regulator-pmx65-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l6";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
VDD_MX_LEVEL:
L7E_LEVEL:
pmx65_l7_level: regulator-pmx65-l7-level {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l7_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MX_LEVEL_AO:
L7E_LEVEL_AO:
pmx65_l7_level_ao: regulator-pmx65-l7-level-ao {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l7_level_ao";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L8E:
pmx65_l8: regulator-pmx65-l8 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
};
L9E:
pmx65_l9: regulator-pmx65-l9 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <760000>;
regulator-max-microvolt = <840000>;
};
L10E:
pmx65_l10: regulator-pmx65-l10 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l10";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L11E:
pmx65_l11: regulator-pmx65-l11 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l11";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
};
L12E:
pmx65_l12: regulator-pmx65-l12 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l12";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
};
L13E:
pmx65_l13: regulator-pmx65-l13 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l13";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
};
L14E:
pmx65_l14: regulator-pmx65-l14 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l14";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <515000>;
regulator-max-microvolt = <1050000>;
};
L15E:
pmx65_l15: regulator-pmx65-l15 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l15";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L16E:
pmx65_l16: regulator-pmx65-l16 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l16";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1698000>;
regulator-max-microvolt = <1957000>;
};
L17E:
pmx65_l17: regulator-pmx65-l17 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l17";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <536000>;
regulator-max-microvolt = <888000>;
};
L18E:
pmx65_l18: regulator-pmx65-l18 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l18";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1304000>;
};
L19E:
pmx65_l19: regulator-pmx65-l19 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l19";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <880000>;
};
L20E:
pmx65_l20: regulator-pmx65-l20 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l20";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <826000>;
regulator-max-microvolt = <898000>;
};
L21E:
pmx65_l21: regulator-pmx65-l21 {
compatible = "qcom,stub-regulator";
regulator-name = "pmx65_l21";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <800000>;
};
};

159
qcom/sdxlemur-usb.dtsi
View file

@ -1,3 +1,5 @@
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
&soc {
usb: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
@ -40,10 +42,16 @@
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&system_noc MASTER_USB3 &mc_virt SLAVE_EBI1>,
<&system_noc MASTER_USB3 &system_noc SLAVE_IPA_CFG>,
<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0x0a600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy>, <&usb_qmp_phy>;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,has-lpm-erratum;
@ -60,4 +68,155 @@
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb2_phy: hsphy@ff4000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0xff4000 0x120>;
reg-names = "hsusb_phy_base";
vdd-supply = <&pmx65_l4>;
qcom,vdd-voltage-level = <0 912000 912000>;
vdda18-supply = <&pmx65_l5>;
vdda33-supply = <&pmx65_l10>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "ref_clk_src", "cfg_ahb_clk";
resets = <&gcc GCC_QUSB2PHY_BCR>;
reset-names = "phy_reset";
qcom,no-rext-present;
};
usb_qmp_phy: ssphy@ff6000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0xff6000 0x2000>,
<0xff628c 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&pmx65_l4>;
qcom,vdd-voltage-level = <0 912000 912000>;
qcom,vdd-max-load-uA = <47900>;
core-supply = <&pmx65_l1>;
qcom,core-max-load-uA = <15000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
"cfg_ahb_clk";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0
USB3_UNI_QSERDES_RX_GM_CAL 0x00 0
USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0
USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_UNI_PCS_EQ_CONFIG1 0x4B 0
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
0xffffffff 0xffffffff 0x00>;
qcom,qmp-phy-reg-offset =
<USB3_UNI_PCS_PCS_STATUS1
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_UNI_PCS_POWER_DOWN_CONTROL
USB3_UNI_PCS_SW_RESET
USB3_UNI_PCS_START_CONTROL>;
};
};

68
qcom/sdxlemur-wcd.dtsi Normal file
View file

@ -0,0 +1,68 @@
&soc {
tavil_codec {
wcd: wcd_pinctrl@5 {
compatible = "qcom,wcd-pinctrl";
qcom,num-gpios = <5>;
gpio-controller;
#gpio-cells = <2>;
spkr_1_wcd_en_active: spkr_1_wcd_en_active {
mux {
pins = "gpio2";
};
config {
pins = "gpio2";
output-high;
};
};
spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep {
mux {
pins = "gpio2";
};
config {
pins = "gpio2";
input-enable;
};
};
spkr_2_wcd_en_active: spkr_2_sd_n_active {
mux {
pins = "gpio3";
};
config {
pins = "gpio3";
output-high;
};
};
spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep {
mux {
pins = "gpio3";
};
config {
pins = "gpio3";
input-enable;
};
};
};
wsa_spkr_wcd_sd1: msm_cdc_pinctrll {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_1_wcd_en_active>;
pinctrl-1 = <&spkr_1_wcd_en_sleep>;
};
wsa_spkr_wcd_sd2: msm_cdc_pinctrlr {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_2_wcd_en_active>;
pinctrl-1 = <&spkr_2_wcd_en_sleep>;
};
};
};

260
qcom/sdxlemur.dtsi
View file

@ -3,9 +3,12 @@
#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/sound/qcom,gpr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interconnect/qcom,sdxlemur.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
#address-cells = <1>;
@ -29,10 +32,10 @@
#size-cells = <1>;
ranges;
cmd_db: reserved-memory@8fe20000 {
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x8fe20000 0x20000>;
reg = <0x8fee0000 0x20000>;
};
mpss_adsp_mem: mpss_adsp_region@90800000 {
@ -87,6 +90,12 @@
size = <0xC00000>;
linux,cma-default;
};
audio_mem: audio_region@0 {
compatible = "shared-dma-pool";
no-map;
size = <0x400000>;
};
};
cpus {
@ -223,11 +232,12 @@
dcc-ram-offset = <0x800>;
};
watchdog: qcom,wdt@17817000 {
wdog: qcom,wdt@17817000 {
compatible = "qcom,msm-watchdog";
reg = <0x17817000 0x1000>;
reg-names = "wdt-base";
interrupts = <1 3 0>, <1 2 0>;
interrupts = <GIC_PPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_PPI 2 IRQ_TYPE_EDGE_RISING>;
qcom,bark-time = <11000>;
qcom,pet-time = <10000>;
qcom,wakeup-enable;
@ -373,10 +383,30 @@
#reset-cells = <1>;
};
clock_apsscc: syscon@17811000 {
compatible = "syscon";
reg = <0x17811000 0x20>;
};
clock_mccc: syscon@90b0000 {
compatible = "syscon";
reg = <0x90b0000 0x54>;
};
clock_debugcc: qcom,cc-debug {
compatible = "qcom,sdxlemur-debugcc";
qcom,gcc = <&gcc>;
qcom,apsscc = <&clock_apsscc>;
qcom,mccc = <&clock_mccc>;
clock-names = "xo_clk_src";
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
};
serial_uart: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x831000 0x200>;
interrupts = <0 26 0>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
@ -386,6 +416,47 @@
status = "ok"
};
pil_modem: qcom,mss@4080000 {
compatible = "qcom,pil-tz-generic";
reg = <0x4080000 0x100>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mss-supply = <&VDD_MSS_LEVEL>;
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
qcom,firmware-name = "modem";
memory-region = <&mpss_adsp_mem>;
qcom,pas-id = <4>;
qcom,smem-id = <421>;
qcom,sysmon-id = <0>;
qcom,ssctl-instance-id = <0x22>;
interrupts-extended = <&intc 0 250 1>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
status = "ok"
};
qnand_1: nand@1b00000 {
compatible = "qcom,msm-nand";
reg = <0x01b00000 0x1000>,
@ -403,10 +474,20 @@
status = "disabled";
};
apsscc: clock-controller@17808000 {
compatible = "qcom,dummycc";
clock-output-names = "apsscc_clocks";
#clock-cells = <1>;
apsscc: clock-controller@17808100 {
compatible = "qcom,sdxlemur-apsscc";
clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>;
clock-names = "bi_tcxo_ao", "gpll0_out_even";
reg = <0x17810008 0x16>,
<0x17808100 0x100>;
reg-names = "apcs_cmd", "apcs_pll";
vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
qcom,speed0-bin-v0 =
< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
< 1497600000 RPMH_REGULATOR_LEVEL_TURBO>;
#reset-cells = <1>;
};
@ -575,6 +656,29 @@
0x2000 3
0x4400 2>;
};
qcom,gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "modem_apps";
qcom,intents = <0x200 20>;
reg = <GPR_DOMAIN_MODEM>;
spf_core {
compatible = "qcom,spf_core";
reg = <GPR_SVC_ADSP_CORE>;
};
audio-pkt {
compatible = "qcom,audio-pkt";
qcom,audiopkt-ch-name = "apr_audio_svc";
reg = <GPR_SVC_MAX>;
};
audio_prm {
compatible = "qcom,audio_prm";
reg = <GPR_SVC_ASM>;
};
};
};
};
@ -665,6 +769,132 @@
compatible = "qcom,secure-buffer";
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
qcom,pil-force-shutdown;
};
ipa_hw: qcom,ipa@03e00000 {
compatible = "qcom,ipa";
mboxes = <&qmp_aop 0>;
reg =
<0x3e00000 0x84000>,
<0x3e04000 0xfc000>;
reg-names = "ipa-base", "gsi-base";
qcom,ipa-cfg-offset = <0x0140000>;
interrupts =
<0 241 IRQ_TYPE_LEVEL_HIGH>,
<0 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <21>; /* IPA core version = IPAv5.0 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <0>; /* MDM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
qcom,modem-cfg-emb-pipe-flt;
qcom,use-xbl-boot;
qcom,arm-smmu;
qcom,smmu-fast-map;
qcom,ipa-wdi3-over-gsi;
qcom,lan-rx-napi;
qcom,wan-use-skb-page;
qcom,tx-wrapper-cache-max-size = <400>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <4>;
interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&system_noc MASTER_IPA &system_noc SLAVE_IMEM>,
<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<150000 600000 150000 1804000 75000 300000 0 76800>;
/* SVS */
qcom,svs =
<625000 1200000 625000 3072000 312500 700000 0 150000>;
/* NOMINAL */
qcom,nominal =
<1250000 2400000 1250000 6220800 625000 1500000 0 400000>;
/* TURBO */
qcom,turbo =
<2000000 3500000 2000000 7219200 1000000 1920000 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x5E0 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x14688000 0x14688000 0x3000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x5E1 0x0>;
dma-coherent;
qcom,iommu-dma = "atomic";
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x5E2 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,iommu-dma = "atomic";
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x5E3 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
@ -686,12 +916,22 @@
thermal_zones: thermal-zones {
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x400000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
qcom,vm-nav-path;
};
};
#include "sdxlemur-pinctrl.dtsi"
#include "sdxlemur-stub-regulator.dtsi"
#include "sdxlemur-regulators.dtsi"
#include "msm-arm-smmu-sdxlemur.dtsi"
#include "sdxlemur-ion.dtsi"
#include "sdxlemur-usb.dtsi"
#include "sdxlemur-pm.dtsi"
#include "sdxlemur-pcie.dtsi"
#include "sdxlemur-blsp.dtsi"
#include "sdxlemur-audio.dtsi"

2
qcom/shima-gpu.dtsi
View file

@ -438,7 +438,7 @@
gmu: qcom,gmu@3d69000 {
compatible = "qcom,gpu-gmu";
reg = <0x3d6a000 0x30000>,
reg = <0x3d6a000 0x34000>,
<0xb290000 0x10000>;
reg-names = "kgsl_gmu_reg",

11
qcom/shima-idp-120fps-overlay.dts Normal file
View file

@ -0,0 +1,11 @@
/dts-v1/;
/plugin/;
#include "shima-idp-120fps.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima IDP + 120fps";
compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp";
qcom,msm-id = <450 0x10000>;
qcom,board-id = <34 2>;
};

10
qcom/shima-idp-120fps.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "shima.dtsi"
#include "shima-idp-120fps.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima IDP + 120fps";
compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp";
qcom,board-id = <34 2>;
};

8
qcom/shima-idp-120fps.dtsi Normal file
View file

@ -0,0 +1,8 @@
#include "shima-idp.dtsi"
&soc {
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>;
};

19
qcom/shima-idp.dtsi
View file

@ -98,21 +98,20 @@
vdd-hba-fixed-regulator;
vcc-supply = <&L7B>;
vcc-voltage-level = <2950000 2960000>;
vcc-voltage-level = <2504000 2960000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
vccq-supply = <&L9B>;
vccq-max-microamp = <900000>;
vccq-min-microamp = <0>;
vccq-min-microamp = <10000>;
vccq2-supply = <&S10B>;
vccq2-voltage-level = <1800000 1800000>;
vccq2-max-microamp = <800000>;
qcom,vddp-ref-clk-supply = <&L9B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vddp-ref-clk-min-microamp = <0>;
qcom,vddp-ref-clk-max-microamp = <10000>;
status = "ok"
};
@ -148,8 +147,17 @@
status = "ok"
};
&pm8350b_amoled_ecm {
display-panels = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video
&dsi_r66451_amoled_60hz_video
&dsi_r66451_amoled_60hz_cmd
&dsi_r66451_amoled_144hz_cmd>;
};
&battery_charger {
qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
qcom,wireless-fw-name = "idt9412.bin";
};
&qupv3_se10_i2c {
@ -180,7 +188,8 @@
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video
&dsi_r66451_amoled_60hz_video
&dsi_r66451_amoled_60hz_cmd>;
&dsi_r66451_amoled_60hz_cmd
&dsi_r66451_amoled_144hz_cmd>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";

11
qcom/shima-idps-digital-mics-120fps-overlay.dts Normal file
View file

@ -0,0 +1,11 @@
/dts-v1/;
/plugin/;
#include "shima-idps-digital-mics-120fps.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps";
compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp";
qcom,msm-id = <450 0x10000>;
qcom,board-id = <34 3>;
};

10
qcom/shima-idps-digital-mics-120fps.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "shima.dtsi"
#include "shima-idps-digital-mics-120fps.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps";
compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp";
qcom,board-id = <34 3>;
};

8
qcom/shima-idps-digital-mics-120fps.dtsi Normal file
View file

@ -0,0 +1,8 @@
#include "shima-idps-digital-mics.dtsi"
&soc {
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>;
};

11
qcom/shima-pcie.dtsi
View file

@ -33,7 +33,7 @@
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0_msi>;
msi-parent = <&pcie0_msi_snps>;
perst-gpio = <&tlmm 94 0>;
wake-gpio = <&tlmm 96 0>;
@ -194,6 +194,15 @@
};
};
pcie0_msi_snps: qcom,pcie0_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
};
pcie0_msi: qcom,pcie0_msi@17a10040 {
compatible = "qcom,pci-msi";
msi-controller;

8
qcom/shima-pinctrl.dtsi
View file

@ -2872,12 +2872,12 @@
pmx_sde: pmx_sde {
sde_dsi_active: sde_dsi_active {
mux {
pins = "gpio24";
pins = "gpio24", "gpio47";
function = "gpio";
};
config {
pins = "gpio24";
pins = "gpio24", "gpio47";
drive-strength = <8>; /* 8 mA */
bias-disable = <0>; /* no pull */
};
@ -2885,12 +2885,12 @@
sde_dsi_suspend: sde_dsi_suspend {
mux {
pins = "gpio24";
pins = "gpio24", "gpio47";
function = "gpio";
};
config {
pins = "gpio24";
pins = "gpio24", "gpio47";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};

12
qcom/shima-pmic-overlay.dtsi
View file

@ -47,6 +47,18 @@
power-source = <1>;
};
};
lcd_backlight_ctrl {
lcd_backlight_ctrl_default: lcd_backlight_ctrl_default {
pins = "gpio9";
function = "func1";
input-disable;
output-enable;
bias-disable;
power-source = <1>; /* 1.8V */
qcom,drive-strength = <2>;
};
};
};
&pmk8350_vadc {

13
qcom/shima-qrd.dtsi
View file

@ -99,20 +99,19 @@
vdd-hba-fixed-regulator;
vcc-supply = <&L7B>;
vcc-voltage-level = <2950000 2960000>;
vcc-voltage-level = <2504000 2960000>;
vcc-low-voltage-sup;
vcc-max-microamp = <800000>;
vccq-supply = <&L9B>;
vccq-max-microamp = <900000>;
vccq-min-microamp = <0>;
vccq-min-microamp = <10000>;
vccq2-supply = <&S10B>;
vccq2-voltage-level = <1800000 1800000>;
qcom,vddp-ref-clk-supply = <&L9B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vddp-ref-clk-min-microamp = <0>;
qcom,vddp-ref-clk-max-microamp = <10000>;
status = "ok"
};
@ -185,11 +184,17 @@
status = "ok"
};
&pm8350b_amoled_ecm {
display-panels = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
};
&battery_charger {
qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
7500000 7000000 6500000 6000000 5500000
5000000 4500000 4000000 3500000 3000000
2500000 2000000 1500000 1000000 500000>;
qcom,wireless-fw-name = "idt9412.bin";
};
&qupv3_se10_i2c {

4
qcom/shima-regulators.dtsi
View file

@ -678,9 +678,9 @@
pm8350c_l12: regulator-pm8350c-l12 {
regulator-name = "pm8350c_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1920000>;
regulator-min-microvolt = <1820000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1920000>;
qcom,init-voltage = <1820000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <60700>;

299
qcom/shima-thermal.dtsi
View file

@ -2,6 +2,23 @@
#include "lahaina-thermal-modem.dtsi"
&qmi_tmd {
modem {
modem_current: modem_current {
qcom,qmi-dev-name = "modem_current";
#cooling-cells = <2>;
};
modem_bw_backoff: modem_bw_backoff {
qcom,qmi-dev-name = "modem_bw_backoff";
#cooling-cells = <2>;
};
modem_wlan_bw: modem_wlan_bw {
qcom,qmi-dev-name = "wlan_bw";
#cooling-cells = <2>;
};
};
cdsp {
qcom,instance-id = <QMI_CDSP_INST_ID>;
@ -17,6 +34,38 @@
};
};
&soc {
qmi-ts-sensors {
modem {
qcom,qmi-sensor-names = "pa",
"pa_1",
"qfe_wtr0",
"modem_tsens",
"qfe_mmw0",
"qfe_mmw1",
"qfe_mmw2",
"qfe_mmw3",
"xo_therm",
"qfe_mmw_streamer0",
"qfe_mmw0_mod",
"qfe_mmw1_mod",
"qfe_mmw2_mod",
"qfe_mmw3_mod",
"qfe_ret_pa0",
"qfe_wtr_pa0",
"qfe_wtr_pa1",
"qfe_wtr_pa2",
"qfe_wtr_pa3",
"sys_therm1",
"modem_tsens1",
"mmw_pa1",
"mmw_pa2",
"mmw_pa3",
"msm_skin_therm";
};
};
};
&cpufreq_hw {
qcom,cpu-isolation {
compatible = "qcom,cpu-isolate";
@ -61,6 +110,49 @@
};
};
qcom,cpu-hotplug {
compatible = "qcom,cpu-hotplug";
cpu0_hotplug: cpu0-hotplug {
qcom,cpu = <&CPU0>;
#cooling-cells = <2>;
};
cpu1_hotplug: cpu1-hotplug {
qcom,cpu = <&CPU1>;
#cooling-cells = <2>;
};
cpu2_hotplug: cpu2-hotplug {
qcom,cpu = <&CPU2>;
#cooling-cells = <2>;
};
cpu3_hotplug: cpu3-hotplug {
qcom,cpu = <&CPU3>;
#cooling-cells = <2>;
};
cpu4_hotplug: cpu4-hotplug {
qcom,cpu = <&CPU4>;
#cooling-cells = <2>;
};
cpu5_hotplug: cpu5-hotplug {
qcom,cpu = <&CPU5>;
#cooling-cells = <2>;
};
cpu6_hotplug: cpu6-hotplug {
qcom,cpu = <&CPU6>;
#cooling-cells = <2>;
};
cpu7_hotplug: cpu7-hotplug {
qcom,cpu = <&CPU7>;
#cooling-cells = <2>;
};
};
qcom,cpu-voltage-cdev {
compatible = "qcom,cc-cooling-devices";
apc1_cluster: qcom,apc1-cluster {
@ -75,6 +167,24 @@
};
&thermal_zones {
/delete-node/ modem-sdr-mmw-usr;
/delete-node/ modem-ambient-usr;
msm-skin-therm-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MSM_SKIN)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
aoss-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
@ -666,6 +776,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu00_config1: cpu00-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -673,6 +789,17 @@
trip = <&cpu00_config>;
cooling-device = <&cpu0_isolate 1 1>;
};
cpu00_cdev1 {
trip = <&cpu00_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu00_cdev2 {
trip = <&cpu00_config1>;
cooling-device = <&cpu0_hotplug 1 1>;
};
};
};
@ -687,6 +814,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu01_config1: cpu01-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -694,6 +827,17 @@
trip = <&cpu01_config>;
cooling-device = <&cpu1_isolate 1 1>;
};
cpu01_cdev1 {
trip = <&cpu01_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu01_cdev2 {
trip = <&cpu01_config1>;
cooling-device = <&cpu1_hotplug 1 1>;
};
};
};
@ -708,6 +852,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu02_config1: cpu02-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -715,6 +865,17 @@
trip = <&cpu02_config>;
cooling-device = <&cpu2_isolate 1 1>;
};
cpu02_cdev1 {
trip = <&cpu02_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu02_cdev2 {
trip = <&cpu02_config1>;
cooling-device = <&cpu2_hotplug 1 1>;
};
};
};
@ -729,6 +890,12 @@
hysteresis = <10000>;
type = "passive";
};
cpu03_config1: cpu03-config1 {
temperature = <112000>;
hysteresis = <12000>;
type = "passive";
};
};
cooling-maps {
@ -736,6 +903,17 @@
trip = <&cpu03_config>;
cooling-device = <&cpu3_isolate 1 1>;
};
cpu03_cdev1 {
trip = <&cpu03_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu03_cdev2 {
trip = <&cpu03_config1>;
cooling-device = <&cpu3_hotplug 1 1>;
};
};
};
@ -746,6 +924,12 @@
thermal-governor = "step_wise";
trips {
cpu10_config: cpu10-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu10_config1: cpu10-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -763,6 +947,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu10_cdev2 {
trip = <&cpu10_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
};
};
@ -773,6 +962,12 @@
thermal-governor = "step_wise";
trips {
cpu11_config: cpu11-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu11_config1: cpu11-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -790,6 +985,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu11_cdev2 {
trip = <&cpu11_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
};
};
@ -800,6 +1000,12 @@
thermal-governor = "step_wise";
trips {
cpu12_config: cpu12-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu12_config1: cpu12-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -817,6 +1023,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu12_cdev2 {
trip = <&cpu12_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
};
};
@ -827,6 +1038,12 @@
thermal-governor = "step_wise";
trips {
cpu13_config: cpu13-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu13_config1: cpu13-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -844,6 +1061,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu13_cdev2 {
trip = <&cpu13_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
};
};
@ -854,6 +1076,12 @@
thermal-governor = "step_wise";
trips {
cpu14_config: cpu14-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu14_config1: cpu14-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -871,6 +1099,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu14_cdev2 {
trip = <&cpu14_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
};
};
@ -881,6 +1114,12 @@
thermal-governor = "step_wise";
trips {
cpu15_config: cpu15-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu15_config1: cpu15-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -898,6 +1137,11 @@
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu15_cdev2 {
trip = <&cpu15_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
};
};
@ -908,6 +1152,12 @@
thermal-governor = "step_wise";
trips {
cpu16_config: cpu16-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu16_config1: cpu16-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -919,6 +1169,11 @@
trip = <&cpu16_config>;
cooling-device = <&cpu7_isolate 1 1>;
};
cpu16_cdev2 {
trip = <&cpu16_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
};
};
@ -929,6 +1184,12 @@
thermal-governor = "step_wise";
trips {
cpu17_config: cpu17-config {
temperature = <108000>;
hysteresis = <8000>;
type = "passive";
};
cpu17_config1: cpu17-config1 {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
@ -940,17 +1201,21 @@
trip = <&cpu17_config>;
cooling-device = <&cpu7_isolate 1 1>;
};
cpu17_cdev2 {
trip = <&cpu17_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
};
};
gpuss-max-step {
gpuss-0-step {
polling-delay-passive = <10>;
polling-delay = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 1>, <&tsens1 2>;
sensor-aggregation = <AGGREGATE_MAX_VALUE>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss_config: active-config0 {
gpuss0_config: active-config0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
@ -959,7 +1224,29 @@
cooling-maps {
gpu_cdev {
trip = <&gpuss_config>;
trip = <&gpuss0_config>;
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
gpuss-1-step {
polling-delay-passive = <10>;
polling-delay = <100>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_config: active-config0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
gpu_cdev {
trip = <&gpuss1_config>;
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};

3
qcom/shima-usb.dtsi
View file

@ -148,7 +148,8 @@
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_CLAMP_ENABLE>;
USB3_DP_PCS_CLAMP_ENABLE
USB3_DP_COM_TYPEC_STATUS>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */

11
qcom/shima-vm.dtsi
View file

@ -15,7 +15,7 @@
};
chosen {
bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8";
bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8";
linux,initrd-start = <0x2a900000>;
linux,initrd-end = <0x2b100000>; /* 8 MB */
kaslr-seed = <0xfeedbeef 0xc0def00d>;
@ -228,6 +228,15 @@
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,support-hypervisor;
};
/*
* QUPv3 Instances
* Qup0 2: SE 10

75
qcom/shima.dtsi
View file

@ -779,6 +779,7 @@
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom-mem-buf {
@ -929,10 +930,8 @@
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -1461,6 +1460,18 @@
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
};
};
@ -1711,7 +1722,7 @@
reset-names = "rst";
iommus = <&apps_smmu 0x80 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma = "fastmap";
dma-coherent;
rpm-level = <3>;
@ -1792,6 +1803,8 @@
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
@ -1799,6 +1812,10 @@
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
@ -2551,7 +2568,6 @@
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 300, 4) >,
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1171200 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
@ -2561,7 +2577,6 @@
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 300, 4) >,
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1171200 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
@ -2596,7 +2611,7 @@
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
@ -2623,26 +2638,6 @@
};
};
cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 300, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 300, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_computemon: qcom,cpu4-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
@ -2688,14 +2683,14 @@
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 300, 4) >,
< 2361600 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 300, 4) >,
< 2361600 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
@ -3472,11 +3467,27 @@
};
};
qfprom_sys: qfprom@0 {
compatible = "qcom,qfprom-sys";
nvmem-cells = <&gpu_speed_bin>,
<&gpu_gaming_bin>,
<&adsp_variant>,
<&feat_conf_m7>,
<&feat_conf_qc_spare_20_lsb>;
nvmem-cell-names = "gpu_speed_bin",
"gpu_gaming_bin",
"adsp_variant",
"feat_conf_m7",
"feat_conf_qc_spare_20_lsb";
};
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 64 0>;
qcom,bt-en-gpio = <&tlmm 65 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
@ -3653,6 +3664,7 @@
pinctrl-0 = <&bt_en_sleep>;
qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 91 0>; /* SW_CTRL */
qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */
qcom,bt-vdd-io-supply = <&S10B>;
qcom,bt-vdd-aon-supply = <&S2C>;
@ -3720,11 +3732,14 @@
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,ipa-uc-holb-monitor;
qcom,gsi_wdi_db_polling;
qcom,ipa-holb-monitor-poll-period = <5>;
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
qcom,tx-wrapper-cache-max-size = <400>;
/* Entry will be removed once shadow stack changes checked-in */
qcom,ipa-wan-aggr-pkt-cnt = <2>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;

1
qcom/yupik-pinctrl.dtsi
View file

@ -7,5 +7,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
};
};

185
qcom/yupik-pm.dtsi Normal file
View file

@ -0,0 +1,185 @@
&soc {
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
#address-cells = <1>;
#size-cells = <0>;
qcom,pm-cluster@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
idle-state-name = "L3";
qcom,clstr-tmr-add = <1000>;
qcom,psci-mode-shift = <4>;
qcom,psci-mode-mask = <0xfff>;
CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */
reg = <0>;
compatible = "arm,idle-state";
idle-state-name = "l3-wfi";
entry-latency-us = <660>;
exit-latency-us = <600>;
min-residency-us = <1260>;
arm,psci-suspend-param = <0x10>;
qcom,psci-mode = <0x1>;
};
CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */
reg = <1>;
compatible = "arm,idle-state";
idle-state-name = "l3-pc";
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x40>;
qcom,psci-mode = <0x4>;
qcom,is-reset;
qcom,min-child-idx = <2>;
};
CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */
reg = <2>;
compatible = "arm,idle-state";
idle-state-name = "cx-off";
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
arm,psci-suspend-param = <0x2240>;
qcom,psci-mode = <0x224>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;
};
LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */
reg = <3>;
compatible = "arm,idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9826>;
arm,psci-suspend-param = <0xc340>;
qcom,psci-mode = <0xc34>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;
};
qcom,pm-cpu@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
qcom,psci-mode-shift = <0>;
qcom,psci-mode-mask = <0xf>;
qcom,ref-stddev = <500>;
qcom,tmr-add = <1000>;
qcom,ref-premature-cnt = <1>;
qcom,disable-ipi-prediction;
qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */
reg = <0>;
compatible = "arm,idle-state";
idle-state-name = "wfi";
entry-latency-us = <61>;
exit-latency-us = <60>;
min-residency-us = <121>;
arm,psci-suspend-param = <0x1>;
qcom,psci-cpu-mode = <0x1>;
};
SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */
reg = <1>;
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
arm,psci-suspend-param = <0x40000003>;
qcom,psci-cpu-mode = <0x3>;
local-timer-stop;
qcom,is-reset;
qcom,use-broadcast-timer;
};
SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */
reg = <2>;
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <702>;
exit-latency-us = <915>;
min-residency-us = <4001>;
arm,psci-suspend-param = <0x40000004>;
qcom,psci-cpu-mode = <0x4>;
local-timer-stop;
qcom,is-reset;
qcom,use-broadcast-timer;
};
};
qcom,pm-cpu@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
qcom,psci-mode-shift = <0>;
qcom,psci-mode-mask = <0xf>;
qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */
reg = <0>;
compatible = "arm,idle-state";
idle-state-name = "wfi";
entry-latency-us = <55>;
exit-latency-us = <66>;
min-residency-us = <121>;
arm,psci-suspend-param = <0x1>;
qcom,psci-cpu-mode = <0x1>;
};
GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */
reg = <1>;
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <523>;
exit-latency-us = <1244>;
min-residency-us = <2207>;
arm,psci-suspend-param = <0x40000003>;
qcom,psci-cpu-mode = <0x3>;
local-timer-stop;
qcom,is-reset;
qcom,use-broadcast-timer;
};
GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */
reg = <2>;
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <526>;
exit-latency-us = <1854>;
min-residency-us = <5555>;
arm,psci-suspend-param = <0x40000004>;
qcom,psci-cpu-mode = <0x4>;
local-timer-stop;
qcom,is-reset;
qcom,use-broadcast-timer;
};
};
};
};
rpmh-master-stats@b221200 {
compatible = "qcom,rpmh-master-stats-v1";
reg = <0xb221200 0x60>;
};
soc-sleep-stats@c3f0000 {
compatible = "qcom,rpmh-sleep-stats";
reg = <0xc3f0000 0x400>;
};
ddr-stats@c300000 {
compatible = "qcom,ddr-stats";
reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
reg-names = "phys_addr_base", "offset_addr";
};
};

59
qcom/yupik-rumi.dtsi
View file

@ -10,4 +10,63 @@
wdog: qcom,wdt@17c10000 {
status = "disabled";
};
usb_emu_phy_0: usb_emu_phy@a720000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a720000 0x9500>;
qcom,emu-init-seq = <0xffff 0x4
0xfff0 0x4
0x100000 0x20
0x0 0x20
0x101f0 0x20
0x100000 0x3c
0x0 0x3c
0x10060 0x3c
0x0 0x4>;
};
};
&usb0 {
/delete-property/ extcon;
dwc3@a600000 {
usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&L10C>;
vdda-pll-supply = <&L6B>;
vdda-phy-max-microamp = <97100>;
vdda-pll-max-microamp = <18400>;
status = "ok"
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L7B>;
vcc-max-microamp = <800000>;
vccq-supply = <&L9B>;
vccq-max-microamp = <900000>;
qcom,vddp-ref-clk-supply = <&L9B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
status = "ok"
};

68
qcom/yupik-usb.dtsi Normal file
View file

@ -0,0 +1,68 @@
#include <dt-bindings/clock/qcom,gcc-yupik.h>
&soc {
/* Primary USB port related controller */
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,ssp-u3-u0-quirk;
tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
};

280
qcom/yupik.dtsi
View file

@ -10,6 +10,8 @@
#include <dt-bindings/interconnect/qcom,yupik.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Yupik";
@ -21,7 +23,35 @@
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases { };
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
};
firmware: firmware {
scm {
compatible = "qcom,scm";
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
};
};
cpus {
#address-cells = <2>;
@ -32,6 +62,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@ -50,6 +81,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@ -63,6 +95,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@ -76,6 +109,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
@ -89,6 +123,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
@ -102,6 +137,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
@ -115,6 +151,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@ -128,6 +165,7 @@
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
@ -317,6 +355,19 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,yupik-pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
@ -324,6 +375,11 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
@ -401,6 +457,54 @@
};
};
qcom,msm-imem@146aa000 {
compatible = "qcom,msm-imem";
reg = <0x146aa000 0x1000>;
ranges = <0x0 0x146aa000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
@ -503,6 +607,141 @@
#reset-cells = <1>;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_1_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<2097152 0>, <102400 0>, /* HS G3 RA */
<4194304 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<2097152 0>, <102400 0>, /* HS G3 RB */
<4194304 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
rpm-level = <3>;
spm-level = <3>;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <59>;
};
qos1 {
mask = <0x0f>;
vote = <65>;
};
};
clk_virt: interconnect {
compatible = "qcom,yupik-clk_virt";
#interconnect-cells = <1>;
@ -562,10 +801,47 @@
compatible = "qcom,yupik-epss-l3-cpu";
#interconnect-cells = <1>;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
system_pm {
compatible = "qcom,system-pm";
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
};
};
#include "shima-gdsc.dtsi"
#include "yupik-pinctrl.dtsi"
#include "yupik-pm.dtsi"
#include "yupik-stub-regulator.dtsi"
&gcc_pcie_0_gdsc {
@ -683,3 +959,5 @@
compatible = "regulator-fixed";
status = "ok"
};
#include "yupik-usb.dtsi"