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clk: qcom: Update the clk structure parameters for GPUCC/DISPCC clks

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Update the halt check for gpu clocks and remove the enable_safe_config
for dispcc for MONACO.

Change-Id: I97f6a1b7b5d7f8aef862455f0bbf23f9b8612d79
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
This commit is contained in:
Saurabh Sahu 2021-05-31 16:15:45 +05:30
commit 1fdcce591e
2 changed files with 2 additions and 3 deletions
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1
drivers/clk/qcom/dispcc-monaco.c
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@ -254,7 +254,6 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.enable_safe_config = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_4,

4
drivers/clk/qcom/gpucc-monaco.c
View file

@ -311,7 +311,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = {
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x418c,
.halt_check = BRANCH_HALT,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x418c,
.enable_mask = BIT(0),
@ -329,7 +329,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
static struct clk_branch gpu_cc_gx_cxo_clk = {
.halt_reg = 0x416c,
.halt_check = BRANCH_HALT,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x416c,
.enable_mask = BIT(0),