A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Add DPC property for SM6150"

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qctecmdr 2021-03-01 10:10:54 -08:00 • committed by Gerrit - the friendly Code Review server
commit 2fdf8ab987
3 changed files with 24 additions and 0 deletions
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8
qcom/sdmshrike.dtsi
View file

@ -50,6 +50,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
@ -74,6 +75,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
@ -92,6 +94,7 @@
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
@ -110,6 +113,7 @@
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
@ -128,6 +132,7 @@
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
@ -146,6 +151,7 @@
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
@ -164,6 +170,7 @@
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
@ -182,6 +189,7 @@
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 1 4>;

8
qcom/sm6150.dtsi
View file

@ -49,6 +49,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -74,6 +75,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -94,6 +96,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -113,6 +116,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -132,6 +136,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -151,6 +156,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
@ -170,6 +176,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
@ -189,6 +196,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1 2>;

8
qcom/sm8150.dtsi
View file

@ -54,6 +54,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
@ -75,6 +76,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
@ -91,6 +93,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
@ -107,6 +110,7 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
@ -123,6 +127,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <374>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
@ -139,6 +144,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <374>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
@ -155,6 +161,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <374>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
@ -171,6 +178,7 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
L2_7: l2-cache {