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[wifi 3.0] add firmware common files

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add firmware common files into separated project.
Included firmware common htt and wmi.
Included hardware common header files for napier and hawkeye

Change-Id: I8724057eb9aa21f7614231d1943177e780ed16b1
CRs-fixed: 1074308
This commit is contained in:
Leo Chang 2016-09-15 13:32:05 -07:00
commit 5e6ced2ea3
140 changed files with 133095 additions and 18953 deletions
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71
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* ============================================================================== */
/* This file contains the definitions of the basic atheros data types. */
/* It is used to map the data types in atheros files to a platform specific */
/* type. */
/* */
/* Author(s): ="Atheros" */
/* ============================================================================== */
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "osapi_linux.h"
#endif
/*=== the following primitives have the same definition for all platforms ===*/
#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
typedef char assertion_name[(predicate) ? 1 : -1]
/*
* If N is a power of 2, then N and N-1 are orthogonal
* (N-1 has all the least-significant bits set which are zero in N)
* so N ^ (N-1) = (N << 1) - 1
*/
#define A_COMPILE_TIME_ASSERT_IS_PWR2(assertion_name, value) \
A_COMPILE_TIME_ASSERT (assertion_name, \
(((value) ^ ((value)-1)) == ((value) << 1) - 1))
#ifndef __ubicom32__
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_CONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_CONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context)
#else
#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
os_malloc_NONCONSISTENT(osdev, size, pa, context, retry)
#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
OS_FREE_NONCONSISTENT(osdev, size, vaddr, pa, context)
#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context) \
OS_SYNC_SINGLE(osdev, pa, size, dir, context)
#endif /* ubicom32 */
#endif /* _OSAPI_H_ */

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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/*
* Shared USB definitions
*
*
*
*
*/
#ifndef __A_USB_DEFS_H__
#define __A_USB_DEFS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* USB endpoint definitions */
#define USB_EP_ADDR_APP_CTRL_IN 0x81
#define USB_EP_ADDR_APP_DATA_IN 0x82
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
#define USB_EP_ADDR_APP_DATA_HP_OUT 0x04
#define USB_CONTROL_REQ_SEND_BMI_CMD 1
#define USB_CONTROL_REQ_RECV_BMI_RESP 2
#define USB_CONTROL_REQ_DIAG_CMD 3
#define USB_CONTROL_REQ_DIAG_RESP 4
/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 64 */
#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE 252
#define HIF_BMI_MAX_TRANSFER_SIZE USB_CONTROL_MAX_BMI_TRANSFER_SIZE
/* 512 Bytes Maxp for High Speed for BULK EP */
#define USB_HS_BULK_MAXP_SIZE 0x200
/* 64 Bytes Maxp for Full Speed for BULK EP */
#define USB_FS_BULK_MAXP_SIZE 0x40
/* diagnostic command defnitions */
#define USB_CTRL_DIAG_CC_READ 0
#define USB_CTRL_DIAG_CC_WRITE 1
#define USB_CTRL_DIAG_CC_WARM_RESET 2
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
A_UINT32 Value;
A_UINT32 _pad[1];
} POSTPACK USB_CTRL_DIAG_CMD_WRITE;
typedef PREPACK struct {
A_UINT32 Cmd;
A_UINT32 Address;
} POSTPACK USB_CTRL_DIAG_CMD_READ;
typedef PREPACK struct {
A_UINT32 ReadValue;
} POSTPACK USB_CTRL_DIAG_RESP_READ;
#define USB_CTRL_MAX_DIAG_CMD_SIZE (sizeof(USB_CTRL_DIAG_CMD_WRITE))
#define USB_CTRL_MAX_DIAG_RESP_SIZE (sizeof(USB_CTRL_DIAG_RESP_READ))
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif

59
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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _APB_ATHR_WLAN_MAP_H_
#define _APB_ATHR_WLAN_MAP_H_
#define RTC_SOC_BASE_ADDRESS 0x00004000
#define RTC_WMAC_BASE_ADDRESS 0x00005000
#define MAC_COEX_BASE_ADDRESS 0x00006000
#define BT_COEX_BASE_ADDRESS 0x00007000
#define SOC_PCIE_BASE_ADDRESS 0x00008000
#define SOC_CORE_BASE_ADDRESS 0x00009000
#define WLAN_UART_BASE_ADDRESS 0x0000c000
#define WLAN_SI_BASE_ADDRESS 0x00010000
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define WLAN_MAC_BASE_ADDRESS 0x00020000
#define EFUSE_BASE_ADDRESS 0x00030000
#define FPGA_REG_BASE_ADDRESS 0x00039000
#define WLAN_UART2_BASE_ADDRESS 0x00054c00
#define CE_WRAPPER_BASE_ADDRESS 0x00057000
#define CE0_BASE_ADDRESS 0x00057400
#define CE1_BASE_ADDRESS 0x00057800
#define CE2_BASE_ADDRESS 0x00057c00
#define CE3_BASE_ADDRESS 0x00058000
#define CE4_BASE_ADDRESS 0x00058400
#define CE5_BASE_ADDRESS 0x00058800
#define CE6_BASE_ADDRESS 0x00058c00
#define CE7_BASE_ADDRESS 0x00059000
#define DBI_BASE_ADDRESS 0x00060000
#define WLAN_MBOX_BASE_ADDRESS 0x00068000
#define WLAN_DBG_UART_BASE_ADDRESS 0x00069000
#define USB_DMA_BASE_ADDRESS 0x0006a000
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */

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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __ATHDEFS_H__
#define __ATHDEFS_H__
/*
* This file contains definitions that may be used across both
* Host and Target software. Nothing here is module-dependent
* or platform-dependent.
*/
/*
* Generic error codes that can be used by hw, sta, ap, sim, dk
* and any other environments. Since these are enums, feel free to
* add any more codes that you need.
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED, /* Object was consumed */
A_CLONE, /* The buffer is cloned */
A_USB_ERROR, /* Rome USB Target error */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#endif /* __ATHDEFS_H__ */

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/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */

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/*
* Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef BIN_SIGN_H_
#define BIN_SIGN_H_
/* Signed binary MetaData */
typedef struct {
unsigned int magic_num;
unsigned int total_len;
unsigned int rampatch_len;
unsigned int product_id;
unsigned int patch_ver;
unsigned short sign_format_ver;
unsigned short sign_algorithm;
unsigned char reserved[8];
} SIGN_HEADER_T;
#endif /* BIN_SIGN_H_ */

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/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
* BMI is a very simple messaging interface used during initialization
* to read memory, write memory, execute code, and to define an
* application entry PC.
*
* It is used to download an application to AR6K, to provide
* patches to code that is already resident on AR6K, and generally
* to examine and modify state. The Host has an opportunity to use
* BMI only once during bootup. Once the Host issues a BMI_DONE
* command, this opportunity ends.
*
* The Host writes BMI requests to mailbox0, and reads BMI responses
* from mailbox0. BMI requests all begin with a command
* (see below for specific commands), and are followed by
* command-specific data.
*
* Flow control:
* The Host can only issue a command once the Target gives it a
* "BMI Command Credit", using AR6K Counter #4. As soon as the
* Target has completed a command, it issues another BMI Command
* Credit (so the Host can issue the next command).
*
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
/* BMI Commands */
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Capbility to write "segmented files" is provided for two reasons
* 1) backwards compatibility for certain situations where Hosts
* have limited flexibility
* 2) because it's darn convenient.
*
* A segmented file consists of a file header followed by an arbitrary number
* of segments. Each segment contains segment metadata -- a Target address and
* a length -- followed by "length" bytes of data. A segmented file ends with
* a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file
* is sent to the Target, firmware writes each segment to the specified address.
*
* Special cases:
* 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the
* specified address is used as a function entry point for a brief function
* with prototype "(void *)(void)". That function is called immediately.
* After execution of the function completes, firmware continues with the
* next segment. No data is expected when length=BMI_SGMTFILE_EXEC.
*
* 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then
* the specified address is established as the application start address
* so that a subsequent BMI_DONE jumps there.
*
* 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then
* the specified address is used as the (possibly compressed) length of board
* data, which is loaded into the proper Target address as specified by
* hi_board_data. In addition, the hi_board_data_initialized flag is set.
*
* A segmented file is sent to the Target using a sequence of 1 or more
* BMI_WRITE_MEMORY commands. The first such command must have
* address=BMI_SEGMENTED_WRITE_ADDR. Subsequent BMI_WRITE_MEMORY commands
* can use an arbitrary address. In each BMI_WRITE_MEMORY command, the
* length specifies the number of data bytes transmitted (except for the
* special cases listed above).
*
* Alternatively, a segmented file may be sent to the Target using a
* BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR
* followed by a series of BMI_LZ_DATA commands that each send the next portion
* of the segmented file.
*
* The data segments may be lz77 compressed. In this case, the segmented file
* header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set. Note that segmented
* file METAdata is never compressed; only the data segments themselves are
* compressed. There is no way to mix compressed and uncompressed data segments
* in a single segmented file. Compressed (or uncompressed) segments are handled
* by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands. (Compression is an
* attribute of the segmented file rather than of the command used to transmit
* it.)
*/
#define BMI_SEGMENTED_WRITE_ADDR 0x1234
/* File header for a segmented file */
struct bmi_segmented_file_header {
A_UINT32 magic_num;
A_UINT32 file_flags;
};
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_FLAG_COMPRESS 1
/* Metadata for a segmented file segment */
struct bmi_segmented_metadata {
A_UINT32 addr;
A_UINT32 length;
};
/* Special values for bmi_segmented_metadata.length (all have high bit set) */
#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */
#define BMI_SGMTFILE_BDDATA 0xfffffffe /* Board Data segment */
#define BMI_SGMTFILE_BEGINADDR 0xfffffffd /* set beginning address */
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Note: In order to support the segmented file feature
* (see BMI_WRITE_MEMORY), when the address specified in a
* BMI_EXECUTE command matches (same physical address)
* BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution
* begins at the address specified by hi_app_start.
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
#define BMI_READ_SOC_WORD 6
/*
* Semantics: Read a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
#define BMI_WRITE_SOC_WORD 7
/*
* Semantics: Write a 32-bit Target SOC word.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
*
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
*
* Response format2 (intermediate firmware, during transition):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*
* Response format3 (newest firmware)
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
/* size of this structure */
A_UINT32 target_info_byte_count;
A_UINT32 target_ver;
A_UINT32 target_type;
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_UNKNOWN 0
#define TARGET_TYPE_AR6001 1
#define TARGET_TYPE_AR6002 2
#define TARGET_TYPE_AR6003 3
#define TARGET_TYPE_AR6004 5
#define TARGET_TYPE_AR6006 6
#define TARGET_TYPE_AR9888 7
#define TARGET_TYPE_AR6320 8
#define TARGET_TYPE_AR900B 9
/* For attach Peregrine 2.0 board target_reg_tbl only */
#define TARGET_TYPE_AR9888V2 10
/* For attach Rome1.0 target_reg_tbl only*/
#define TARGET_TYPE_AR6320V1 11
/* For Rome2.0/2.1 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V2 12
/* For Rome3.0 target_reg_tbl ID*/
#define TARGET_TYPE_AR6320V3 13
/* For Tufello1.0 target_reg_tbl ID*/
#define TARGET_TYPE_QCA9377V1 14
/* cascade */
#define TARGET_TYPE_QCA9984 15
/* dakota */
#define TARGET_TYPE_IPQ4019 16
/* besra */
#define TARGET_TYPE_QCA9888 17
/* For Adrastea target */
#define TARGET_TYPE_ADRASTEA 19
extern void target_register_tbl_attach(A_UINT32 target_type);
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
#define BMI_SIGN_STREAM_START 17
/*
* Semantics: Trigger target start/end binary signature verification
* flow.
* Request format:
* A_UINT32 command (BMI_SIGN_STREAM_START)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
/* TBDXXX: Need a better place for these */
#define BMI_CE_NUM_TO_TARG 0
#define BMI_CE_NUM_TO_HOST 1
#endif /* __BMI_MSG_H__ */

49
fw/cepci.h Executable file → Normal file
View file

@ -33,7 +33,6 @@
* Structures shared between Host software and Target firmware.
*/
/*
* Total number of PCIe MSI interrupts requested for all interrupt sources.
* PCIe standard forces this to be a power of 2.
@ -55,9 +54,6 @@
#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
#define MSI_ASSIGN_CE_MAX 7
/*
* PCI-specific Target state. Much of this may be of interest
* to the Host so HOST_INTEREST->hi_interconnect_state points
@ -66,49 +62,50 @@
* required to initialize pipe_cfg_addr and svc_to_pipe_map.
*/
struct pcie_state_s {
A_UINT32 pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
/* NB: CE_pipe_config[CE_COUNT] */
A_UINT32 svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
A_UINT32 MSI_requested; /* number of MSI interrupts requested */
A_UINT32 MSI_granted; /* number of MSI interrupts granted */
A_UINT32 MSI_addr; /* Message Signalled Interrupt address */
A_UINT32 MSI_data; /* Base data */
A_UINT32 MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
uint32_t MSI_requested; /* number of MSI interrupts requested */
uint32_t MSI_granted; /* number of MSI interrupts granted */
uint32_t MSI_addr; /* Message Signalled Interrupt address */
uint32_t MSI_data; /* Base data */
uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
MSI data for other interrupts are
in various SoC registers */
A_UINT32 power_mgmt_method; /* PCIE_PWR_METHOD_* */
A_UINT32 config_flags; /* PCIE_CONFIG_FLAG_* */
uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
};
/*
* PCIE_CONFIG_FLAG definitions
*/
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#if defined(AR900B)
#define CE_PKTLOG_PIPE 8 /* used by both host and target side */
#endif
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_GATING_L1 0x0000001
#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
#define PCIE_CONFIG_FLAG_CLK_REQ_L1 0x0000008
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*/
struct CE_pipe_config {
A_UINT32 pipenum;
A_UINT32 pipedir;
A_UINT32 nentries;
A_UINT32 nbytes_max;
A_UINT32 flags;
A_UINT32 reserved;
uint32_t pipenum;
uint32_t pipedir;
uint32_t nentries;
uint32_t nbytes_max;
uint32_t flags;
uint32_t reserved;
};
#endif /* __CEPCI_H__ */

88
fw/dbglog.h Executable file → Normal file
View file

@ -32,83 +32,87 @@
#include "athstartpack.h"
#endif
#include <wlan_module_ids.h>
#include "wlan_module_ids.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
/* Bit 0-15. Contains bit 8-23 of the LF0 timer */
#define DBGLOG_TIMESTAMP_MASK 0xFFFFFFFF
#define DBGLOG_DBGID_OFFSET 0
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_DBGID_MASK 0x000003FF /* Bit 0-9 */
/* Upper limit is width of mask */
#define DBGLOG_DBGID_NUM_MAX 256
#define DBGLOG_MODULEID_OFFSET 10
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
#define DBGLOG_MODULEID_NUM_MAX 32 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_MASK 0x0003FC00 /* Bit 10-17 */
/* Upper limit is width of mask */
#define DBGLOG_MODULEID_NUM_MAX 32
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25*/
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_VDEVID_OFFSET 18
#define DBGLOG_VDEVID_MASK 0x03FC0000 /* Bit 20-25 */
#define DBGLOG_VDEVID_NUM_MAX 16
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
#define DBGLOG_NUM_ARGS_MAX 9 /* it is bcoz of limitation
of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_NUM_ARGS_OFFSET 26
#define DBGLOG_NUM_ARGS_MASK 0xFC000000 /* Bit 26-31 */
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */
#define DBGLOG_NUM_ARGS_MAX 9
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
#define DBGLOG_GET_DBGID(arg) \
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
#define DBGLOG_GET_MODULEID(arg) \
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
#define DBGLOG_GET_VDEVID(arg) \
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_NUMARGS(arg) \
((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
#define DBGLOG_GET_TIME_STAMP(arg) \
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
/* Debug Log levels*/
typedef enum {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
}DBGLOG_LOG_LVL;
enum DBGLOG_LOG_LVL {
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
DBGLOG_INFO_LVL_2,
DBGLOG_WARN,
DBGLOG_ERR,
DBGLOG_LVL_MAX
};
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_H_ */

118
fw/dbglog_id.h Executable file → Normal file
View file

@ -41,21 +41,20 @@ extern "C" {
*/
/*
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
* The target state machine framework will send dbglog messages on behalf on
* other modules. We do this do avoid each module adding identical dbglog code
* for state transitions and event processing. We also don't want to force each
* module to define the the same XXX_DBGID_SM_MSG with the same value below.
* Instead we use a special ID that the host dbglog code recognizes as a
* message sent by the SM on behalf on another module.
*/
#define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START 0
#define INF_ASSERTION_FAILED 1
#define INF_TARGET_ID 2
#define INF_TARGET_MEM_REMAING 3
#define INF_TARGET_MEM_REMAING 3
#define INF_TARGET_MEM_EXT_REMAING 4
#define INF_TARGET_MEM_ALLOC_TRACK 5
#define INF_TARGET_MEM_ALLOC_RAM 6
@ -298,7 +297,7 @@ extern "C" {
#define WHAL_ERROR_XTAL_SET 49
#define WHAL_DBGID_DEFINITION_END 50
#define COEX_DEBUGID_START 0
#define COEX_DEBUGID_START 0
#define BTCOEX_DBG_MCI_1 1
#define BTCOEX_DBG_MCI_2 2
#define BTCOEX_DBG_MCI_3 3
@ -688,6 +687,7 @@ extern "C" {
#define WAL_DBGID_TX_SCH_REGISTER_TIDQ 12
#define WAL_DBGID_TX_SCH_UNREGISTER_TIDQ 13
#define WAL_DBGID_TX_SCH_TICKLE_TIDQ 14
#define WAL_DBGID_XCESS_FAILURES 15
#define WAL_DBGID_AST_ADD_WDS_ENTRY 16
#define WAL_DBGID_AST_DEL_WDS_ENTRY 17
@ -780,6 +780,7 @@ extern "C" {
#define ANI_DBGID_MRC_CCK 10
#define ANI_DBGID_SELF_CORR_LOW 11
#define ANI_DBGID_ENABLE 12
#define ANI_DBGID_CURRENT_LEVEL 13
#define ANI_DBGID_POLL_PERIOD 14
#define ANI_DBGID_LISTEN_PERIOD 15
@ -864,8 +865,7 @@ extern "C" {
#define P2P_GO_BCN_TX_COMP 38
#define P2P_DBGID_DEFINITION_END 39
//CSA modules DBGIDs
/* CSA modules DBGIDs */
#define CSA_DBGID_DEFINITION_START 0
#define CSA_OFFLOAD_POOL_INIT 1
#define CSA_OFFLOAD_REGISTER_VDEV 2
@ -925,7 +925,6 @@ extern "C" {
#define WOW_IBSS_VDEV_ALLOW 23
#define WOW_DBGID_DEFINITION_END 24
/* SWBMISS module DBGIDs */
#define SWBMISS_DBGID_DEFINITION_START 0
#define SWBMISS_ENABLED 1
@ -1145,6 +1144,7 @@ extern "C" {
#define RTT_CHANNEL_SWITCH_PREEMPT 18
#define RTT_CHANNEL_SWITCH_STOP 19
#define RTT_TIMER_START 20
#define RTT_FTM_PARAM_INFO 21
#define RTT_RX_TM_FRAME 22
#define RTT_INITR_TSTAMP 23
@ -1186,7 +1186,7 @@ extern "C" {
#define WLAN_PHTERR_DFS_DBDID_FILTER_STATUS 5
#define WLAN_PHYERR_DFS_DBGID_DEFINITION_END 6
/* RMC DBGIDs*/
/* RMC DBGIDs */
#define RMC_DBGID_DEFINITION_START 0
#define RMC_CREATE_INSTANCE 1
#define RMC_DELETE_INSTANCE 2
@ -1246,7 +1246,6 @@ extern "C" {
#define WLAN_STATS_DBGID_RSSI 6
#define WLAN_STATS_DBGID_CNE_RSSI 7
#define WLAN_STATS_DBGID_DEFINITION_END 8
/* NAN DBGIDs */
#define NAN_DBGID_START 0
@ -1491,46 +1490,51 @@ extern "C" {
#define NAN_DBGID_BEACON_RX_LAST (NAN_DBGID_OTA_PKT_LAST + 20)
/* NaN Datapath Timekeeper debug IDs */
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST /* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0) /* 136 */
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1) /* 137 */
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2) /* 138 */
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3) /* 139 */
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4) /* 140 */
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5) /* 141 */
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6) /* 142 */
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7) /* 143 */
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8) /* 144 */
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9) /* 145 */
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10) /* 146 */
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11) /* 147 */
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12) /* 148 */
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13) /* 149 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14) /* 150 */
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15) /* 151 */
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16) /* 152 */
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17) /* 153 */
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18) /* 154 */
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19) /* 155 */
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20) /* 156 */
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21) /* 157 */
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22) /* 158 */
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23) /* 159 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24) /* 160 */
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25) /* 161 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26) /* 162 */
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27) /* 163 */
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28) /* 164 */
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29) /* 165 */
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30) /* 166 */
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31) /* 167 */
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32) /* 168 */
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33) /* 169 */
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34) /* 170 */
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35) /* 171 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36) /* 172 */
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37) /* 173 */
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38) /* 174 */
/* 116 + 20 = 136 */
#define NAN_DBGID_TMKR_BASE NAN_DBGID_BEACON_RX_LAST
/* 136 */
#define NAN_DBGID_TMKR_INIT (NAN_DBGID_TMKR_BASE + 0)
#define NAN_DBGID_TMKR_OPEN (NAN_DBGID_TMKR_BASE + 1)
#define NAN_DBGID_TMKR_CLOSE (NAN_DBGID_TMKR_BASE + 2)
#define NAN_DBGID_TMKR_NEGOTIATE (NAN_DBGID_TMKR_BASE + 3)
#define NAN_DBGID_TMKR_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 4)
#define NAN_DBGID_TMKR_UNITTEST (NAN_DBGID_TMKR_BASE + 5)
#define NAN_DBGID_TMKR_LF_TMR_HNDLR (NAN_DBGID_TMKR_BASE + 6)
#define NAN_DBGID_TMKR_DEINIT (NAN_DBGID_TMKR_BASE + 7)
#define NAN_DBGID_TMKR_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 8)
#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 9)
#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 10)
#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 11)
#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 12)
#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 13)
/* 150 */
#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT (NAN_DBGID_TMKR_BASE + 14)
#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 15)
#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP (NAN_DBGID_TMKR_BASE + 16)
#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG (NAN_DBGID_TMKR_BASE + 17)
#define NAN_DBGID_TMKR_POPULATE_MASTER (NAN_DBGID_TMKR_BASE + 18)
#define NAN_DBGID_TMKR_ALLOCATE_SLOTS (NAN_DBGID_TMKR_BASE + 19)
#define NAN_DBGID_TMKR_RELEASE_SLOTS (NAN_DBGID_TMKR_BASE + 20)
#define NAN_DBGID_TMKR_ENABLE (NAN_DBGID_TMKR_BASE + 21)
#define NAN_DBGID_TMKR_DISABLE (NAN_DBGID_TMKR_BASE + 22)
#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW (NAN_DBGID_TMKR_BASE + 23)
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 24)
#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 25)
/* 162 */
#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING (NAN_DBGID_TMKR_BASE + 26)
#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW (NAN_DBGID_TMKR_BASE + 27)
#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME (NAN_DBGID_TMKR_BASE + 28)
#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL (NAN_DBGID_TMKR_BASE + 29)
#define NAN_DBGID_TMKR_SCHEDULE_EVENT (NAN_DBGID_TMKR_BASE + 30)
#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 31)
#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 32)
#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT (NAN_DBGID_TMKR_BASE + 33)
#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT (NAN_DBGID_TMKR_BASE + 34)
#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 35)
/* 172 */
#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT (NAN_DBGID_TMKR_BASE + 36)
#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT (NAN_DBGID_TMKR_BASE + 37)
#define NAN_DBGID_TMKR_LAST (NAN_DBGID_TMKR_BASE + 38)
#define NAN_DBGID_END (NAN_DBGID_TMKR_LAST)
@ -1631,6 +1635,7 @@ extern "C" {
#define ERE_DBGID_STATS_RX 12
#define ERE_DBGID_DEFINITION_END 13
/* IDs 14 - 251 reserved for ERE */
/* Timekeeper debug IDs */
#define TIMEKEEPER_INIT 252
#define TIMEKEEPER_OPEN 253
@ -1736,9 +1741,8 @@ extern "C" {
#define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND 1
#define WLAN_MODULE_QBOOST_DEFINITION_END 2
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_ID_H_ */

154
fw/efuse_reg.h Normal file
View file

@ -0,0 +1,154 @@
/*
* Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014
#define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014
#define VDDQ_HOLD_TIME_REG_V_MSB 31
#define VDDQ_HOLD_TIME_REG_V_LSB 0
#define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff
#define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB)
#define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000018
#define RD_STROBE_PW_REG_OFFSET 0x00000018
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x0000001c
#define PG_STROBE_PW_REG_OFFSET 0x0000001c
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020
#define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31
#define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0
#define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff
#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB)
#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK)
#define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024
#define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024
#define STROBE_PULSE_INTERVAL_REG_V_MSB 31
#define STROBE_PULSE_INTERVAL_REG_V_LSB 0
#define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff
#define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB)
#define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB)
#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK)
#define EFUSE_INTF0_ADDRESS 0x00000800
#define EFUSE_INTF0_OFFSET 0x00000800
#define EFUSE_INTF0_R_MSB 31
#define EFUSE_INTF0_R_LSB 0
#define EFUSE_INTF0_R_MASK 0xffffffff
#define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB)
#define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK)
#define EFUSE_INTF1_ADDRESS 0x00001000
#define EFUSE_INTF1_OFFSET 0x00001000
#define EFUSE_INTF1_R_MSB 31
#define EFUSE_INTF1_R_LSB 0
#define EFUSE_INTF1_R_MASK 0xffffffff
#define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB)
#define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int vddq_hold_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
volatile unsigned int pgenb_setup_hold_time_reg;
volatile unsigned int strobe_pulse_interval_reg;
volatile unsigned int csb_addr_load_setup_hold_reg;
unsigned char pad0[2004]; /* pad to 0x800 */
volatile unsigned int efuse_intf0[512];
volatile unsigned int efuse_intf1[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */

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/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _ENET__H_
#define _ENET__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define ETHERNET_ADDR_LEN 6 /* bytes */
#define ETHERNET_TYPE_LEN 2 /* bytes - length of the Ethernet type field */
struct ethernet_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 ethertype[ETHERNET_TYPE_LEN];
};
#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t))
#define ETHERNET_CRC_LEN 4 /* bytes - length of the Ethernet CRC */
#define ETHERNET_MAX_LEN 1518 /* bytes */
#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN))
struct llc_snap_hdr_t {
A_UINT8 dsap;
A_UINT8 ssap;
A_UINT8 cntl;
A_UINT8 org_code[3];
A_UINT8 ethertype[2];
};
#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
(offsetof(struct llc_snap_hdr_t, ethertype[0]))
#define ETHERTYPE_VLAN_LEN 4
struct ethernet_vlan_hdr_t {
A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
A_UINT8 src_addr[ETHERNET_ADDR_LEN];
A_UINT8 vlan_tpid[2];
A_UINT8 vlan_tci[2];
A_UINT8 ethertype[2];
};
#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \
((typeorlen) == ETHERTYPE_PAE || \
(typeorlen) == ETHERTYPE_WAI)
#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
#ifndef ETHERTYPE_IPV4
#define ETHERTYPE_IPV4 0x0800 /* Internet Protocol, Version 4 (IPv4) */
#endif
#ifndef ETHERTYPE_AARP
#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */
#endif
#ifndef ETHERTYPE_IPX
#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */
#endif
#ifndef ETHERTYPE_ARP
#define ETHERTYPE_ARP 0x0806 /* Address Resolution Protocol (ARP) */
#endif
#ifndef ETHERTYPE_RARP
#define ETHERTYPE_RARP 0x8035 /* Reverse Address Resolution Protocol (RARP) */
#endif
#ifndef ETHERTYPE_VLAN
#define ETHERTYPE_VLAN 0x8100 /* VLAN TAG protocol */
#endif
#ifndef ETHERTYPE_SNMP
#define ETHERTYPE_SNMP 0x814C /* Simple Network Management Protocol (SNMP) */
#endif
#ifndef ETHERTYPE_IPV6
#define ETHERTYPE_IPV6 0x86DD /* Internet Protocol, Version 6 (IPv6) */
#endif
#ifndef ETHERTYPE_PAE
#define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */
#endif
#ifndef ETHERTYPE_WAI
#define ETHERTYPE_WAI 0x88B4 /* WAPI */
#endif
#ifndef ETHERTYPE_TDLS
#define ETHERTYPE_TDLS 0x890D /* TDLS */
#endif
#define LLC_SNAP_LSAP 0xaa
#define LLC_UI 0x3
#define RFC1042_SNAP_ORGCODE_0 0x00
#define RFC1042_SNAP_ORGCODE_1 0x00
#define RFC1042_SNAP_ORGCODE_2 0x00
#define BTEP_SNAP_ORGCODE_0 0x00
#define BTEP_SNAP_ORGCODE_1 0x00
#define BTEP_SNAP_ORGCODE_2 0xf8
#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP && \
(_llc)->ssap == LLC_SNAP_LSAP && \
(_llc)->cntl == LLC_UI)
#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
(_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
(_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
#endif /* _ENET__H_ */

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/*
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H
#define EPPING_TEST_H
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
#endif
#define EPPING_RSVD_FILL 0xCC
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host */
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; }
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3) /* target will not fill buffers */
A_UINT16 Context; /* flags */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* EPPING_TEST_H */

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/*
* Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef ATHR_WIN_NWF
#pragma warning(disable:4214)
#endif
#undef MS
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#undef WO
#define WO(_f) ((_f ## _OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define HTC_WRITE32(_addr, _val) \
(*(A_UINT32 *)(_addr) = (_val))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#endif
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/****** DANGER DANGER ***************
*
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
*
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
*
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR {
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/
ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/
reserved : 16; /*used by bundle processing in SDIO systems*/
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
#define HTC_FRAME_HDR_ENDPOINTID_LSB 0
#define HTC_FRAME_HDR_ENDPOINTID_MASK 0x000000ff
#define HTC_FRAME_HDR_ENDPOINTID_OFFSET 0x00000000
#define HTC_FRAME_HDR_FLAGS_LSB 8
#define HTC_FRAME_HDR_FLAGS_MASK 0x0000ff00
#define HTC_FRAME_HDR_FLAGS_OFFSET 0x00000000
#define HTC_FRAME_HDR_PAYLOADLEN_LSB 16
#define HTC_FRAME_HDR_PAYLOADLEN_MASK 0xffff0000
#define HTC_FRAME_HDR_PAYLOADLEN_OFFSET 0x00000000
#define HTC_FRAME_HDR_CONTROLBYTES0_LSB 0
#define HTC_FRAME_HDR_CONTROLBYTES0_MASK 0x000000ff
#define HTC_FRAME_HDR_CONTROLBYTES0_OFFSET 0x00000004
#define HTC_FRAME_HDR_CONTROLBYTES1_LSB 8
#define HTC_FRAME_HDR_CONTROLBYTES1_MASK 0x0000ff00
#define HTC_FRAME_HDR_CONTROLBYTES1_OFFSET 0x00000004
#define HTC_FRAME_HDR_RESERVED_LSB 16
#define HTC_FRAME_HDR_RESERVED_MASK 0xffff0000
#define HTC_FRAME_HDR_RESERVED_OFFSET 0x00000004
/* frame header flags */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xFC) /* bits 7..2 */
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 2
/*
* To be compatible with an older definition of a smaller (4-bit)
* bundle count field, the bundle count is stored in a segmented
* format - the 4 LSbs of the bundle count value are stored in bits 5:2
* of the BUNDLE_CNT field, which is bits 7:4 of the HTC_FLAGS word;
* the next 2 bits of the bundle count value are stored in bits 1:0 of
* the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word.
*/
#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x) \
((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x) \
((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \
(HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_HDR_ALIGNMENT_PADDING \
(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
/* HTC control message IDs */
#define HTC_MSG_READY_ID 1
#define HTC_MSG_CONNECT_SERVICE_ID 2
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
#define HTC_MSG_SETUP_COMPLETE_ID 4
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
#define HTC_MSG_SEND_SUSPEND_COMPLETE 6
#define HTC_MSG_NACK_SUSPEND 7
#define HTC_MSG_WAKEUP_FROM_SUSPEND_ID 8
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
/* base message ID header */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
#define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT32 MessageID : 16, /* ID */
CreditCount : 16; /* number of credits the target can offer */
A_UINT32 CreditSize : 16, /* size of each credit */
MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
_Pad1 : 8;
} POSTPACK HTC_READY_MSG;
#define HTC_READY_MSG_MESSAGEID_LSB 0
#define HTC_READY_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_READY_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITCOUNT_LSB 16
#define HTC_READY_MSG_CREDITCOUNT_MASK 0xffff0000
#define HTC_READY_MSG_CREDITCOUNT_OFFSET 0x00000000
#define HTC_READY_MSG_CREDITSIZE_LSB 0
#define HTC_READY_MSG_CREDITSIZE_MASK 0x0000ffff
#define HTC_READY_MSG_CREDITSIZE_OFFSET 0x00000004
#define HTC_READY_MSG_MAXENDPOINTS_LSB 16
#define HTC_READY_MSG_MAXENDPOINTS_MASK 0x00ff0000
#define HTC_READY_MSG_MAXENDPOINTS_OFFSET 0x00000004
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT32 HTCVersion : 8, MaxMsgsPerHTCBundle : 8, reserved : 16;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_READY_EX_MSG_HTCVERSION_LSB 0
#define HTC_READY_EX_MSG_HTCVERSION_MASK 0x000000ff
#define HTC_READY_EX_MSG_HTCVERSION_OFFSET sizeof(HTC_READY_MSG)
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_LSB 8
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_MASK 0x0000ff00
#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET sizeof(HTC_READY_MSG)
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
/* service ID of the service to connect to */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 ConnectionFlags : 16, /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)
/* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
/* disable credit flow control on a specific service */
#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL (1 << 3)
/* enable htc schedule on a specific service */
#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE (1 << 4)
ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_LSB 0
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_LSB 16
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_MASK 0x00ff0000
#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_OFFSET 0x00000004
#define HTC_SET_RECV_ALLOC_SHIFT 8
#define HTC_SET_RECV_ALLOC_MASK 0xFF00
#define HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(value) (((A_UINT8)value) << HTC_SET_RECV_ALLOC_SHIFT)
#define HTC_CONNECT_FLAGS_GET_RECV_ALLOCATION(value) (A_UINT8)(((value) & HTC_SET_RECV_ALLOC_MASK) >> HTC_SET_RECV_ALLOC_SHIFT)
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
/* service ID that the connection request was made */
A_UINT32 MessageID:16, service_id:16;
A_UINT32 Status : 8, /* service connection status */
EndpointID : 8, /* assigned endpoint ID */
MaxMsgSize : 16; /* maximum expected message size on this endpoint */
A_UINT32 ServiceMetaLength : 8, /* length of meta data that follows */
_Pad1 : 8, reserved : 16;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_OFFSET 0x00000000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_LSB 8
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_MASK 0x0000ff00
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_LSB 16
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_MASK 0xffff0000
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_OFFSET 0x00000004
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_LSB 0
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_MASK 0x000000ff
#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET 0x00000000
/* extended setup completion message */
typedef PREPACK struct {
A_UINT32 MessageID : 16, reserved : 16;
A_UINT32 SetupFlags : 32;
A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8;
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_OFFSET 0x00000000
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_MASK 0xffffffff
#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_OFFSET 0x00000004
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_LSB 0
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_MASK 0x000000ff
#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_LSB 8
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_MASK 0x0000ff00
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_LSB 16
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_MASK 0x00ff0000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_LSB 24
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK 0xff000000
#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET 0x00000008
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) /* enable recv bundling from target */
#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1) /* disable credit based flow control,
only supported on some interconnects */
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
#define HTC_RECORD_NULL 0
#define HTC_RECORD_CREDITS 1
#define HTC_RECORD_LOOKAHEAD 2
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT32 RecordID : 8, /* Record ID */
Length : 8, /* Length of record */
reserved : 16;
} POSTPACK HTC_RECORD_HDR;
#define HTC_RECORD_HDR_RECORDID_LSB 0
#define HTC_RECORD_HDR_RECORDID_MASK 0x000000ff
#define HTC_RECORD_HDR_RECORDID_OFFSET 0x00000000
#define HTC_RECORD_HDR_LENGTH_LSB 8
#define HTC_RECORD_HDR_LENGTH_MASK 0x0000ff00
#define HTC_RECORD_HDR_LENGTH_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 EndpointID : 8, /* Endpoint that owns these credits */
Credits : 8, /* credits to report since last report */
reserved : 16;
} POSTPACK HTC_CREDIT_REPORT;
#define HTC_CREDIT_REPORT_ENDPOINTID_LSB 0
#define HTC_CREDIT_REPORT_ENDPOINTID_MASK 0x000000ff
#define HTC_CREDIT_REPORT_ENDPOINTID_OFFSET 0x00000000
#define HTC_CREDIT_REPORT_CREDITS_LSB 8
#define HTC_CREDIT_REPORT_CREDITS_MASK 0x0000ff00
#define HTC_CREDIT_REPORT_CREDITS_OFFSET 0x00000000
typedef PREPACK struct {
A_UINT32 PreValid : 8, /* pre valid guard */
reserved0 : 24;
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
A_UINT32 PostValid : 8, /* post valid guard */
reserved1 : 24;
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
#define HTC_LOOKAHEAD_REPORT_PREVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_PREVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_PREVALID_OFFSET 0x00000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000004
#define HTC_LOOKAHEAD_REPORT_POSTVALID_LSB 0
#define HTC_LOOKAHEAD_REPORT_POSTVALID_MASK 0x000000ff
#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET 0x00000008
typedef PREPACK struct {
A_UINT32 LookAhead0 : 8, /* 4 byte lookahead */
LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB 0
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK 0x000000ff
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB 8
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK 0x0000ff00
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB 16
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK 0x00ff0000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET 0x00000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB 24
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK 0xff000000
#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET 0x00000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

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/*
* Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __HTC_SERVICES_H__
#define __HTC_SERVICES_H__
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
NMI_SERVICE_GROUP = 2,
HTT_SERVICE_GROUP = 3,
CFG_NV_SERVICE_GROUP = 4,
WDI_IPA_SERVICE_GROUP = 5,
PACKET_LOG_SERVICE_GROUP = 6,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
} HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define WMI_MAX_SERVICES 5
#define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
#define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
#define HTT_DATA_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2)
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#define CFG_NV_SVC MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0)
/*
* Directions for interconnect pipe configuration.
* These definitions may be used during configuration and are shared
* between Host and Target.
*
* Pipe Directions are relative to the Host, so PIPEDIR_IN means
* "coming IN over air through Target to Host" as with a WiFi Rx operation.
* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
* over the interconnect.
*/
typedef A_UINT32 PIPEDIR;
#define PIPEDIR_NONE 0
#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
#define PIPEDIR_INOUT 3 /* bidirectional, target to target */
#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */
#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
A_UINT32 service_id;
A_UINT32 pipedir;
A_UINT32 pipenum;
};
#endif /*HTC_SERVICES_H_ */

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@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@ -35,43 +35,43 @@
#define _HTT_COMMON_H_
enum htt_sec_type {
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
htt_sec_type_none,
htt_sec_type_wep128,
htt_sec_type_wep104,
htt_sec_type_wep40,
htt_sec_type_tkip,
htt_sec_type_tkip_nomic,
htt_sec_type_aes_ccmp,
htt_sec_type_wapi,
htt_sec_type_aes_ccmp_256,
htt_sec_type_aes_gcmp,
htt_sec_type_aes_gcmp_256,
/* keep this last! */
htt_num_sec_types
/* keep this last! */
htt_num_sec_types
};
enum htt_rx_ind_mpdu_status {
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
HTT_RX_IND_MPDU_STATUS_OK,
HTT_RX_IND_MPDU_STATUS_ERR_FCS,
HTT_RX_IND_MPDU_STATUS_ERR_DUP,
HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
/*
* MISC: discard for unspecified reasons.
* Leave this enum value last.
*/
HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
};
#define HTT_INVALID_PEER 0xffff
@ -103,18 +103,31 @@ enum htt_rx_ind_mpdu_status {
* type rather than L2 header type.
*/
enum htt_pkt_type {
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
htt_pkt_type_raw = 0,
htt_pkt_type_native_wifi = 1,
htt_pkt_type_ethernet = 2,
htt_pkt_type_mgmt = 3,
htt_pkt_type_eth2 = 4,
/* keep this last */
htt_pkt_num_types
/* keep this last */
htt_pkt_num_types
};
/*
* TX MSDU ID partition -
* FW supports bigger MSDU ID partition which is defined as
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* When both host and FW support new partition, FW uses
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
* If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_READY and WMI_INIT
*/
#define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
#define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN 3000
#define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
/* 8192 = 0xr2000 */
#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192
/* 12288 = 0x3000 */
#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN 12288
#endif /* _HTT_COMMON_H_ */

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/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IP_PROT__H_
#define _IP_PROT__H_
#define IP_PROTOCOL_ICMP 0x01 /* Internet Control Message Protocol */
#define IP_PROTOCOL_IGMP 0x02 /* Internet Group Management Protocol */
#define IP_PROTOCOL_IPV4 0x04 /* IPv4 (encapsulation) */
#define IP_PROTOCOL_TCP 0x06 /* Transmission Control Protocol */
#define IP_PROTOCOL_UDP 0x11 /* User Datagram Protocol */
#define IP_PROTOCOL_RDP 0x1B /* Reliable Datagram Protocol */
#define IP_PROTOCOL_IPV6 0x29 /* IPv6 (encapsulation) */
#define IP_PROTOCOL_IPV6_ROUTE 0x2B /* Routing Header for IPv6 */
#define IP_PROTOCOL_IPV6_FRAG 0x2C /* Fragment Header for IPv6 */
#define IP_PROTOCOL_RSVP 0x2E /* Resource Reservation Protocol */
#define IP_PROTOCOL_GRE 0x2F /* Generic Routing Encapsulation */
#define IP_PROTOCOL_MHRP 0x30 /* Mobile Host Routing Protocol */
#define IP_PROTOCOL_BNA 0x31 /* BNA */
#define IP_PROTOCOL_ESP 0x32 /* Encapsulating Security Payload */
#define IP_PROTOCOL_MOBILE 0x37 /* IP Mobility (Min Encap) */
#define IP_PROTOCOL_IPV6_ICMP 0x3A /* ICMP for IPv6 */
#define IP_PROTOCOL_IPV6_NONXT 0x3B /* No Next Header for IPv6 */
#define IP_PROTOCOL_IPV6_OPTS 0x3C /* Destination Options for IPv6 */
#define IP_PROTOCOL_IPCOMP 0x6C /* IP Payload Compression Protocol */
#define IP_PROTOCOL_L2TP 0x73 /* Layer Two Tunneling Protocol Version 3 */
#define IP_PROTOCOL_SMP 0x79 /* Simple Message Protocol */
#define IP_PROTOCOL_SCTP 0x84 /* Stream Control Transmission Protocol */
#define IP_PROTOCOL_SHIM6 0x8C /* Site Multihoming by IPv6 Intermediation */
/* IPv6 ICMP types */
#define IPV6_ICMP_TYPE_MLD 0x8F
#endif /* _IP_PROT__H_ */

55
fw/ipv4.h Normal file
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@ -0,0 +1,55 @@
/*
* Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _IPV4__H_
#define _IPV4__H_
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#endif
#define IPV4_ADDR_LEN 4 /* bytes */
struct ipv4_hdr_t {
A_UINT8 ver_hdrlen; /* version and hdr length */
A_UINT8 tos; /* type of service */
A_UINT8 len[2]; /* total length */
A_UINT8 id[2];
A_UINT8 flags_fragoff[2]; /* flags and fragment offset field */
A_UINT8 ttl; /* time to live */
A_UINT8 protocol;
A_UINT8 hdr_checksum[2];
A_UINT8 src_addr[IPV4_ADDR_LEN];
A_UINT8 dst_addr[IPV4_ADDR_LEN];
};
#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t))
#define IPV4_HDR_OFFSET_PROTOCOL (offsetof(struct ipv4_hdr_t, protocol))
#define IPV4_HDR_OFFSET_DST_ADDR (offsetof(struct ipv4_hdr_t, dst_addr[0]))
#endif /* _IPV4__H_ */

184
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@ -0,0 +1,184 @@
/*
* Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
/**
* @file ol_fw_tx_dbg.h
*
* @details data structs used for uploading summary info about the FW's tx
*/
#ifndef _OL_FW_TX_DBG__H_
#define _OL_FW_TX_DBG__H_
/*
* Undef ATH_SUPPORT_FW_TX_DBG to remove the FW tx debug feature.
* Removing the FW tx debug feature saves a modest amount of program memory.
* The data memory allocation for the FW tx debug feature is controlled
* by the host --> target resource configuration parameters; even if
* ATH_SUPPORT_FW_TX_DBG is defined, no data memory will be allocated for
* the FW tx debug log unless the host --> target resource configuration
* specifies it.
*/
#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_osapi.h> /* PREPACK, POSTPACK */
#endif
enum ol_fw_tx_dbg_log_mode {
ol_fw_tx_dbg_log_mode_wraparound, /* overwrite old data with new */
ol_fw_tx_dbg_log_mode_single, /* fill log once, then stop */
};
/*
* tx PPDU stats upload message header
*/
struct ol_fw_tx_dbg_ppdu_msg_hdr {
/* word 0 */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M 0x000000ff
A_UINT8 mpdu_bytes_array_len; /* length of array of per-MPDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S 8
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M 0x0000ff00
A_UINT8 msdu_bytes_array_len; /* length of array of per-MSDU byte counts */
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD 0
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S 16
#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M 0x00ff0000
A_UINT8 mpdu_msdus_array_len; /* length of array of per-MPDU MSDU counts */
A_UINT8 reserved;
/* word 1 */
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD 1
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S 0
#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M 0xffffffff
A_UINT32 microsec_per_tick; /* conversion for timestamp entries */
};
/*
* tx PPDU log element / stats upload message element
*/
struct ol_fw_tx_dbg_ppdu_base {
/* word 0 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S 0
#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M 0x0000ffff
A_UINT16 start_seq_num;
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD 0
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S 16
#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M 0xffff0000
A_UINT16 start_pn_lsbs;
/* word 1 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD 1
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S 0
#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M 0xffffffff
A_UINT32 num_bytes;
/* word 2 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S 0
#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M 0x000000ff
A_UINT8 num_msdus;
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD 2
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S 8
#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M 0x0000ff00
A_UINT8 num_mpdus;
A_UINT16
#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD 2
#define OL_FW_TX_DBG_PPDU_EXT_TID_S 16
#define OL_FW_TX_DBG_PPDU_EXT_TID_M 0x001f0000
ext_tid : 5,
#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD 2
#define OL_FW_TX_DBG_PPDU_PEER_ID_S 21
#define OL_FW_TX_DBG_PPDU_PEER_ID_M 0xffe00000
peer_id : 11;
/* word 3 - filled in during tx enqueue */
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD 3
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S 0
#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M 0xffffffff
A_UINT32 timestamp_enqueue;
/* word 4 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD 4
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S 0
#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M 0xffffffff
A_UINT32 timestamp_completion;
/* word 5 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD 5
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_lsbs;
/* word 6 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD 6
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M 0xffffffff
A_UINT32 block_ack_bitmap_msbs;
/* word 7 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD 7
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_lsbs;
/* word 8 - filled in during tx completion (enqueue would work too) */
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD 8
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S 0
#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M 0xffffffff
A_UINT32 enqueued_bitmap_msbs;
/* word 9 - filled in during tx completion */
#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_CODE_S 0
#define OL_FW_TX_DBG_PPDU_RATE_CODE_M 0x000000ff
A_UINT8 rate_code;
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD 9
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S 8
#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M 0x0000ff00
A_UINT8 rate_flags; /* includes dynamic bandwidth info */
#define OL_FW_TX_DBG_PPDU_TRIES_WORD 9
#define OL_FW_TX_DBG_PPDU_TRIES_S 16
#define OL_FW_TX_DBG_PPDU_TRIES_M 0x00ff0000
A_UINT8 tries;
#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD 9
#define OL_FW_TX_DBG_PPDU_COMPLETE_S 24
#define OL_FW_TX_DBG_PPDU_COMPLETE_M 0xff000000
A_UINT8 complete;
};
#endif /* _OL_FW_TX_DBG__H_ */

1966
fw/rtc_soc_reg.h Normal file
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551
fw/targaddrs.h Executable file → Normal file
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@ -42,14 +42,14 @@
* AR6004: These bits can be set in LOCAL_SCRATCH register 0.
* AR9888: These bits can be set in soc_core register SCRATCH_0.
*/
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
@ -80,10 +80,6 @@
#endif
#define AR6006_SOC_RESET_ADDRESS 0X00004000
#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
#define QCA9984_HOST_INTEREST_ADDRESS 0x00400800
#define IPQ4019_HOST_INTEREST_ADDRESS 0x00400800
#define QCA9888_HOST_INTEREST_ADDRESS 0x00400800
#define HOST_INTEREST_MAX_SIZE 0x200
@ -103,20 +99,20 @@ struct dbglog_hdr_s;
* More items may be added at the end.
*/
PREPACK64 struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/* Save SW ROM version */
A_UINT32 hi_sw_rom_version; /* 0x0c */
/*
* General-purpose flag bits, similar to SOC_OPTION_* flags.
@ -124,161 +120,161 @@ PREPACK64 struct host_interest_s {
*/
volatile A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
/* Host uses BE CPU or not */
A_UINT32 hi_be; /* 0x44 */
A_UINT32 hi_stack; /* normal stack */ /* 0x48 */
A_UINT32 hi_err_stack; /* error stack */ /* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
A_UINT32 hi_stack; /* normal stack *//* 0x48 */
A_UINT32 hi_err_stack; /* error stack *//* 0x4c */
A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
/*
* Indication of Board Data state:
* 0: board data is not yet initialized.
* 1: board data is initialized; unknown size
* >1: number of bytes of initialized board data (varies with board type)
*/
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
volatile A_UINT32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* Percentage of high priority RX traffic to total expected RX traffic -
* applicable only to ar6004 */
A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
/* test applications flags */
A_UINT32 hi_test_apps_related ; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* test applications flags */
A_UINT32 hi_test_apps_related; /* 0xdc */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xe0 */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe4 */
/* Number of packet log buffers */
volatile A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* wow extension configuration */
A_UINT32 hi_wow_ext_config; /* 0xec */
A_UINT32 hi_pwr_save_flags; /* 0xf0 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Spatial Multiplexing Power Save (SMPS) options */
A_UINT32 hi_smps_options; /* 0xf4 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Interconnect-specific state */
A_UINT32 hi_interconnect_state; /* 0xf8 */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Coex configuration flags */
A_UINT32 hi_coex_config; /* 0xfc */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* Early allocation support */
A_UINT32 hi_early_alloc; /* 0x100 */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor.*/
/* Bit 1 -- TBD */
/* FW swap field */
/* Bits of this 32bit word will be used to pass specific swap
instruction to FW */
/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
FW will not swap TX descriptor. Meaning packets are formed
on the target processor. */
/* Bit 1 -- TBD */
A_UINT32 hi_fw_swap; /* 0x104 */
A_UINT32 hi_fw_swap; /* 0x104 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* global arenas pointer address, used by host driver debug */
A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* allocated bytes of DRAM use by allocated */
A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* remaining bytes of DRAM */
A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* memory track count, configured by host */
A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* minidump buffer */
A_UINT32 hi_minidump; /* 0x118 */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
/* bdata's sig and key addr */
A_UINT32 hi_bd_sig_key; /* 0x11c */
} POSTPACK64;
@ -287,38 +283,38 @@ PREPACK64 struct host_interest_s {
#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
* sending WMI ready event to host */
#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
@ -328,12 +324,12 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|-------------------------------------------------------------------------------|
*/
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|||-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
@ -345,13 +341,12 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_option_flag2 options */
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */
#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
#define HI_OPTION_RF_KILL_SHIFT 0x2
#define HI_OPTION_RF_KILL_MASK 0x1
@ -359,68 +354,71 @@ PREPACK64 struct host_interest_s {
#define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20
#define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
/* AR9888 1.0 only. Enable/disable CDC max perf support from host */
#define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20
#define CDC_MAX_PERF_WAR_ENABLED() \
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU. */
#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
/* This bit is to enable BE low latency for some customers.
* The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).
*/
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
#define HI_RESET_FLAG_WARM_RESET 0x20
#define HI_RESET_FLAG_WARM_RESET 0x20
/* define hi_fw_swap bits */
#define HI_DESC_IN_FW_BIT 0x01
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define ON_RESET_PRESERVE_BOOT_INFO() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
#define ON_RESET_WARM_RESET() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
/* host CPU endianness */
#define HOST_ON_BE_CPU() \
(HOST_INTEREST->hi_be)
(HOST_INTEREST->hi_be)
/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
/* AP nart no swap descriptor flag. Decsriptors are created
* on the target processor.
*/
#define DESC_IN_FW() \
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
/* redefine for hi_acs_flags since no product ever use it
@ -434,15 +432,20 @@ PREPACK64 struct host_interest_s {
* 1 HOST supports HTT reduced tx completion
* 2 HOST supports HTT alternate credit size for data frames
* 15..3 reserved for HOST
* 16 FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done
* 16 FW set it before sending HTC_Ready to indicate MBOX swap is done
* 17 same as above but to indicate HTT reduced tx completion capability
* 31..18 reserved for FW
*/
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0) /* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16) /* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17) /* FW support HTT reduced tx completion */
/* HOST require to swap MBOX */
#define HI_ACS_FLAGS_HOST_SWAP_MBOX (1 << 0)
/* HOST supports HTT reduced tx completion */
#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1)
/* HOST supports alternate credit size for data frames */
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
/* FW swapped MBOX */
#define HI_ACS_FLAGS_FW_SWAPPED_MBOX (1 << 16)
/* FW support HTT reduced tx completion */
#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)
/* CONSOLE FLAGS
*
@ -484,7 +487,6 @@ PREPACK64 struct host_interest_s {
#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
/* WOW Extension configuration
*
* Bit Range Meaning
@ -508,16 +510,16 @@ PREPACK64 struct host_interest_s {
#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
#define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
#define HI_WOW_EXT_GET_NUM_LISTS(config) \
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
/*
* Early allocation configuration
@ -546,57 +548,57 @@ PREPACK64 struct host_interest_s {
#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
#define HI_EARLY_ALLOC_VALID() \
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
== (HI_EARLY_ALLOC_MAGIC))
#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
((HOST_INTEREST->hi_pktlog_num_buffers))
((HOST_INTEREST->hi_pktlog_num_buffers))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
#define HOST_INTEREST_DFS_IS_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
#define HOST_INTEREST_EARLY_CFG_DONE() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
/*power save flag bit definitions*/
#define HI_PWR_SAVE_LPL_ENABLED 0x1
@ -609,15 +611,15 @@ PREPACK64 struct host_interest_s {
#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
/*power save related utility macros*/
#define HI_LPL_ENABLED() \
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
#define HI_DEV_LPL_TYPE_GET(_devix) \
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
(HOST_INTEREST->hi_pwr_save_flags & \
((HI_PWR_SAVE_LPL_DEV_MASK) << \
(HI_PWR_SAVE_LPL_DEV0_LSB + \
(_devix)*2)))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
@ -628,24 +630,24 @@ PREPACK64 struct host_interest_s {
#define AR6320_VTOP(vaddr) (vaddr)
#define AR900B_VTOP(vaddr) (vaddr)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
0)))))))
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
0)))))))
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
@ -664,23 +666,8 @@ PREPACK64 struct host_interest_s {
#define AR6320_BOARD_EXT_DATA_SZ 0
#define QCA9377_BOARD_DATA_SZ 8192
#define QCA9377_BOARD_EXT_DATA_SZ 0
#define AR900B_BOARD_DATA_SZ (14 * 1024)
#define AR900B_BOARD_DATA_SZ 7168
#define AR900B_BOARD_EXT_DATA_SZ 0
#define QCA9984_BOARD_DATA_SZ (14 * 1024)
#define QCA9984_BOARD_EXT_DATA_SZ 0
#define QCA9888_BOARD_DATA_SZ (14 * 1024)
#define QCA9888_BOARD_EXT_DATA_SZ 0
#define IPQ4019_BOARD_DATA_SZ (14 * 1024)
#define IPQ4019_BOARD_EXT_DATA_SZ 0
/* Allocate board data right at the begining of AXI SRAM,
* Current size for beeliner is 14K.
* Allocate it towards the end of DRAM, until AXI SRAM is functional.
*/
#define AR900B_BOARD_DATA_ADDR 0xc0000
#define QCA9984_BOARD_DATA_ADDR 0xc0000
#define QCA9888_BOARD_DATA_ADDR 0xc0000
#define IPQ4019_BOARD_DATA_ADDR 0xc0000
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000

30
fw/targcfg.h Executable file → Normal file
View file

@ -29,25 +29,25 @@
#define __TARGCFG_H__
#if defined(ATH_TARGET)
#include <osapi.h> /* A_UINT32 */
#include <osapi.h> /* A_UINT32 */
#else
#include <a_types.h> /* A_UINT32 */
#include <a_types.h> /* A_UINT32 */
#endif
typedef struct _targcfg_t {
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
A_UINT32 num_vdev;
A_UINT32 num_peers;
A_UINT32 num_peer_ast;
A_UINT32 num_peer_keys;
A_UINT32 num_peer_tid;
A_UINT32 num_mcast_keys;
A_UINT32 num_tx;
A_UINT32 num_rx;
A_UINT32 num_mgmt_tx;
A_UINT32 num_mgmt_rx;
A_UINT32 tx_chain_mask;
A_UINT32 rx_chain_mask;
A_UINT32 override; /* Override target with the values supplied above */
} targcfg_t;
#endif /* __TARGCFG_H__ */

159
fw/wal_rx_desc.h Executable file → Normal file
View file

@ -28,11 +28,10 @@
#ifndef _WAL_RX_DESC__H_
#define _WAL_RX_DESC__H_
#if defined(ATH_TARGET)
#include <athdefs.h> /* A_UINT8 */
#include <athdefs.h> /* A_UINT8 */
#else
#include <a_types.h> /* A_UINT8 */
#include <a_types.h> /* A_UINT8 */
#endif
/*
@ -42,7 +41,7 @@
*
*/
#if !defined(ATH_PERF_PWR_OFFLOAD)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
#include <hw/interface/rx_location_info.h>
#include <hw/interface/rx_pkt_end.h>
#include <hw/interface/rx_phy_ppdu_end.h>
@ -73,33 +72,36 @@
* ring.
*/
struct hw_rx_desc_base {
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
struct rx_attention attention;
struct rx_frag_info frag_info;
struct rx_mpdu_start mpdu_start;
struct rx_msdu_start msdu_start;
struct rx_msdu_end msdu_end;
struct rx_mpdu_end mpdu_end;
struct rx_ppdu_start ppdu_start;
struct rx_ppdu_end ppdu_end;
};
#endif
#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
/*
* This struct defines the basic MSDU rx descriptor created by FW.
*/
struct fw_rx_desc_base {
union {
struct {
A_UINT8 discard : 1,
forward : 1,
any_err : 1,
dup_err : 1,
ipa_ind : 1,
inspect : 1,
extension: 2;
}bits;
A_UINT8 val;
}u;
union {
struct {
A_UINT8 discard:1,
forward:1,
any_err:1,
dup_err:1,
ipa_ind:1,
inspect:1,
extension:2;
} bits;
A_UINT8 val;
} u;
};
#define FW_RX_DESC_DISCARD_M 0x1
@ -118,62 +120,61 @@ struct fw_rx_desc_base {
#define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt) (_fw_desc_cnt)
enum {
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
FW_RX_DESC_EXT_NONE = 0,
FW_RX_DESC_EXT_LRO_ONLY,
FW_RX_DESC_EXT_LRO_AND_OTHER,
FW_RX_DESC_EXT_OTHER
};
#define FW_RX_DESC_DISCARD_GET(_var) \
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
#define FW_RX_DESC_DISCARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
#define FW_RX_DESC_FORWARD_GET(_var) \
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
#define FW_RX_DESC_FORWARD_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
#define FW_RX_DESC_INSPECT_GET(_var) \
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
#define FW_RX_DESC_INSPECT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
#define FW_RX_DESC_EXT_GET(_var) \
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
#define FW_RX_DESC_EXT_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
((_var) |= ((_val) << FW_RX_DESC_EXT_S))
/*
* This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
*/
struct fw_rx_msdu_info {
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */
ip_chksum_fail : 1,
ipv6_proto : 1,
tcp_proto : 1,
udp_proto : 1,
ip_frag : 1,
first_wakeup : 1,
reserved : 1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag : 1,
reserved : 7;
} mon;
A_UINT8 val;
} u;
union {
/*
* The "bits" struct defines the flags in fw_rx_msdu_info used
* during regular operation.
*/
struct {
A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */
ip_chksum_fail:1,
ipv6_proto:1,
tcp_proto:1,
udp_proto:1,
ip_frag:1,
first_wakeup:1,
reserved:1;
} bits;
/*
* The "mon" struct defines the flags in fw_rx_msdu_info used
* during monitor mode.
*/
struct {
A_UINT8 last_frag:1,
reserved:7;
} mon;
A_UINT8 val;
} u;
};
/* regular operation flags */
@ -194,39 +195,39 @@ struct fw_rx_msdu_info {
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_S 6
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
#define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
#define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
#define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
#define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
#define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
#define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
#define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
#define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
#define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
#define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
/* monitor mode flags */
@ -236,9 +237,7 @@ struct fw_rx_msdu_info {
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
#define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
#endif /* _WAL_RX_DESC__H_ */

1083
fw/wlan_defs.h Executable file → Normal file
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File diff suppressed because it is too large Load diff

164
fw/wlan_module_ids.h Executable file → Normal file
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@ -1,3 +1,23 @@
/*
* Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
@ -10,79 +30,79 @@
/* Wlan module ids , global across all the modules */
typedef enum {
WLAN_MODULE_ID_MIN = 0,
WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
WLAN_MODULE_WMI, /* 0x1 */
WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
WLAN_MODULE_WHAL, /* 0x3 */
WLAN_MODULE_COEX, /* 0x4 */
WLAN_MODULE_ROAM, /* 0x5 */
WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
WLAN_MODULE_RESMGR, /* 0x7 */
WLAN_MODULE_VDEV_MGR, /* 0x8 */
WLAN_MODULE_SCAN, /* 0x9 */
WLAN_MODULE_RATECTRL, /* 0xa */
WLAN_MODULE_AP_PWRSAVE, /* 0xb */
WLAN_MODULE_BLOCKACK, /* 0xc */
WLAN_MODULE_MGMT_TXRX, /* 0xd */
WLAN_MODULE_DATA_TXRX, /* 0xe */
WLAN_MODULE_HTT, /* 0xf */
WLAN_MODULE_HOST, /* 0x10 */
WLAN_MODULE_BEACON, /* 0x11 */
WLAN_MODULE_OFFLOAD, /* 0x12 */
WLAN_MODULE_WAL, /* 0x13 */
WAL_MODULE_DE, /* 0x14 */
WLAN_MODULE_PCIELP, /* 0x15 */
WLAN_MODULE_RTT, /* 0x16 */
WLAN_MODULE_RESOURCE, /* 0x17 */
WLAN_MODULE_DCS, /* 0x18 */
WLAN_MODULE_CACHEMGR, /* 0x19 */
WLAN_MODULE_ANI, /* 0x1a */
WLAN_MODULE_P2P, /* 0x1b */
WLAN_MODULE_CSA, /* 0x1c */
WLAN_MODULE_NLO, /* 0x1d */
WLAN_MODULE_CHATTER, /* 0x1e */
WLAN_MODULE_WOW, /* 0x1f */
WLAN_MODULE_WAL_VDEV, /* 0x20 */
WLAN_MODULE_WAL_PDEV, /* 0x21 */
WLAN_MODULE_TEST, /* 0x22 */
WLAN_MODULE_STA_SMPS, /* 0x23 */
WLAN_MODULE_SWBMISS, /* 0x24 */
WLAN_MODULE_WMMAC, /* 0x25 */
WLAN_MODULE_TDLS, /* 0x26 */
WLAN_MODULE_HB, /* 0x27 */
WLAN_MODULE_TXBF, /* 0x28 */
WLAN_MODULE_BATCH_SCAN, /* 0x29 */
WLAN_MODULE_THERMAL_MGR, /* 0x2a */
WLAN_MODULE_PHYERR_DFS, /* 0x2b */
WLAN_MODULE_RMC, /* 0x2c */
WLAN_MODULE_STATS, /* 0x2d */
WLAN_MODULE_NAN, /* 0x2e */
WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
WLAN_MODULE_HIF_UART, /* 0x30 */
WLAN_MODULE_LPI, /* 0x31 */
WLAN_MODULE_EXTSCAN, /* 0x32 */
WLAN_MODULE_UNIT_TEST, /* 0x33 */
WLAN_MODULE_MLME, /* 0x34 */
WLAN_MODULE_SUPPL, /* 0x35 */
WLAN_MODULE_ERE, /* 0x36 */
WLAN_MODULE_OCB, /* 0x37 */
WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
WLAN_MODULE_WPM, /* 0x39 */
WLAN_MODULE_CSS, /* 0x3a */
WLAN_MODULE_PPS, /* 0x3b */
WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
WLAN_MODULE_MAWC, /* 0x3d */
WLAN_MODULE_CMC_QMIC, /* 0x3e */
WLAN_MODULE_EGAP, /* 0x3f */
WLAN_MODULE_NAN20, /* 0x40 */
WLAN_MODULE_QBOOST, /* 0x41 */
WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
WLAN_MODULE_HALPHY, /* 0x43 */
WAL_MODULE_ENQ, /* 0x44 */
WLAN_MODULE_ID_MIN = 0,
WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
WLAN_MODULE_WMI, /* 0x1 */
WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
WLAN_MODULE_WHAL, /* 0x3 */
WLAN_MODULE_COEX, /* 0x4 */
WLAN_MODULE_ROAM, /* 0x5 */
WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
WLAN_MODULE_RESMGR, /* 0x7 */
WLAN_MODULE_VDEV_MGR, /* 0x8 */
WLAN_MODULE_SCAN, /* 0x9 */
WLAN_MODULE_RATECTRL, /* 0xa */
WLAN_MODULE_AP_PWRSAVE, /* 0xb */
WLAN_MODULE_BLOCKACK, /* 0xc */
WLAN_MODULE_MGMT_TXRX, /* 0xd */
WLAN_MODULE_DATA_TXRX, /* 0xe */
WLAN_MODULE_HTT, /* 0xf */
WLAN_MODULE_HOST, /* 0x10 */
WLAN_MODULE_BEACON, /* 0x11 */
WLAN_MODULE_OFFLOAD, /* 0x12 */
WLAN_MODULE_WAL, /* 0x13 */
WAL_MODULE_DE, /* 0x14 */
WLAN_MODULE_PCIELP, /* 0x15 */
WLAN_MODULE_RTT, /* 0x16 */
WLAN_MODULE_RESOURCE, /* 0x17 */
WLAN_MODULE_DCS, /* 0x18 */
WLAN_MODULE_CACHEMGR, /* 0x19 */
WLAN_MODULE_ANI, /* 0x1a */
WLAN_MODULE_P2P, /* 0x1b */
WLAN_MODULE_CSA, /* 0x1c */
WLAN_MODULE_NLO, /* 0x1d */
WLAN_MODULE_CHATTER, /* 0x1e */
WLAN_MODULE_WOW, /* 0x1f */
WLAN_MODULE_WAL_VDEV, /* 0x20 */
WLAN_MODULE_WAL_PDEV, /* 0x21 */
WLAN_MODULE_TEST, /* 0x22 */
WLAN_MODULE_STA_SMPS, /* 0x23 */
WLAN_MODULE_SWBMISS, /* 0x24 */
WLAN_MODULE_WMMAC, /* 0x25 */
WLAN_MODULE_TDLS, /* 0x26 */
WLAN_MODULE_HB, /* 0x27 */
WLAN_MODULE_TXBF, /* 0x28 */
WLAN_MODULE_BATCH_SCAN, /* 0x29 */
WLAN_MODULE_THERMAL_MGR, /* 0x2a */
WLAN_MODULE_PHYERR_DFS, /* 0x2b */
WLAN_MODULE_RMC, /* 0x2c */
WLAN_MODULE_STATS, /* 0x2d */
WLAN_MODULE_NAN, /* 0x2e */
WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
WLAN_MODULE_HIF_UART, /* 0x30 */
WLAN_MODULE_LPI, /* 0x31 */
WLAN_MODULE_EXTSCAN, /* 0x32 */
WLAN_MODULE_UNIT_TEST, /* 0x33 */
WLAN_MODULE_MLME, /* 0x34 */
WLAN_MODULE_SUPPL, /* 0x35 */
WLAN_MODULE_ERE, /* 0x36 */
WLAN_MODULE_OCB, /* 0x37 */
WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
WLAN_MODULE_WPM, /* 0x39 */
WLAN_MODULE_CSS, /* 0x3a */
WLAN_MODULE_PPS, /* 0x3b */
WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
WLAN_MODULE_MAWC, /* 0x3d */
WLAN_MODULE_CMC_QMIC, /* 0x3e */
WLAN_MODULE_EGAP, /* 0x3f */
WLAN_MODULE_NAN20, /* 0x40 */
WLAN_MODULE_QBOOST, /* 0x41 */
WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
WLAN_MODULE_HALPHY, /* 0x43 */
WAL_MODULE_ENQ, /* 0x44 */
WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
} WLAN_MODULE_ID;

257
fw/wlan_tgt_def_config.h Normal file
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@ -0,0 +1,257 @@
/*
* Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __WLAN_TGT_DEF_CONFIG_H__
#define __WLAN_TGT_DEF_CONFIG_H__
/*
* set of default target config , that can be over written by platform
*/
/*
* default limit of 8 VAPs per device.
*/
/* Rome PRD support 4 vdevs */
#define CFG_TGT_NUM_VDEV 4
/*
* We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize hash collisions.
* TODO: This scaling factor would be taken care inside the WAL in the future.
*/
#define CFG_TGT_NUM_PEER_AST 2
/* # of WDS entries to support.
*/
#define CFG_TGT_WDS_ENTRIES 0
/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
*/
#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0
/* Fixed delimiters to be inserted after every MPDU
*/
#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0
/*
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_AST_SKID_LIMIT 16
/*
* total number of peers per device.
*/
#define CFG_TGT_NUM_PEERS 14
/*
* In offload mode target supports features like WOW, chatter and other
* protocol offloads. In order to support them some functionalities like
* reorder buffering, PN checking need to be done in target. This determines
* maximum number of peers suported by target in offload mode
*/
/*
* The current firmware implementation requires the number of offload peers
* should be (number of vdevs + 1).
* The reason for this is the firmware clubbed the self peer and offload peer
* in the same pool. So if the firmware wanted to support n vdevs then the
* number of offload peer must be n+1 of which n buffers will be used for
* self peer and the remaining 1 is used for offload peer to support chatter
* mode for single STA.
* Technically the macro should be 1 however the current firmware requires n+1.
* TODO: This MACRO need to be modified in the future, if the firmware modified
* to allocate buffers for self peer and offload peer independently.
*/
#define CFG_TGT_NUM_OFFLOAD_PEERS (CFG_TGT_NUM_VDEV+1)
/*
* Number of reorder buffers used in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 4
/*
* keys per peer node
*/
#define CFG_TGT_NUM_PEER_KEYS 2
/*
* total number of data TX and RX TIDs
*/
#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + CFG_TGT_NUM_VDEV + 2))
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
*/
#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x7
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
*/
#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x7
/* 100 ms for video, best-effort, and background */
#define CFG_TGT_RX_TIMEOUT_LO_PRI 100
/* 40 ms for voice*/
#define CFG_TGT_RX_TIMEOUT_HI_PRI 40
/* AR9888 unified is default in ethernet mode */
#define CFG_TGT_RX_DECAP_MODE (0x2)
/* Decap to native Wifi header */
#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
/* Decap to raw mode header */
#define CFG_TGT_RX_DECAP_MODE_RAW (0x0)
/* maximum number of pending scan requests */
#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4
/* maximum number of VDEV that could use BMISS offload */
#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x3
/* maximum number of VDEV offload Roaming to support */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x3
/* maximum number of AP profiles pushed to offload Roaming */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8
/* maximum number of VDEV offload GTK to support */
#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x3
/* default: mcast->ucast disabled if ATH_SUPPORT_MCAST2UCAST not defined */
#ifndef ATH_SUPPORT_MCAST2UCAST
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */
#else
/* (for testing) small multicast group membership table enabled */
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 4
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 16
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 2
#endif
#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 32
/*
* Specify how much memory the target should allocate for a debug log of
* tx PPDU meta-information (how large the PPDU was, when it was sent,
* whether it was successful, etc.)
* The size of the log records is configurable, from a minimum of 28 bytes
* to a maximum of about 300 bytes. A typical configuration would result
* in each log record being about 124 bytes.
* Thus, 1KB of log space can hold about 30 small records, 3 large records,
* or about 8 typical-sized records.
*/
#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */
/* target based fragment timeout and MPDU duplicate detection */
#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
/* Default VoW configuration
*/
#define CFG_TGT_DEFAULT_VOW_CONFIG 0
/*
* total number of descriptors to use in the target
*/
#define CFG_TGT_NUM_MSDU_DESC (1024 + 32)
/*
* Maximum number of frag table entries
*/
#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 10
/*
* Maximum number of VDEV that beacon tx offload will support
*/
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 3
/*
* number of vdevs that can support tdls
*/
#define CFG_TGT_NUM_TDLS_VDEVS 1
/*
* number of peers that each Tdls vdev can track
*/
#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32
/*
* number of TDLS concurrent sleep STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1
/*
* number of TDLS concurrent buffer STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1
/*
* ht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080
/*
* vht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200
/*
* threshold to enable GTX
*/
#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3
/*
* margin to move back when per > margin + threshold
*/
#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2
/*
* step for every move
*/
#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1
/*
* lowest TPC
*/
#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0
/*
* enable all BW 20/40/80/160
*/
#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf
/*
* number of vdevs that can support OCB
*/
#define CFG_TGT_NUM_OCB_VDEVS 1
/*
* maximum number of channels that can do OCB
*/
#define CFG_TGT_NUM_OCB_CHANNELS 2
/*
* maximum number of channels in an OCB schedule
*/
#define CFG_TGT_NUM_OCB_SCHEDULES 2
#endif /*__WLAN_TGT_DEF_CONFIG_H__ */

289
fw/wlan_tgt_def_config_hl.h Normal file
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@ -0,0 +1,289 @@
/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __WLAN_TGT_DEF_CONFIG_H__
#define __WLAN_TGT_DEF_CONFIG_H__
/*
* TODO: please help to consider if we need a seperate config file from LL case.
*/
/*
* set of default target config , that can be over written by platform
*/
#ifdef QCA_SUPPORT_INTEGRATED_SOC
#define CFG_TGT_NUM_VDEV 3 /*STA, P2P device, P2P GO/Cli*/
#else
/*
* default limit of VAPs per device.
*/
#define CFG_TGT_NUM_VDEV 3
#endif
/*
* We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize
* hash collisions.
* TODO: This scaling factor would be taken care inside the WAL in the future.
*/
#define CFG_TGT_NUM_PEER_AST 2
/* # of WDS entries to support.
*/
#define CFG_TGT_WDS_ENTRIES 2
/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
*/
#define CFG_TGT_DEFAULT_DMA_BURST_SIZE 0
/* Fixed delimiters to be inserted after every MPDU
*/
#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM 0
/*
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_AST_SKID_LIMIT 6
/*
* total number of peers per device.
* currently set to 8 to bring up IP3.9 for memory size problem
*/
#define CFG_TGT_NUM_PEERS 8
/*
* max number of peers per device.
*/
#define CFG_TGT_NUM_PEERS_MAX 8
/*
* In offload mode target supports features like WOW, chatter and other
* protocol offloads. In order to support them some functionalities like
* reorder buffering, PN checking need to be done in target. This determines
* maximum number of peers suported by target in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_PEERS 0
/*
* Number of reorder buffers used in offload mode
*/
#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS 0
/*
* keys per peer node
*/
#define CFG_TGT_NUM_PEER_KEYS 2
/*
* total number of TX/RX data TIDs
*/
#define CFG_TGT_NUM_TIDS (2 * (CFG_TGT_NUM_PEERS + \
CFG_TGT_NUM_VDEV))
/*
* max number of Tx TIDS
*/
#define CFG_TGT_NUM_TIDS_MAX (2 * (CFG_TGT_NUM_PEERS_MAX + \
CFG_TGT_NUM_VDEV))
/*
* number of multicast keys.
*/
#define CFG_TGT_NUM_MCAST_KEYS 8
/*
* A value of 3 would probably suffice - one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_PDEV_HANDLERS 8
/*
* A value of 3 would probably suffice - one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_VDEV_HANDLERS 4
/*
* set this to 8:
* one for WAL interals (connection pause)
* one for the control stack,
* one for the data stack
* and one for debugging
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_HANDLERS 14
/*
* set this to 3: one for the control stack, one for
* the data stack, and one for debugging.
* This value may need to be fine tuned, but a constant value will
* probably always be appropriate; it is probably not necessary to
* determine this value dynamically.
*/
#define CFG_TGT_NUM_PEER_HANDLERS 32
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
* this is rome
*/
#define CFG_TGT_DEFAULT_TX_CHAIN_MASK 0x3
/*
* set this to 0x7 (Peregrine = 3 chains).
* need to be set dynamically based on the HW capability.
* this is rome
*/
#define CFG_TGT_DEFAULT_RX_CHAIN_MASK 0x3
/* 100 ms for video, best-effort, and background */
#define CFG_TGT_RX_TIMEOUT_LO_PRI 100
/* 40 ms for voice*/
#define CFG_TGT_RX_TIMEOUT_HI_PRI 40
/* AR9888 unified is default in ethernet mode */
#define CFG_TGT_RX_DECAP_MODE (0x2)
/* Decap to native Wifi header */
#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
/* Decap to raw mode header */
#define CFG_TGT_RX_DECAP_MODE_RAW (0x0)
/* maximum number of pending scan requests */
#define CFG_TGT_DEFAULT_SCAN_MAX_REQS 0x4
/* maximum number of scan event handlers */
#define CFG_TGT_DEFAULT_SCAN_MAX_HANDLERS 0x4
/* maximum number of VDEV that could use BMISS offload */
#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV 0x2
/* maximum number of VDEV offload Roaming to support */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV 0x2
/* maximum number of AP profiles pushed to offload Roaming */
#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES 0x8
/* maximum number of VDEV offload GTK to support */
#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV 0x2
/* default: mcast->ucast disabled */
#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */
/*
* Specify how much memory the target should allocate for a debug log of
* tx PPDU meta-information (how large the PPDU was, when it was sent,
* whether it was successful, etc.)
* The size of the log records is configurable, from a minimum of 28 bytes
* to a maximum of about 300 bytes. A typical configuration would result
* in each log record being about 124 bytes.
* Thus, 1KB of log space can hold about 30 small records, 3 large records,
* or about 8 typical-sized records.
*/
#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */
/* target based fragment timeout and MPDU duplicate detection */
#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
/* Default VoW configuration
*/
#define CFG_TGT_DEFAULT_VOW_CONFIG 0
/*
* total number of descriptors to use in the target
*/
#ifndef HIF_SDIO
#define CFG_TGT_NUM_MSDU_DESC (32)
#else
#define CFG_TGT_NUM_MSDU_DESC (0)
#endif
/*
* Maximum number of frag table entries
*/
#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 2
/*
* number of vdevs that can support tdls
*/
#define CFG_TGT_NUM_TDLS_VDEVS 1
/*
* number of peers that each Tdls vdev can track
*/
#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES 32
/*
* number of TDLS concurrent sleep STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS 1
/*
* number of TDLS concurrent buffer STAs
*/
#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS 1
#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 16
/*
* Maximum number of VDEV that beacon tx offload will support
*/
#ifdef HIF_SDIO
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 2
#else
#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 1
#endif
/*
* ht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_HT_MASK 0x8080
/*
* vht enable highest MCS by default
*/
#define CFG_TGT_DEFAULT_GTX_VHT_MASK 0x80200
/*
* threshold to enable GTX
*/
#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD 3
/*
* margin to move back when per > margin + threshold
*/
#define CFG_TGT_DEFAULT_GTX_PER_MARGIN 2
/*
* step for every move
*/
#define CFG_TGT_DEFAULT_GTX_TPC_STEP 1
/*
* lowest TPC
*/
#define CFG_TGT_DEFAULT_GTX_TPC_MIN 0
/*
* enable all BW 20/40/80/160
*/
#define CFG_TGT_DEFAULT_GTX_BW_MASK 0xf
/*
* number of vdevs that can support OCB
*/
#define CFG_TGT_NUM_OCB_VDEVS 1
/*
* maximum number of channels that can do OCB
*/
#define CFG_TGT_NUM_OCB_CHANNELS 2
/*
* maximum number of channels in an OCB schedule
*/
#define CFG_TGT_NUM_OCB_SCHEDULES 2
#endif /*__WLAN_TGT_DEF_CONFIG_H__ */

134
fw/wmi.h Executable file → Normal file
View file

@ -50,7 +50,6 @@
extern "C" {
#endif
#define HTC_PROTOCOL_VERSION 0x0002
#define WMI_PROTOCOL_VERSION 0x0002
@ -58,37 +57,38 @@ extern "C" {
#define WMI_MODE_MAX 8
#define WMI_MAX_RATE_MASK 6
PREPACK struct host_app_area_s {
A_UINT32 wmi_protocol_ver;
A_UINT32 wmi_protocol_ver;
} POSTPACK;
#undef MS
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
#undef SM
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
#undef WO
#define WO(_f) ((_f##_OFFSET) >> 2)
#define WO(_f) ((_f ## _OFFSET) >> 2)
#undef GET_FIELD
#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
#undef SET_FIELD
#define SET_FIELD(_addr, _f, _val) \
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
(*((A_UINT32 *)(_addr) + WO(_f)) = \
(*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
#define WMI_GET_FIELD(_msg_buf, _msg_type, _f) \
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
#define WMI_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
#define WMI_EP_APASS WMI_EP_APSS /* TYPO: leave incorrect name as an alias for the correct name */
#define WMI_EP_APSS 0x0 /* WLAN driver running on apps processor sub-system */
/* TYPO: leave incorrect name as an alias for the correct name */
#define WMI_EP_APASS WMI_EP_APSS
/* WLAN driver running on apps processor sub-system */
#define WMI_EP_APSS 0x0
#define WMI_EP_LPASS 0x1
#define WMI_EP_SENSOR 0x2
#define WMI_EP_NANOHUB 0x3 /* WLAN driver running on NANO Hub */
/* WLAN driver running on NANO Hub */
#define WMI_EP_NANOHUB 0x3
#define WMI_EP_MODEM 0x4
#define WMI_EP_LOCATION 0x5
@ -96,37 +96,35 @@ PREPACK struct host_app_area_s {
* Control Path
*/
typedef PREPACK struct {
A_UINT32 commandId : 24,
reserved : 2, /* used for WMI endpoint ID */
plt_priv : 6; /* platform private */
} POSTPACK WMI_CMD_HDR; /* used for commands and events */
A_UINT32 commandId : 24, reserved : 2, /* used for WMI endpoint ID */
plt_priv : 6; /* platform private */
} POSTPACK WMI_CMD_HDR; /* used for commands and events */
#define WMI_CMD_HDR_COMMANDID_LSB 0
#define WMI_CMD_HDR_COMMANDID_MASK 0x00ffffff
#define WMI_CMD_HDR_COMMANDID_OFFSET 0x00000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24
#define WMI_CMD_HDR_PLT_PRIV_LSB 24
#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000
#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK 0x03000000
#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET 24
#define WMI_CMD_HDR_PLT_PRIV_LSB 24
#define WMI_CMD_HDR_PLT_PRIV_MASK 0xff000000
#define WMI_CMD_HDR_PLT_PRIV_OFFSET 0x00000000
/*
* List of Commnands
*/
typedef enum {
WMI_EXTENSION_CMDID, //used in wmi_svc.c /* Non-wireless extensions */
WMI_IGNORE_CMDID, //used in wlan_wmi.c
WMI_EXTENSION_CMDID, /* used in wmi_svc.c / * Non-wireless extensions * / */
WMI_IGNORE_CMDID, /* used in wlan_wmi.c */
} WMI_COMMAND_ID;
typedef enum {
NONE_CRYPT = 0x01,
WEP_CRYPT = 0x02,
TKIP_CRYPT = 0x04,
AES_CRYPT = 0x08,
NONE_CRYPT = 0x01,
WEP_CRYPT = 0x02,
TKIP_CRYPT = 0x04,
AES_CRYPT = 0x08,
#ifdef WAPI_ENABLE
WAPI_CRYPT = 0x10,
#endif /*WAPI_ENABLE*/
WAPI_CRYPT = 0x10,
#endif /*WAPI_ENABLE */
} CRYPTO_TYPE;
#define WMI_MAX_SSID_LEN 32
@ -136,63 +134,63 @@ typedef enum {
*/
#define WMI_PMK_LEN 32
/*
* WMI_ADD_CIPHER_KEY_CMDID
*/
typedef enum {
PAIRWISE_USAGE = 0x00,
GROUP_USAGE = 0x01,
TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
PAIRWISE_USAGE = 0x00,
GROUP_USAGE = 0x01,
TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
} KEY_USAGE;
/*
* List of Events (target to host)
*/
typedef enum {
WMI_EXTENSION_EVENTID //wmi_profhook.c and umac_wmi_events.c
WMI_EXTENSION_EVENTID, /* wmi_profhook.c and umac_wmi_events.c */
} WMI_EVENT_ID;
typedef enum {
WMI_11A_CAPABILITY = 1,
WMI_11G_CAPABILITY = 2,
WMI_11AG_CAPABILITY = 3,
WMI_11NA_CAPABILITY = 4,
WMI_11NG_CAPABILITY = 5,
WMI_11NAG_CAPABILITY = 6,
WMI_11AC_CAPABILITY = 7,
WMI_11AX_CAPABILITY = 8,
// END CAPABILITY
WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
WMI_11A_CAPABILITY = 1,
WMI_11G_CAPABILITY = 2,
WMI_11AG_CAPABILITY = 3,
WMI_11NA_CAPABILITY = 4,
WMI_11NG_CAPABILITY = 5,
WMI_11NAG_CAPABILITY = 6,
WMI_11AC_CAPABILITY = 7,
WMI_11AX_CAPABILITY = 8,
/* END CAPABILITY */
WMI_11N_CAPABILITY_OFFSET =
(WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
} WMI_PHY_CAPABILITY;
/* Deprectated, need clean up */
#define WMI_MAX_RX_META_SZ (12)
typedef PREPACK struct {
A_INT8 rssi;
A_UINT8 info; /* usage of 'info' field(8-bit):
* b1:b0 - WMI_MSG_TYPE
* b4:b3:b2 - UP(tid)
* b5 - Used in AP mode. More-data in tx dir, PS in rx.
* b7:b6 - Dot3 header(0),
* Dot11 Header(1),
* ACL data(2)
*/
A_INT8 rssi;
A_UINT8 info; /* usage of 'info' field(8-bit):
* b1:b0 - WMI_MSG_TYPE
* b4:b3:b2 - UP(tid)
* b5 - Used in AP mode. More-data in tx dir, PS in rx.
* b7:b6 - Dot3 header(0),
* Dot11 Header(1),
* ACL data(2)
*/
A_UINT16 info2; /* usage of 'info2' field(16-bit):
* b11:b0 - seq_no
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
A_UINT16 info3; /* b3:b2:b1:b0 - device id
* b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx
* b7:b5 - unused?
* b15:b8 - pad before data start(irrespective of meta version)
*/
A_UINT16 info2; /* usage of 'info2' field(16-bit):
* b11:b0 - seq_no
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
A_UINT16 info3; /* b3:b2:b1:b0 - device id
* b4 - Used in AP mode. uAPSD trigger in rx, EOSP in tx
* b7:b5 - unused?
* b15:b8 - pad before data start(irrespective of meta version)
*/
} POSTPACK WMI_DATA_HDR;
#ifdef __cplusplus
}
#endif
#endif /* _WMI_H_ */

468
fw/wmi_services.h Executable file → Normal file
View file

@ -35,170 +35,262 @@
#ifndef _WMI_SERVICES_H_
#define _WMI_SERVICES_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WMI_SERVICE_BEACON_OFFLOAD=0, /* beacon offload */
WMI_SERVICE_SCAN_OFFLOAD=1, /* scan offload */
WMI_SERVICE_ROAM_SCAN_OFFLOAD=2, /* roam scan offload */
WMI_SERVICE_BCN_MISS_OFFLOAD=3, /* beacon miss offload */
WMI_SERVICE_STA_PWRSAVE=4, /* fake sleep + basic power save */
WMI_SERVICE_STA_ADVANCED_PWRSAVE=5, /* uapsd, pspoll, force sleep */
WMI_SERVICE_AP_UAPSD=6, /* uapsd on AP */
WMI_SERVICE_AP_DFS=7, /* DFS on AP */
WMI_SERVICE_11AC=8, /* supports 11ac */
WMI_SERVICE_BLOCKACK=9, /* Supports triggering ADDBA/DELBA from host*/
WMI_SERVICE_PHYERR=10, /* PHY error */
WMI_SERVICE_BCN_FILTER=11, /* Beacon filter support */
WMI_SERVICE_RTT=12, /* RTT (round trip time) support */
WMI_SERVICE_WOW=13, /* WOW Support */
WMI_SERVICE_RATECTRL_CACHE=14, /* Rate-control caching */
WMI_SERVICE_IRAM_TIDS=15, /* TIDs in IRAM */
WMI_SERVICE_ARPNS_OFFLOAD=16, /* ARP NS Offload support for STA vdev */
WMI_SERVICE_NLO=17, /* Network list offload service */
WMI_SERVICE_GTK_OFFLOAD=18, /* GTK offload */
WMI_SERVICE_SCAN_SCH=19, /* Scan Scheduler Service */
WMI_SERVICE_CSA_OFFLOAD=20, /* CSA offload service */
WMI_SERVICE_CHATTER=21, /* Chatter service */
WMI_SERVICE_COEX_FREQAVOID=22, /* FW report freq range to avoid */
WMI_SERVICE_PACKET_POWER_SAVE=23, /* packet power save service */
WMI_SERVICE_FORCE_FW_HANG=24, /* Service to test the firmware recovery mechanism */
WMI_SERVICE_GPIO=25, /* GPIO service */
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */
WMI_STA_UAPSD_BASIC_AUTO_TRIG=27, /* Basic version of station UAPSD AC Trigger Generation Method with
* variable tigger periods (service, delay, and suspend intervals) */
WMI_STA_UAPSD_VAR_AUTO_TRIG=28, /* Station UAPSD AC Trigger Generation Method with variable
* trigger periods (service, delay, and suspend intervals) */
WMI_SERVICE_STA_KEEP_ALIVE=29, /* Serivce to support the STA KEEP ALIVE mechanism */
WMI_SERVICE_TX_ENCAP=30, /* Packet type for TX encapsulation */
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */
WMI_SERVICE_EARLY_RX=32, /* adaptive early-rx feature */
WMI_SERVICE_STA_SMPS=33, /* STA MIMO-PS */
WMI_SERVICE_FWTEST=34, /* Firmware test service */
WMI_SERVICE_STA_WMMAC=35, /* STA WMMAC */
WMI_SERVICE_TDLS=36, /* TDLS support */
WMI_SERVICE_BURST=37, /* SIFS spaced burst support */
WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE=38, /* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
WMI_SERVICE_ADAPTIVE_OCS=39, /* Service to support adaptive off-channel scheduler */
WMI_SERVICE_BA_SSN_SUPPORT=40, /* target will provide Sequence number for the peer/tid combo */
WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE=41,
WMI_SERVICE_WLAN_HB=42, /* wlan HB service */
WMI_SERVICE_LTE_ANT_SHARE_SUPPORT=43, /* support LTE/WLAN antenna sharing */
WMI_SERVICE_BATCH_SCAN=44, /* Service to support batch scan */
WMI_SERVICE_QPOWER=45, /* QPower service */
WMI_SERVICE_PLMREQ=46,
WMI_SERVICE_THERMAL_MGMT=47, /* thermal throttling support */
WMI_SERVICE_RMC=48, /* RMC support */
WMI_SERVICE_MHF_OFFLOAD=49, /* multi-hop forwarding offload */
WMI_SERVICE_COEX_SAR=50, /* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
WMI_SERVICE_BCN_TXRATE_OVERRIDE=51, /* Will support the bcn/prb rsp rate override */
WMI_SERVICE_NAN=52, /* Neighbor Awareness Network */
WMI_SERVICE_L1SS_STAT=53, /* L1SS statistics counter report */
WMI_SERVICE_ESTIMATE_LINKSPEED=54, /* Linkspeed Estimation per peer */
WMI_SERVICE_OBSS_SCAN=55, /* Service to support OBSS scan */
WMI_SERVICE_TDLS_OFFCHAN=56, /* TDLS off channel support */
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA=57, /* TDLS UAPSD Buffer STA support */
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA=58, /* TDLS UAPSD Sleep STA support */
WMI_SERVICE_IBSS_PWRSAVE=59, /* IBSS power save support */
WMI_SERVICE_LPASS=60, /* Service to support LPASS */
WMI_SERVICE_EXTSCAN=61, /* Extended Scans */
WMI_SERVICE_D0WOW=62, /* D0-WOW Support */
WMI_SERVICE_HSOFFLOAD=63, /* Hotspot offload feature Support */
WMI_SERVICE_ROAM_HO_OFFLOAD=64, /* roam handover offload */
WMI_SERVICE_RX_FULL_REORDER=65, /* target-based Rx full reorder */
WMI_SERVICE_DHCP_OFFLOAD=66, /* DHCP offload support */
WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT=67, /* STA RX DATA offload to IPA support */
WMI_SERVICE_MDNS_OFFLOAD=68, /* mDNS responder offload support */
WMI_SERVICE_SAP_AUTH_OFFLOAD=69, /* softap auth offload */
WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT=70, /* Dual Band Simultaneous support */
WMI_SERVICE_OCB=71, /* OCB mode support */
WMI_SERVICE_AP_ARPNS_OFFLOAD=72, /* arp offload support for ap mode vdev */
WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT=73, /* Per band chainmask support */
WMI_SERVICE_PACKET_FILTER_OFFLOAD=74, /* Per vdev packet filters */
WMI_SERVICE_MGMT_TX_HTT=75, /* Mgmt Tx via HTT interface */
WMI_SERVICE_MGMT_TX_WMI=76, /* Mgmt Tx via WMI interface */
WMI_SERVICE_EXT_MSG=77, /* WMI_SERVICE_READY_EXT msg follows */
WMI_SERVICE_MAWC=78, /* Motion Aided WiFi Connectivity (MAWC)*/
WMI_SERVICE_PEER_ASSOC_CONF=79, /* target will send ASSOC_CONF after ASSOC_CMD is processed */
WMI_SERVICE_EGAP=80, /* enhanced green ap support */
WMI_SERVICE_STA_PMF_OFFLOAD=81, /* FW supports 11W PMF Offload for STA */
WMI_SERVICE_UNIFIED_WOW_CAPABILITY=82, /* FW supports unified D0 and D3 wow */
WMI_SERVICE_ENHANCED_PROXY_STA=83, /* Enhanced ProxySTA mode support */
WMI_SERVICE_ATF=84, /* Air Time Fairness support */
WMI_SERVICE_COEX_GPIO=85, /* BTCOEX GPIO support */
WMI_SERVICE_AUX_SPECTRAL_INTF=86, /* Aux Radio enhancement support for ignoring spectral scan intf from main radios */
WMI_SERVICE_AUX_CHAN_LOAD_INTF=87, /* Aux Radio enhancement support for ignoring chan load intf from main radios*/
WMI_SERVICE_BSS_CHANNEL_INFO_64=88, /* BSS channel info (freq, noise floor, 64-bit counters) event support */
WMI_SERVICE_ENTERPRISE_MESH=89, /* Enterprise MESH Service Support */
WMI_SERVICE_RESTRT_CHNL_SUPPORT=90, /* Restricted Channel Support */
WMI_SERVICE_BPF_OFFLOAD=91, /* FW supports bpf offload */
WMI_SERVICE_SYNC_DELETE_CMDS=92, /* FW sends response event for Peer, Vdev delete commands */
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT=93,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT=94,
WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES=95, /* allow per-peer tx MCS min/max limits by host */
WMI_SERVICE_NAN_DATA=96, /* FW supports NAN data */
WMI_SERVICE_NAN_RTT=97, /* FW supports NAN RTT */
WMI_SERVICE_11AX=98, /* FW supports 802.11ax */
/* WMI_SERVICE_DEPRECATED_REPLACE
* FW supports these new WMI commands, to be used rather than
* deprecated matching commands:
* - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID)
* - WMI_PDEV_SET_HW_MODE_CMDID (vs. WMI_SOC_SET_HW_MODE_CMDID)
* - WMI_PDEV_SET_MAC_CONFIG_CMDID (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
* - WMI_PDEV_SET_ANTENNA_MODE_CMDID (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
* - WMI_VDEV_SET_DSCP_TID_MAP_CMDID (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
*/
WMI_SERVICE_DEPRECATED_REPLACE=99,
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE=100, /* FW supports a new mode that allows to run connection tracker in host */
WMI_SERVICE_ENHANCED_MCAST_FILTER=101, /* FW supports enhanced multicast filtering (of mcast IP inside ucast WLAN) */
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT=102, /* periodic channel stats service */
WMI_SERVICE_MESH_11S=103, /* 11s mesh service support */
WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT=104, /* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate) channel bandwidth */
WMI_SERVICE_VDEV_RX_FILTER=105, /* Support per-vdev specs of which rx frames to filter out */
WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT=106,
WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET=107, /* FW supports marking the first data packet which wakes the host from suspend */
WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET=108, /* FW supports command that can add/delete multiple mcast filters */
/* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
* FW supports host-managed RX reorder.
* Host managed RX reorder involves RX BA state machine handling
* on peer/TID basis, REO configuration for HW based reordering/PN
* check and processing reorder exceptions generated by HW.
*/
WMI_SERVICE_HOST_MANAGED_RX_REORDER=109,
/* Specify whether the target supports the following WMI messages for
* reading / writing its flash memory:
* WMI_READ_DATA_FROM_FLASH_CMDID,
* WMI_READ_DATA_FROM_FLASH_EVENTID,
* WMI_TRANSFER_DATA_TO_FLASH_CMDID,
* WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
*/
WMI_SERVICE_FLASH_RDWR_SUPPORT=110,
WMI_SERVICE_WLAN_STATS_REPORT=111, /* support WLAN stats report */
typedef enum {
WMI_SERVICE_BEACON_OFFLOAD = 0, /* beacon offload */
WMI_SERVICE_SCAN_OFFLOAD = 1, /* scan offload */
WMI_SERVICE_ROAM_SCAN_OFFLOAD = 2, /* roam scan offload */
WMI_SERVICE_BCN_MISS_OFFLOAD = 3, /* beacon miss offload */
/* fake sleep + basic power save */
WMI_SERVICE_STA_PWRSAVE = 4,
WMI_SERVICE_STA_ADVANCED_PWRSAVE = 5, /* uapsd, pspoll, force sleep */
WMI_SERVICE_AP_UAPSD = 6, /* uapsd on AP */
WMI_SERVICE_AP_DFS = 7, /* DFS on AP */
WMI_SERVICE_11AC = 8, /* supports 11ac */
/* Supports triggering ADDBA/DELBA from host*/
WMI_SERVICE_BLOCKACK = 9,
WMI_SERVICE_PHYERR = 10, /* PHY error */
WMI_SERVICE_BCN_FILTER = 11, /* Beacon filter support */
/* RTT (round trip time) support */
WMI_SERVICE_RTT = 12,
WMI_SERVICE_WOW = 13, /* WOW Support */
WMI_SERVICE_RATECTRL_CACHE = 14, /* Rate-control caching */
WMI_SERVICE_IRAM_TIDS = 15, /* TIDs in IRAM */
/* ARP NS Offload support for STA vdev */
WMI_SERVICE_ARPNS_OFFLOAD = 16,
/* Network list offload service */
WMI_SERVICE_NLO = 17,
WMI_SERVICE_GTK_OFFLOAD = 18, /* GTK offload */
WMI_SERVICE_SCAN_SCH = 19, /* Scan Scheduler Service */
WMI_SERVICE_CSA_OFFLOAD = 20, /* CSA offload service */
WMI_SERVICE_CHATTER = 21, /* Chatter service */
/* FW report freq range to avoid */
WMI_SERVICE_COEX_FREQAVOID = 22,
WMI_SERVICE_PACKET_POWER_SAVE = 23, /* packet power save service */
/* Service to test the firmware recovery mechanism */
WMI_SERVICE_FORCE_FW_HANG = 24,
WMI_SERVICE_GPIO = 25, /* GPIO service */
/* Modulated DTIM support */
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
/**
* Basic version of station UAPSD AC Trigger Generation Method with
* variable tigger periods (service, delay, and suspend intervals)
*/
WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
/**
* Station UAPSD AC Trigger Generation Method with variable
* trigger periods (service, delay, and suspend intervals)
*/
WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
/* Serivce to support the STA KEEP ALIVE mechanism */
WMI_SERVICE_STA_KEEP_ALIVE = 29,
/* Packet type for TX encapsulation */
WMI_SERVICE_TX_ENCAP = 30,
/* detect out-of-sync sleeping stations */
WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
WMI_SERVICE_EARLY_RX = 32, /* adaptive early-rx feature */
WMI_SERVICE_STA_SMPS = 33, /* STA MIMO-PS */
WMI_SERVICE_FWTEST = 34, /* Firmware test service */
WMI_SERVICE_STA_WMMAC = 35, /* STA WMMAC */
WMI_SERVICE_TDLS = 36, /* TDLS support */
WMI_SERVICE_BURST = 37, /* SIFS spaced burst support */
/* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
/* Service to support adaptive off-channel scheduler */
WMI_SERVICE_ADAPTIVE_OCS = 39,
/* target will provide Sequence number for the peer/tid combo */
WMI_SERVICE_BA_SSN_SUPPORT = 40,
WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
WMI_SERVICE_WLAN_HB = 42, /* wlan HB service */
/* support LTE/WLAN antenna sharing */
WMI_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
WMI_SERVICE_BATCH_SCAN = 44, /*Service to support batch scan*/
WMI_SERVICE_QPOWER = 45, /* QPower service */
WMI_SERVICE_PLMREQ = 46,
WMI_SERVICE_THERMAL_MGMT = 47, /* thermal throttling support */
WMI_SERVICE_RMC = 48, /* RMC support */
/* multi-hop forwarding offload */
WMI_SERVICE_MHF_OFFLOAD = 49,
/* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
WMI_SERVICE_COEX_SAR = 50,
/* Will support the bcn/prb rsp rate override */
WMI_SERVICE_BCN_TXRATE_OVERRIDE = 51,
WMI_SERVICE_NAN = 52, /* Neighbor Awareness Network */
/* L1SS statistics counter report */
WMI_SERVICE_L1SS_STAT = 53,
/* Linkspeed Estimation per peer */
WMI_SERVICE_ESTIMATE_LINKSPEED = 54,
/* Service to support OBSS scan */
WMI_SERVICE_OBSS_SCAN = 55,
WMI_SERVICE_TDLS_OFFCHAN = 56, /* TDLS off channel support */
/* TDLS UAPSD Buffer STA support */
WMI_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
/* TDLS UAPSD Sleep STA support */
WMI_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
WMI_SERVICE_IBSS_PWRSAVE = 59, /* IBSS power save support */
WMI_SERVICE_LPASS = 60, /*Service to support LPASS*/
WMI_SERVICE_EXTSCAN = 61, /* Extended Scans */
WMI_SERVICE_D0WOW = 62, /* D0-WOW Support */
/* Hotspot offload feature Support */
WMI_SERVICE_HSOFFLOAD = 63,
WMI_SERVICE_ROAM_HO_OFFLOAD = 64, /* roam handover offload */
/* target-based Rx full reorder */
WMI_SERVICE_RX_FULL_REORDER = 65,
WMI_SERVICE_DHCP_OFFLOAD = 66, /* DHCP offload support */
/* STA RX DATA offload to IPA support */
WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
/* mDNS responder offload support */
WMI_SERVICE_MDNS_OFFLOAD = 68,
WMI_SERVICE_SAP_AUTH_OFFLOAD = 69, /* softap auth offload */
/* Dual Band Simultaneous support */
WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
WMI_SERVICE_OCB = 71, /* OCB mode support */
/* arp offload support for ap mode vdev */
WMI_SERVICE_AP_ARPNS_OFFLOAD = 72,
/* Per band chainmask support */
WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
WMI_SERVICE_PACKET_FILTER_OFFLOAD = 74, /* Per vdev packet filters */
WMI_SERVICE_MGMT_TX_HTT = 75, /* Mgmt Tx via HTT interface */
WMI_SERVICE_MGMT_TX_WMI = 76, /* Mgmt Tx via WMI interface */
/* WMI_SERVICE_READY_EXT msg follows */
WMI_SERVICE_EXT_MSG = 77,
/* Motion Aided WiFi Connectivity (MAWC)*/
WMI_SERVICE_MAWC = 78,
/* target will send ASSOC_CONF after ASSOC_CMD is processed */
WMI_SERVICE_PEER_ASSOC_CONF = 79,
WMI_SERVICE_EGAP = 80, /* enhanced green ap support */
/* FW supports 11W PMF Offload for STA */
WMI_SERVICE_STA_PMF_OFFLOAD = 81,
/* FW supports unified D0 and D3 wow */
WMI_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
/* Enhanced ProxySTA mode support */
WMI_SERVICE_ENHANCED_PROXY_STA = 83,
WMI_SERVICE_ATF = 84, /* Air Time Fairness support */
WMI_SERVICE_COEX_GPIO = 85, /* BTCOEX GPIO support */
/**
* Aux Radio enhancement support for ignoring spectral scan intf
* from main radios
*/
WMI_SERVICE_AUX_SPECTRAL_INTF = 86,
/**
* Aux Radio enhancement support for ignoring chan load intf
* from main radios
*/
WMI_SERVICE_AUX_CHAN_LOAD_INTF = 87,
/**
* BSS channel info (freq, noise floor, 64-bit counters)
* event support
*/
WMI_SERVICE_BSS_CHANNEL_INFO_64 = 88,
/* Enterprise MESH Service Support */
WMI_SERVICE_ENTERPRISE_MESH = 89,
WMI_SERVICE_RESTRT_CHNL_SUPPORT = 90, /* Restricted Channel Support */
WMI_SERVICE_BPF_OFFLOAD = 91, /* FW supports bpf offload */
/* FW sends response event for Peer, Vdev delete commands */
WMI_SERVICE_SYNC_DELETE_CMDS = 92,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
/* allow per-peer tx MCS min/max limits by host */
WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
WMI_SERVICE_NAN_DATA = 96, /* FW supports NAN data */
WMI_SERVICE_NAN_RTT = 97, /* FW supports NAN RTT */
WMI_SERVICE_11AX = 98, /* FW supports 802.11ax */
/* WMI_SERVICE_DEPRECATED_REPLACE
* FW supports these new WMI commands, to be used rather than
* deprecated matching commands:
* - WMI_PDEV_SET_PCL_CMDID (vs. WMI_SOC_SET_PCL_CMDID)
* - WMI_PDEV_SET_HW_MODE_CMDID
* (vs. WMI_SOC_SET_HW_MODE_CMDID)
* - WMI_PDEV_SET_MAC_CONFIG_CMDID
* (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
* - WMI_PDEV_SET_ANTENNA_MODE_CMDID
* (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
* - WMI_VDEV_SET_DSCP_TID_MAP_CMDID
* (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
*/
WMI_SERVICE_DEPRECATED_REPLACE = 99,
/**
* FW supports a new mode that allows to run connection tracker
* in host
*/
WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
/**
* FW supports enhanced multicast filtering (of mcast IP inside
* ucast WLAN)
*/
WMI_SERVICE_ENHANCED_MCAST_FILTER = 101,
/* periodic channel stats service */
WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
WMI_SERVICE_MESH_11S = 103,
/**
* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate)
* channel bandwidth
*/
WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
/* Support per-vdev specs of which rx frames to filter out */
WMI_SERVICE_VDEV_RX_FILTER = 105,
WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
/**
* FW supports marking the first data packet which wakes
* the host from suspend
*/
WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
/* FW supports command that can add/delete multiple mcast filters */
WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
/* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
* FW supports host-managed RX reorder.
* Host managed RX reorder involves RX BA state machine handling
* on peer/TID basis, REO configuration for HW based reordering/PN
* check and processing reorder exceptions generated by HW.
*/
WMI_SERVICE_HOST_MANAGED_RX_REORDER = 109,
/* Specify whether the target supports the following WMI messages
* for reading / writing its flash memory:
* WMI_READ_DATA_FROM_FLASH_CMDID,
* WMI_READ_DATA_FROM_FLASH_EVENTID,
* WMI_TRANSFER_DATA_TO_FLASH_CMDID,
* WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
*/
WMI_SERVICE_FLASH_RDWR_SUPPORT = 110,
WMI_SERVICE_WLAN_STATS_REPORT = 111, /* support WLAN stats report */
/******* ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED *******/
/* WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT -
* FW supports bigger MSDU ID partition which is defined as
* HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. When both host and FW support
* new partition, FW uses HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. If host
* doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
* Handshaking is done through WMI_INIT and WMI service ready
*
* support bigger MSDU ID partition
*/
WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
WMI_SERVICE_DFS_PHYERR_OFFLOAD = 113,
WMI_MAX_SERVICE=128, /* max service */
/*** ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED ***/
/* NOTE:
* The above service flags are delivered in the wmi_service_bitmap field
* of the WMI_SERVICE_READY_EVENT message.
* The below service flags are delivered in a WMI_SERVICE_AVAILABLE_EVENT
* message rather than in the WMI_SERVICE_READY_EVENT message's
* wmi_service_bitmap field.
* The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
* WMI_SERVICE_READY_EVENT message.
*/
WMI_MAX_SERVICE = 128, /* max service */
/*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/
/*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/
/**
* NOTE:
* The above service flags are delivered in the wmi_service_bitmap
* field of the WMI_SERVICE_READY_EVENT message.
* The below service flags are delivered in a
* WMI_SERVICE_AVAILABLE_EVENT message rather than in the
* WMI_SERVICE_READY_EVENT message's wmi_service_bitmap field.
* The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
* WMI_SERVICE_READY_EVENT message.
*/
WMI_MAX_EXT_SERVICE
/*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/
/*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/
WMI_MAX_EXT_SERVICE
} WMI_SERVICE;
@ -207,59 +299,61 @@ typedef enum {
#define WMI_NUM_EXT_SERVICES (WMI_MAX_EXT_SERVICE - WMI_MAX_SERVICE)
#define WMI_SERVICE_EXT_BM_SIZE32 ((WMI_NUM_EXT_SERVICES + 31) / 32)
#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD /* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help compiling with old host driver */
/**
* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help
* compiling with old host driver
*/
#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD
/*
* turn on the WMI service bit corresponding to the WMI service.
*/
#define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
(1 << ((svc_id)%(sizeof(A_UINT32)))) )
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
(1 << ((svc_id)%(sizeof(A_UINT32)))) )
#define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \
( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &= \
( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
#define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \
( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \
(1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] & \
(1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
#define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] |= (1 << bit); \
} \
} while (0)
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] |= (1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
} \
} while (0)
do { \
if (svc_id < WMI_MAX_SERVICE) { \
WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
} else { \
int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
(pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
} \
} while (0)
#define WMI_SERVICE_EXT_IS_ENABLED(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
/* If the service ID is beyond the known limit, treat it as disabled */ \
((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
/* If service ID is in the non-extension range, use the old check */ \
(svc_id) < WMI_MAX_SERVICE ? \
WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
/* If service ID is in the extended range, check ext_bmap */ \
(pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
((svc_id) & 0x1f))
/* If the service ID is beyond the known limit, treat it as disabled */ \
((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
/* If service ID is in the non-extension range, use the old check */ \
(svc_id) < WMI_MAX_SERVICE ? \
WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
/* If service ID is in the extended range, check ext_bmap */ \
(pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
((svc_id) & 0x1f))
#ifdef __cplusplus
}
#endif
#endif /*_WMI_SERVICES_H_*/

4608
fw/wmi_tlv_defs.h Executable file → Normal file
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80
fw/wmi_tlv_helper.h Executable file → Normal file
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@ -24,6 +24,7 @@
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _WMI_TLV_HELPER_H_
#define _WMI_TLV_HELPER_H_
@ -42,7 +43,7 @@
* (5) Either WMITLV_SIZE_FIX or WMITLV_SIZE_VAR to indicate if this TLV is variable size.
*
* Note: It is important that the last TLV_ELEM does not have the "\" character.
*/
*/
/* Size of the TLV Header which is the Tag and Length fields */
#define WMI_TLV_HDR_SIZE (1 * sizeof(A_UINT32))
@ -75,20 +76,19 @@ typedef struct {
A_UINT32 tag_struct_size;
A_UINT32 tag_varied_size;
A_UINT32 tag_array_size;
A_UINT32 cmd_num_tlv;
A_UINT32 cmd_num_tlv;
} wmitlv_attributes_struc;
/* Template structure definition for a variable size array of UINT32 */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
A_UINT32 uint32_array[1]; /* variable length Array of UINT32 */
} wmitlv_array_uint32;
/* Template structure definition for a variable size array of unknown structure */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
A_UINT32 struc_array[1]; /* variable length Array of structures */
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
A_UINT32 struc_array[1]; /* variable length Array of structures */
} wmitlv_array_struc;
/*
@ -97,60 +97,64 @@ typedef struct {
*/
#define WMITLV_ARR_SIZE_INVALID 0x1FE
#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \
WMI_TLV_HLPR_NUM_TLVS_FOR_##wmi_cmd_event_id
#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id) \
WMI_TLV_HLPR_NUM_TLVS_FOR_ ## wmi_cmd_event_id
void
wmitlv_set_static_param_tlv_buf(void *param_tlv_buf, A_UINT32 max_tlvs_accomodated);
wmitlv_set_static_param_tlv_buf(void *param_tlv_buf,
A_UINT32 max_tlvs_accomodated);
void
wmitlv_free_allocated_command_tlvs(
A_UINT32 cmd_id,
void **wmi_cmd_struct_ptr);
wmitlv_free_allocated_command_tlvs(A_UINT32 cmd_id, void **wmi_cmd_struct_ptr);
void
wmitlv_free_allocated_event_tlvs(
A_UINT32 event_id,
void **wmi_cmd_struct_ptr);
wmitlv_free_allocated_event_tlvs(A_UINT32 event_id, void **wmi_cmd_struct_ptr);
int
wmitlv_check_command_tlv_params(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
wmitlv_check_command_tlv_params(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_event_tlv_params(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
wmitlv_check_event_tlv_params(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id);
int
wmitlv_check_and_pad_command_tlvs(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
wmitlv_check_and_pad_command_tlvs(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id,
void **wmi_cmd_struct_ptr);
int
wmitlv_check_and_pad_event_tlvs(
void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
wmitlv_check_and_pad_event_tlvs(void *os_ctx, void *param_struc_ptr,
A_UINT32 param_buf_len,
A_UINT32 wmi_cmd_event_id,
void **wmi_cmd_struct_ptr);
/** This structure is the element for the Version WhiteList
* table. */
typedef struct {
A_UINT32 major;
A_UINT32 minor;
A_UINT32 namespace_0;
A_UINT32 namespace_1;
A_UINT32 namespace_2;
A_UINT32 namespace_3;
A_UINT32 major;
A_UINT32 minor;
A_UINT32 namespace_0;
A_UINT32 namespace_1;
A_UINT32 namespace_2;
A_UINT32 namespace_3;
} wmi_whitelist_version_info;
struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */
struct _wmi_abi_version; /* Forward declaration to make the ARM compiler happy */
int
wmi_cmp_and_set_abi_version(int num_whitelist, wmi_whitelist_version_info *version_whitelist_table,
struct _wmi_abi_version *my_vers,
struct _wmi_abi_version *opp_vers,
struct _wmi_abi_version *out_vers);
wmi_cmp_and_set_abi_version(int num_whitelist,
wmi_whitelist_version_info *
version_whitelist_table,
struct _wmi_abi_version *my_vers,
struct _wmi_abi_version *opp_vers,
struct _wmi_abi_version *out_vers);
int
wmi_versions_are_compatible(struct _wmi_abi_version *vers1, struct _wmi_abi_version *vers2);
wmi_versions_are_compatible(struct _wmi_abi_version *vers1,
struct _wmi_abi_version *vers2);
#endif /*_WMI_TLV_HELPER_H_*/

23263
fw/wmi_unified.h Executable file → Normal file
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5
fw/wmi_version.h Executable file → Normal file
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@ -35,8 +35,8 @@
* compatibility. */
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
#define __WMI_REVISION_ 290
* change that may or may not break compatibility */
#define __WMI_REVISION_ 309
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
@ -78,4 +78,3 @@
#define WMI_ABI_VERSION_NS_1 __NAMESPACE_1_
#define WMI_ABI_VERSION_NS_2 __NAMESPACE_2_
#define WMI_ABI_VERSION_NS_3 __NAMESPACE_3_

111
fw/wmix.h Executable file → Normal file
View file

@ -53,29 +53,29 @@ extern "C" {
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
*/
typedef struct {
A_UINT32 commandId;
A_UINT32 commandId;
} POSTPACK WMIX_CMD_HDR;
typedef enum {
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
WMIX_DSETDATA_REPLY_CMDID,
WMIX_HB_CHALLENGE_RESP_CMDID,
WMIX_DBGLOG_CFG_MODULE_CMDID,
WMIX_PROF_CFG_CMDID, /* 0x200a */
WMIX_PROF_ADDR_SET_CMDID,
WMIX_PROF_START_CMDID,
WMIX_PROF_STOP_CMDID,
WMIX_PROF_COUNT_GET_CMDID,
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
WMIX_DSETDATA_REPLY_CMDID,
WMIX_HB_CHALLENGE_RESP_CMDID,
WMIX_DBGLOG_CFG_MODULE_CMDID,
WMIX_PROF_CFG_CMDID, /* 0x200a */
WMIX_PROF_ADDR_SET_CMDID,
WMIX_PROF_START_CMDID,
WMIX_PROF_STOP_CMDID,
WMIX_PROF_COUNT_GET_CMDID,
} WMIX_COMMAND_ID;
typedef enum {
WMIX_DSETOPENREQ_EVENTID = 0x3001,
WMIX_DSETCLOSE_EVENTID,
WMIX_DSETDATAREQ_EVENTID,
WMIX_HB_CHALLENGE_RESP_EVENTID,
WMIX_DBGLOG_EVENTID,
WMIX_PROF_COUNT_EVENTID,
WMIX_PKTLOG_EVENTID,
WMIX_DSETOPENREQ_EVENTID = 0x3001,
WMIX_DSETCLOSE_EVENTID,
WMIX_DSETDATAREQ_EVENTID,
WMIX_HB_CHALLENGE_RESP_EVENTID,
WMIX_DBGLOG_EVENTID,
WMIX_PROF_COUNT_EVENTID,
WMIX_PKTLOG_EVENTID,
} WMIX_EVENT_ID;
/*
@ -87,10 +87,10 @@ typedef enum {
* DataSet Open Request Event
*/
typedef struct {
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETOPENREQ_EVENT;
/*
@ -98,7 +98,7 @@ typedef struct {
* DataSet Close Event
*/
typedef struct {
A_UINT32 access_cookie;
A_UINT32 access_cookie;
} POSTPACK WMIX_DSETCLOSE_EVENT;
/*
@ -106,33 +106,32 @@ typedef struct {
* DataSet Data Request Event
*/
typedef struct {
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} WMIX_DSETDATAREQ_EVENT;
typedef struct {
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
} WMIX_DSETOPEN_REPLY_CMD;
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
} WMIX_DSETOPEN_REPLY_CMD;
typedef struct {
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
A_UINT8 buf[1];
} WMIX_DSETDATA_REPLY_CMD;
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
A_UINT8 buf[1];
} WMIX_DSETDATA_REPLY_CMD;
/*
* =============Error Detection support=================
@ -143,9 +142,9 @@ typedef struct {
* Heartbeat Challenge Response command
*/
typedef struct {
A_UINT32 cookie;
A_UINT32 source;
} WMIX_HB_CHALLENGE_RESP_CMD;
A_UINT32 cookie;
A_UINT32 source;
} WMIX_HB_CHALLENGE_RESP_CMD;
/*
* WMIX_HB_CHALLENGE_RESP_EVENTID
@ -158,13 +157,13 @@ typedef struct {
*/
typedef struct {
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
} WMIX_PROF_CFG_CMD;
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
} WMIX_PROF_CFG_CMD;
typedef struct {
A_UINT32 addr;
} WMIX_PROF_ADDR_SET_CMD;
A_UINT32 addr;
} WMIX_PROF_ADDR_SET_CMD;
/*
* Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
@ -173,13 +172,11 @@ typedef struct {
* count set to the corresponding count
*/
typedef struct {
A_UINT32 addr;
A_UINT32 count;
} WMIX_PROF_COUNT_EVENT;
A_UINT32 addr;
A_UINT32 count;
} WMIX_PROF_COUNT_EVENT;
#ifdef __cplusplus
}
#endif
#endif /* _WMIX_H_ */

131
hw/qca6290/v1/HALcomdef.h Normal file
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@ -0,0 +1,131 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
/*
==============================================================================
FILE: HALcomdef.h
DESCRIPTION:
==============================================================================
Edit History
$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $
when who what, where, why
-------- --- -----------------------------------------------------------
06/17/10 sc Included com_dtypes.h and cleaned up typedefs
05/15/08 gfr Added HAL_ENUM_32BITS macro.
02/14/08 gfr Added bool32 type.
11/13/07 gfr Removed dependency on comdef.h
01/08/07 hxw Created
*/
/*
* Assembly wrapper
*/
#ifndef _ARM_ASM_
/*
* C++ wrapper
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
/* -----------------------------------------------------------------------
** Types
** ----------------------------------------------------------------------- */
/*
* Standard integer types.
*
* bool32 - boolean, 32 bit (TRUE or FALSE)
*/
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
/*
* Macro to allow forcing an enum to 32 bits. The argument should be
* an identifier in the namespace of the enumeration in question, i.e.
* for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
*/
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
/*===========================================================================
FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
DESCRIPTION
IN/OUT port macros for byte and word ports, typically inlined by compilers
which support these routines
PARAMETERS
inp( xx_addr )
inpw( xx_addr )
inpdw( xx_addr )
outp( xx_addr, xx_byte_val )
outpw( xx_addr, xx_word_val )
outpdw( xx_addr, xx_dword_val )
xx_addr - Address of port to read or write (may be memory mapped)
xx_byte_val - 8 bit value to write
xx_word_val - 16 bit value to write
xx_dword_val - 32 bit value to write
DEPENDENCIES
None
RETURN VALUE
inp/inpw/inpdw: the byte, word or dword read from the given address
outp/outpw/outpdw: the byte, word or dword written to the given address
SIDE EFFECTS
None.
===========================================================================*/
/* ARM based targets use memory mapped i/o, so the inp/outp calls are
** macroized to access memory directly
*/
#define inp(port) (*((volatile byte *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#ifdef __cplusplus
}
#endif
#endif /* !_ARM_ASM_ */
#endif /* HAL_COMDEF_H */

490
hw/qca6290/v1/HALhwio.h Normal file
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@ -0,0 +1,490 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
/*
===========================================================================
*/
/**
@file HALhwio.h
Public interface include file for accessing the HWIO HAL definitions.
The HALhwio.h file is the public API interface to the HW I/O (HWIO)
register access definitions.
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Common types.
*/
#include "HALcomdef.h"
/* -----------------------------------------------------------------------
** Macros
** ----------------------------------------------------------------------- */
/**
@addtogroup macros
@{
*/
/**
* Map a base name to the pointer to access the base.
*
* This macro maps a base name to the pointer to access the base.
* This is generally just used internally.
*
*/
#define HWIO_BASE_PTR(base) base##_BASE_PTR
/**
* Declare a HWIO base pointer.
*
* This macro will declare a HWIO base pointer data structure. The pointer
* will always be declared as a weak symbol so multiple declarations will
* resolve correctly to the same data at link-time.
*/
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
#endif
/**
@}
*/
/**
@addtogroup hwio_macros
@{
*/
/**
* @name Address Macros
*
* Macros for getting register addresses.
* These macros are used for retrieving the address of a register.
* HWIO_ADDR* will return the directly accessible address (virtual or physical based
* on environment), HWIO_PHYS* will always return the physical address.
* The offset from the base region can be retrieved using HWIO_OFFS*.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* @{
*/
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
/** @} */
/**
* @name Input Macros
*
* These macros are used for reading from a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the input will be masked with the supplied mask. The HWIO_INF*
* macros take a field name and will do the appropriate masking and shifting
* to return just the value of that field.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
*
* @{
*/
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
/** @} */
/**
* @name Output Macros
*
* These macros are used for writing to a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the output will be masked with the supplied mask (meaning these
* macros do a read first, mask in the supplied data, then write it back).
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
* The HWIO_OUTF* macros take a field name and will do the appropriate masking
* and shifting to output just the value of that field.
* HWIO_OUTV* registers take a named value instead of a numeric value and
* do the same masking/shifting as HWIO_OUTF.
*
* Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
*
* @{
*/
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
/** @} */
/**
* @name Shift and Mask Macros
*
* Macros for getting shift and mask values for fields and registers.
* HWIO_RMSK: The mask value for accessing an entire register. For example:
* @code
* HWIO_RMSK(REG) -> 0xFFFFFFFF
* @endcode
* HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
* HWIO_SHFT: The right-shift value for accessing a field in a register. For example:
* @code
* HWIO_SHFT(REG, FLD) -> 8
* @endcode
* HWIO_FMSK: The mask value for accessing a field in a register. For example:
* @code
* HWIO_FMSK(REG, FLD) -> 0xFF00
* @endcode
* HWIO_VAL: The value for a field in a register. For example:
* @code
* HWIO_VAL(REG, FLD, ON) -> 0x1
* @endcode
* HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
* the given field position. For example:
* @code
* HWIO_FVAL(REG, FLD, 0x1) -> 0x100
* @endcode
* HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
* into the given field position. For example:
* @code
* HWIO_FVALV(REG, FLD, ON) -> 0x100
* @endcode
*
* @{
*/
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
/** @} */
/**
* @name Shadow Register Macros
*
* These macros are used for directly reading the value stored in a
* shadow register.
* Shadow registers are defined for write-only registers. Generally these
* macros should not be necessary as HWIO_OUTM* macros will automatically use
* the shadow values internally.
*
* @{
*/
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
/** @} */
/**
@}
*/ /* end_group */
/** @cond */
/*
* Map to final symbols. This remapping is done to allow register
* redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
* then remappings like "#define xreg xregnew" do not work as expected.
*/
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
/*
* HWIO_INTLOCK
*
* Macro used by autogenerated code for mutual exclusion around
* read-mask-write operations. This is not supported in HAL
* code but can be overridden by non-HAL code.
*/
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
/*
* Input/output port macros for memory mapped IO.
*/
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
/*
* Replace macros with externally supplied functions.
*/
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern ( uint32 nAddr );
extern uint16 __inpw_extern ( uint32 nAddr );
extern uint32 __inpdw_extern ( uint32 nAddr );
extern void __outp_extern ( uint32 nAddr, uint8 nData );
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
#endif /* HAL_HWIO_EXTERNAL */
/*
* Base 8-bit byte accessing macros.
*/
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr,val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte( io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 16-bit word accessing macros.
*/
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr,val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK( ); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word( io, shadow); \
HWIO_INTFREE( )
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 32-bit double-word accessing macros.
*/
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr,val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword( io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))) )
/** @endcond */
#endif /* HAL_HWIO_H */

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 buffer_addr_31_0[31:0]
// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
uint32_t buffer_addr_31_0 : 32; //[31:0]
uint32_t buffer_addr_39_32 : 8, //[7:0]
return_buffer_manager : 3, //[10:8]
sw_buffer_cookie : 21; //[31:11]
};
/*
buffer_addr_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
buffer_addr_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
return_buffer_manager
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<legal 0-6>
sw_buffer_cookie
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE:
The two most significant bits can have a special meaning
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
and field transmit_bw_restriction is set
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
<legal all>
*/
/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<legal 0-6>
*/
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE:
The two most significant bits can have a special meaning
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
and field transmit_bw_restriction is set
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
<legal all>
*/
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _BUFFER_ADDR_INFO_H_

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hw/qca6290/v1/ce_src_desc.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 src_buffer_low[31:0]
// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
// 2 fw_metadata[15:0], ce_res_1[31:16]
// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
uint32_t src_buffer_low : 32; //[31:0]
uint32_t src_buffer_high : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_0 : 4, //[15:12]
length : 16; //[31:16]
uint32_t fw_metadata : 16, //[15:0]
ce_res_1 : 16; //[31:16]
uint32_t ce_res_2 : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
src_buffer_low
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
src_buffer_high
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
toeplitz_en
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
src_swap
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
dest_swap
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
gather
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
ce_res_0
Reserved
<legal all>
length
Length of the buffer in units of octets of the current
descriptor
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_1
Reserved
<legal all>
ce_res_2
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff
/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff
/* Description CE_SRC_DESC_1_TOEPLITZ_EN
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_SRC_DESC_1_SRC_SWAP
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200
/* Description CE_SRC_DESC_1_DEST_SWAP
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400
/* Description CE_SRC_DESC_1_GATHER
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
*/
#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_1_GATHER_LSB 11
#define CE_SRC_DESC_1_GATHER_MASK 0x00000800
/* Description CE_SRC_DESC_1_CE_RES_0
Reserved
<legal all>
*/
#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_1_CE_RES_0_LSB 12
#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000
/* Description CE_SRC_DESC_1_LENGTH
Length of the buffer in units of octets of the current
descriptor
<legal all>
*/
#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_1_LENGTH_LSB 16
#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000
/* Description CE_SRC_DESC_2_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_2_FW_METADATA_LSB 0
#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff
/* Description CE_SRC_DESC_2_CE_RES_1
Reserved
<legal all>
*/
#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
#define CE_SRC_DESC_2_CE_RES_1_LSB 16
#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000
/* Description CE_SRC_DESC_3_CE_RES_2
Reserved
<legal all>
*/
#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
#define CE_SRC_DESC_3_CE_RES_2_LSB 0
#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff
/* Description CE_SRC_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_3_RING_ID_LSB 20
#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_SRC_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_SRC_DESC_H_

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hw/qca6290/v1/ce_stat_desc.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
// 1 toeplitz_hash_0[31:0]
// 2 toeplitz_hash_1[31:0]
// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
uint32_t ce_res_5 : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_6 : 4, //[15:12]
length : 16; //[31:16]
uint32_t toeplitz_hash_0 : 32; //[31:0]
uint32_t toeplitz_hash_1 : 32; //[31:0]
uint32_t fw_metadata : 16, //[15:0]
ce_res_7 : 4, //[19:16]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
ce_res_5
Reserved
<legal all>
toeplitz_en
<legal all>
src_swap
Source memory buffer swapped
<legal all>
dest_swap
Destination memory buffer swapped
<legal all>
gather
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
ce_res_6
Reserved
<legal all>
length
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
toeplitz_hash_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
toeplitz_hash_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_7
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_STAT_DESC_0_CE_RES_5
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_5_LSB 0
#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff
/* Description CE_STAT_DESC_0_TOEPLITZ_EN
<legal all>
*/
#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_STAT_DESC_0_SRC_SWAP
Source memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_SRC_SWAP_LSB 9
#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200
/* Description CE_STAT_DESC_0_DEST_SWAP
Destination memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_DEST_SWAP_LSB 10
#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400
/* Description CE_STAT_DESC_0_GATHER
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
*/
#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_0_GATHER_LSB 11
#define CE_STAT_DESC_0_GATHER_MASK 0x00000800
/* Description CE_STAT_DESC_0_CE_RES_6
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_6_LSB 12
#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000
/* Description CE_STAT_DESC_0_LENGTH
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
*/
#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_0_LENGTH_LSB 16
#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000
/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff
/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff
/* Description CE_STAT_DESC_3_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_3_FW_METADATA_LSB 0
#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff
/* Description CE_STAT_DESC_3_CE_RES_7
Reserved
<legal all>
*/
#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_3_CE_RES_7_LSB 16
#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000
/* Description CE_STAT_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_3_RING_ID_LSB 20
#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_STAT_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_STAT_DESC_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
/**
@file com_dtypes.h
@brief This header file contains general data types that are of use to all
modules.
*/
/*===========================================================================
NOTE: The @brief description and any detailed descriptions above do not appear
in the PDF.
The Utility_Services_API_mainpage.dox file contains all file/group
descriptions that are in the output PDF generated using Doxygen and
Latex. To edit or update any of the file/group text in the PDF, edit
the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
The above description for this file is part of the "utils_services"
group description in the Utility_Services_API_mainpage.dox file.
===========================================================================*/
/*===========================================================================
S T A N D A R D D E C L A R A T I O N S
DESCRIPTION
This header file contains general data types that are of use to all modules.
The values or definitions are dependent on the specified
target. T_WINNT specifies Windows NT based targets, otherwise the
default is for ARM targets.
T_WINNT Software is hosted on an NT platforn, triggers macro and
type definitions, unlike definition above which triggers
actual OS calls
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $
when who what, where, why
-------- --- ----------------------------------------------------------
03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup.
11/09/10 EBR Doxygenated file.
09/15/09 pc Created file.
===========================================================================*/
/*===========================================================================
Data Declarations
===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
/* For NT apps we want to use the Win32 definitions and/or those
supplied by the Win32 compiler for things like NULL, MAX, MIN
abs, labs, etc.
*/
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
/* ------------------------------------------------------------------------
** Constants
** ------------------------------------------------------------------------ */
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
/** @addtogroup utils_services
@{ */
/** @name Macros for Common Data Types
@{ */
#define TRUE 1 /**< Boolean TRUE value. */
#define FALSE 0 /**< Boolean FALSE value. */
#define ON 1 /**< ON value. */
#define OFF 0 /**< OFF value. */
#ifndef NULL
#define NULL 0 /**< NULL value. */
#endif
/** @} */ /* end_name_group Macros for Common Data Types */
/* -----------------------------------------------------------------------
** Standard Types
** ----------------------------------------------------------------------- */
/** @} */ /* end_addtogroup utils_services */
/* The following definitions are the same across platforms. This first
group are the sanctioned types.
*/
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
/** @addtogroup utils_services
@{ */
/** Boolean value type.
*/
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
/** @cond
*/
#if defined(DALSTDDEF_H) /* guards against a known re-definer */
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif /* #if !defined(DALSTDDEF_H) */
/** @endcond */
#ifndef _UINT32_DEFINED
/** Unsigned 32-bit value.
*/
typedef unsigned long int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
/** Unsigned 16-bit value.
*/
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
/** Unsigned 8-bit value.
*/
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
/** Signed 32-bit value.
*/
typedef signed long int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
/** Signed 16-bit value.
*/
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
/** Signed 8-bit value.
*/
typedef signed char int8;
#define _INT8_DEFINED
#endif
/** @cond
*/
/* This group are the deprecated types. Their use should be
** discontinued and new code should use the types above
*/
#ifndef _BYTE_DEFINED
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
/** DEPRECATED: Unsinged 16 bit value type.
*/
typedef unsigned short word;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long dword;
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char uint1;
/** DEPRECATED: Unsigned 16 bit value type.
*/
typedef unsigned short uint2;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long uint4;
/** DEPRECATED: Signed 8 bit value type.
*/
typedef signed char int1;
/** DEPRECATED: Signed 16 bit value type.
*/
typedef signed short int2;
/** DEPRECATED: Signed 32 bit value type.
*/
typedef long int int4;
/** DEPRECATED: Signed 32 bit value.
*/
typedef signed long sint31;
/** DEPRECATED: Signed 16 bit value.
*/
typedef signed short sint15;
/** DEPRECATED: Signed 8 bit value.
*/
typedef signed char sint7;
typedef uint16 UWord16 ;
typedef uint32 UWord32 ;
typedef int32 Word32 ;
typedef int16 Word16 ;
typedef uint8 UWord8 ;
typedef int8 Word8 ;
typedef int32 Vect32 ;
/** @endcond */
#if (! defined T_WINNT) && (! defined __GNUC__)
/* Non WinNT Targets */
#ifndef _INT64_DEFINED
/** Signed 64-bit value.
*/
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
/** Unsigned 64-bit value.
*/
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
/* WINNT or SOLARIS based targets */
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64; /* Signed 64-bit value */
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64; /* Unsigned 64-bit value */
#define _UINT64_DEFINED
#endif
#endif
#endif /* T_WINNT */
#endif /* _ARM_ASM_ */
#ifdef __cplusplus
}
#endif
/** @} */ /* end_addtogroup utils_services */
#endif /* COM_DTYPES_H */

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
//////////////////////////////////////////////////////////////////////////////
// lithium_top_reg.h generated by: GenArmCHeader.pl
//////////////////////////////////////////////////////////////////////////////
// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
//////////////////////////////////////////////////////////////////////////////
// RCS File : -USE CVS LOG-
// Revision : -USE CVS LOG-
// Last Check In : -USE CVS LOG-
//////////////////////////////////////////////////////////////////////////////
// Description : Constants related to Hardware Registers
//
// Byte Addresses are used for all BASES and ADDRESSES
//////////////////////////////////////////////////////////////////////////////
#ifndef LITHIUM_TOP_REG_H
#define LITHIUM_TOP_REG_H
#define UMAC_CE_COMMON_CE_HOST_IE_0 (0x00A18034)
#define UMAC_CE_COMMON_CE_HOST_IE_1 (0x00A18038)
#endif

39
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __MAC_TCL_REG_SEQ_BASE_H__
#define __MAC_TCL_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

6821
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51
hw/qca6290/v1/msmhwio.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef MSMHWIO_H
#define MSMHWIO_H
/*
===========================================================================
*/
/**
@file msmhwio.h
Deprecated public interface include file for accessing the HWIO macro
definitions.
The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO)
register access definitions. See HALhwio.h and DDIHWIO.h for the new
interfaces.
*/
/*
====================================================================
$Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $
====================================================================
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Include main HWIO macros.
*/
#include "HALhwio.h"
#endif /* MSMHWIO_H */

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_DESTINATION_RING_H_
#define _REO_DESTINATION_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_mpdu_desc_info.h"
#include "rx_msdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info;
// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details;
// 6 rx_reo_queue_desc_addr_31_0[31:0]
// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
struct reo_destination_ring {
struct buffer_addr_info buf_or_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
reo_dest_buffer_type : 1, //[8]
reo_push_reason : 2, //[10:9]
reo_error_code : 5, //[15:11]
receive_queue_number : 16; //[31:16]
uint32_t soft_reorder_info_valid : 1, //[0]
reorder_opcode : 4, //[4:1]
reorder_slot_index : 8, //[12:5]
reserved_8a : 19; //[31:13]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15 : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
struct buffer_addr_info buf_or_link_desc_addr_info
Consumer: REO/SW/FW
Producer: RXDMA
Details of the physical address of the a buffer or MSDU
link descriptor
struct rx_mpdu_desc_info rx_mpdu_desc_info_details
Consumer: REO/SW/FW
Producer: RXDMA
General information related to the MPDU that is passed
on from REO entrance ring to the REO destination ring
struct rx_msdu_desc_info rx_msdu_desc_info_details
General information related to the MSDU that is passed
on from RXDMA all the way to to the REO destination ring.
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
reo_dest_buffer_type
Indicates the type of address provided in the
'Buf_or_link_desc_addr_info'
<enum 0 MSDU_buf_address> The address of an MSDU buffer
<enum 1 MSDU_link_desc_address> The address of the MSDU
link descriptor.
<legal all>
reo_push_reason
Indicates why REO pushed the frame to this exit ring
<enum 0 reo_error_detected> Reo detected an error an
pushed this frame to this queue
<enum 1 reo_routing_instruction> Reo pushed the frame to
this queue per received routing instructions. No error
within REO was detected
<legal 0 - 1>
reo_error_code
Field only valid when 'Reo_push_reason' set to
'reo_error_detected'.
<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
provided in the REO_ENTRANCE ring is set to 0
<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
valid bit is NOT set
<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
session having been setup.
<enum 3 non_ba_duplicate> Non-BA session, SN equal to
SSN, Retry bit set: duplicate frame
<enum 4 ba_duplicate> BA session, duplicate frame
<enum 5 regular_frame_2k_jump> A normal (management/data
frame) received with 2K jump in SN
<enum 6 bar_frame_2k_jump> A bar received with 2K jump
in SSN
<enum 7 regular_frame_OOR> A normal (management/data
frame) received with SN falling within the OOR window
<enum 8 bar_frame_OOR> A bar received with SSN falling
within the OOR window
<enum 9 bar_frame_no_ba_session> A bar received without
a BA session
<enum 10 bar_frame_sn_equals_ssn> A bar received with
SSN equal to SN
<enum 11 pn_check_failed> PN Check Failed packet.
<enum 12 2k_error_handling_flag_set> Frame is forwarded
as a result of the 'Seq_2k_error_detected_flag' been set in
the REO Queue descriptor
<enum 13 pn_error_handling_flag_set> Frame is forwarded
as a result of the 'pn_error_detected_flag' been set in the
REO Queue descriptor
<enum 14 queue_descriptor_blocked_set> Frame is
forwarded as a result of the queue descriptor(address) being
blocked as SW/FW seems to be currently in the process of
making updates to this descriptor...
<legal 0-14>
receive_queue_number
This field indicates the REO MPDU reorder queue ID from
which this frame originated. This field is populated from a
field with the same name in the RX_REO_QUEUE descriptor.
<legal all>
soft_reorder_info_valid
When set, REO has been instructed to not perform the
actual re-ordering of frames for this queue, but just to
insert the reorder opcodes
<legal all>
reorder_opcode
Field is valid when 'Soft_reorder_info_valid' is set.
This field is always valid for debug purpose as well.
Details are in the MLD.
<enum 0 invalid>
<enum 1 fwdcur_fwdbuf>
<enum 2 fwdbuf_fwdcur>
<enum 3 qcur>
<enum 4 fwdbuf_qcur>
<enum 5 fwdbuf_drop>
<enum 6 fwdall_drop>
<enum 7 fwdall_qcur>
<enum 8 reserved_reo_opcode_1>
<enum 9 dropcur> the error reason code is in
reo_error_code field.
<enum 10 reserved_reo_opcode_2>
<enum 11 reserved_reo_opcode_3>
<enum 12 reserved_reo_opcode_4>
<enum 13 reserved_reo_opcode_5>
<enum 14 reserved_reo_opcode_6>
<enum 15 reserved_reo_opcode_7>
<legal all>
reorder_slot_index
Field only valid when 'Soft_reorder_info_valid' is set.
TODO: add description
<legal all>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15
<legal 0>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE
Indicates the type of address provided in the
'Buf_or_link_desc_addr_info'
<enum 0 MSDU_buf_address> The address of an MSDU buffer
<enum 1 MSDU_link_desc_address> The address of the MSDU
link descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100
/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON
Indicates why REO pushed the frame to this exit ring
<enum 0 reo_error_detected> Reo detected an error an
pushed this frame to this queue
<enum 1 reo_routing_instruction> Reo pushed the frame to
this queue per received routing instructions. No error
within REO was detected
<legal 0 - 1>
*/
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600
/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE
Field only valid when 'Reo_push_reason' set to
'reo_error_detected'.
<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
provided in the REO_ENTRANCE ring is set to 0
<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
valid bit is NOT set
<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
session having been setup.
<enum 3 non_ba_duplicate> Non-BA session, SN equal to
SSN, Retry bit set: duplicate frame
<enum 4 ba_duplicate> BA session, duplicate frame
<enum 5 regular_frame_2k_jump> A normal (management/data
frame) received with 2K jump in SN
<enum 6 bar_frame_2k_jump> A bar received with 2K jump
in SSN
<enum 7 regular_frame_OOR> A normal (management/data
frame) received with SN falling within the OOR window
<enum 8 bar_frame_OOR> A bar received with SSN falling
within the OOR window
<enum 9 bar_frame_no_ba_session> A bar received without
a BA session
<enum 10 bar_frame_sn_equals_ssn> A bar received with
SSN equal to SN
<enum 11 pn_check_failed> PN Check Failed packet.
<enum 12 2k_error_handling_flag_set> Frame is forwarded
as a result of the 'Seq_2k_error_detected_flag' been set in
the REO Queue descriptor
<enum 13 pn_error_handling_flag_set> Frame is forwarded
as a result of the 'pn_error_detected_flag' been set in the
REO Queue descriptor
<enum 14 queue_descriptor_blocked_set> Frame is
forwarded as a result of the queue descriptor(address) being
blocked as SW/FW seems to be currently in the process of
making updates to this descriptor...
<legal 0-14>
*/
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800
/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
This field indicates the REO MPDU reorder queue ID from
which this frame originated. This field is populated from a
field with the same name in the RX_REO_QUEUE descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000
/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
When set, REO has been instructed to not perform the
actual re-ordering of frames for this queue, but just to
insert the reorder opcodes
<legal all>
*/
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001
/* Description REO_DESTINATION_RING_8_REORDER_OPCODE
Field is valid when 'Soft_reorder_info_valid' is set.
This field is always valid for debug purpose as well.
Details are in the MLD.
<enum 0 invalid>
<enum 1 fwdcur_fwdbuf>
<enum 2 fwdbuf_fwdcur>
<enum 3 qcur>
<enum 4 fwdbuf_qcur>
<enum 5 fwdbuf_drop>
<enum 6 fwdall_drop>
<enum 7 fwdall_qcur>
<enum 8 reserved_reo_opcode_1>
<enum 9 dropcur> the error reason code is in
reo_error_code field.
<enum 10 reserved_reo_opcode_2>
<enum 11 reserved_reo_opcode_3>
<enum 12 reserved_reo_opcode_4>
<enum 13 reserved_reo_opcode_5>
<enum 14 reserved_reo_opcode_6>
<enum 15 reserved_reo_opcode_7>
<legal all>
*/
#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1
#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e
/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX
Field only valid when 'Soft_reorder_info_valid' is set.
TODO: add description
<legal all>
*/
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0
/* Description REO_DESTINATION_RING_8_RESERVED_8A
<legal 0>
*/
#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13
#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000
/* Description REO_DESTINATION_RING_9_RESERVED_9A
<legal 0>
*/
#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024
#define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0
#define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_10_RESERVED_10A
<legal 0>
*/
#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028
#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0
#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_11_RESERVED_11A
<legal 0>
*/
#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0
#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_12_RESERVED_12A
<legal 0>
*/
#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030
#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0
#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_13_RESERVED_13A
<legal 0>
*/
#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034
#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0
#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_14_RESERVED_14A
<legal 0>
*/
#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038
#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0
#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_15_RESERVED_15
<legal 0>
*/
#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0
#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff
/* Description REO_DESTINATION_RING_15_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_RING_ID_LSB 20
#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000
/* Description REO_DESTINATION_RING_15_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_DESTINATION_RING_H_

722
hw/qca6290/v1/reo_entrance_ring.h Normal file
View file

@ -0,0 +1,722 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_ENTRANCE_RING_H_
#define _REO_ENTRANCE_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_details.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info;
// 4 rx_reo_queue_desc_addr_31_0[31:0]
// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7]
// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
struct reo_entrance_ring {
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
rounded_mpdu_byte_count : 14, //[21:8]
reo_destination_indication : 5, //[26:22]
frameless_bar : 1, //[27]
reserved_5a : 4; //[31:28]
uint32_t rxdma_push_reason : 2, //[1:0]
rxdma_error_code : 5, //[6:2]
reserved_6a : 25; //[31:7]
uint32_t reserved_7a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
struct rx_mpdu_details reo_level_mpdu_frame_info
Consumer: REO
Producer: RXDMA
Details related to the MPDU being pushed into the REO
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
rounded_mpdu_byte_count
An approximation of the number of bytes received in this
MPDU.
Used to keeps stats on the amount of data flowing
through a queue.
<legal all>
reo_destination_indication
RXDMA copy the MPDU's first MSDU's destination
indication field here. This is used for REO to be able to
re-route the packet to a different SW destination ring if
the packet is detected as error in REO.
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
frameless_bar
When set, this REO entrance ring struct contains BAR
info from a multi TID BAR frame. The original multi TID BAR
frame itself contained all the REO info for the first TID,
but all the subsequent TID info and their linkage to the REO
descriptors is passed down as 'frameless' BAR info.
The only fields valid in this descriptor when this bit
is set are:
Rx_reo_queue_desc_addr_31_0
RX_reo_queue_desc_addr_39_32
And within the
Reo_level_mpdu_frame_info:
Within Rx_mpdu_desc_info_details:
Mpdu_Sequence_number
BAR_frame
Peer_meta_data
All other fields shall be set to 0
<legal all>
reserved_5a
<legal 0>
rxdma_push_reason
Indicates why rxdma pushed the frame to this ring
<enum 0 rxdma_error_detected> RXDMA detected an error an
pushed this frame to this queue
<enum 1 rxdma_routing_instruction> RXDMA pushed the
frame to this queue per received routing instructions. No
error within RXDMA was detected
This field is ignored by REO.
<legal 0 - 1>
rxdma_error_code
Field only valid when 'rxdma_push_reason' set to
'rxdma_error_detected'.
This field is ignored by REO.
<enum 0 rxdma_overflow_err>MPDU frame is not complete
due to a FIFO overflow error in RXPCU.
<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
due to receiving incomplete MPDU from the PHY
<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
error
<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
error
<enum 5 rxdma_unecrypted_err>CRYPTO reported an
unencrypted frame error when encrypted was expected
<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
length error
<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
number of MSDUs allowed in an MPDU got exceeded
<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
error
<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
parsing error
<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
during SA search
<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
during DA search
<enum 12 rxdma_flow_timeout_err>RX OLE reported a
timeout during flow search
<enum 13 Rxdma_flush_request>RXDMA received a flush
request
reserved_6a
<legal 0>
reserved_7a
<legal 0>
ring_id
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
It help to identify the ring that is being looked <legal
all>
looping_count
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
An approximation of the number of bytes received in this
MPDU.
Used to keeps stats on the amount of data flowing
through a queue.
<legal all>
*/
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
RXDMA copy the MPDU's first MSDU's destination
indication field here. This is used for REO to be able to
re-route the packet to a different SW destination ring if
the packet is detected as error in REO.
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR
When set, this REO entrance ring struct contains BAR
info from a multi TID BAR frame. The original multi TID BAR
frame itself contained all the REO info for the first TID,
but all the subsequent TID info and their linkage to the REO
descriptors is passed down as 'frameless' BAR info.
The only fields valid in this descriptor when this bit
is set are:
Rx_reo_queue_desc_addr_31_0
RX_reo_queue_desc_addr_39_32
And within the
Reo_level_mpdu_frame_info:
Within Rx_mpdu_desc_info_details:
Mpdu_Sequence_number
BAR_frame
Peer_meta_data
All other fields shall be set to 0
<legal all>
*/
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
/* Description REO_ENTRANCE_RING_5_RESERVED_5A
<legal 0>
*/
#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
Indicates why rxdma pushed the frame to this ring
<enum 0 rxdma_error_detected> RXDMA detected an error an
pushed this frame to this queue
<enum 1 rxdma_routing_instruction> RXDMA pushed the
frame to this queue per received routing instructions. No
error within RXDMA was detected
This field is ignored by REO.
<legal 0 - 1>
*/
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
Field only valid when 'rxdma_push_reason' set to
'rxdma_error_detected'.
This field is ignored by REO.
<enum 0 rxdma_overflow_err>MPDU frame is not complete
due to a FIFO overflow error in RXPCU.
<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
due to receiving incomplete MPDU from the PHY
<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
error
<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
error
<enum 5 rxdma_unecrypted_err>CRYPTO reported an
unencrypted frame error when encrypted was expected
<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
length error
<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
number of MSDUs allowed in an MPDU got exceeded
<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
error
<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
parsing error
<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
during SA search
<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
during DA search
<enum 12 rxdma_flow_timeout_err>RX OLE reported a
timeout during flow search
<enum 13 Rxdma_flush_request>RXDMA received a flush
request
*/
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
/* Description REO_ENTRANCE_RING_6_RESERVED_6A
<legal 0>
*/
#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7
#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80
/* Description REO_ENTRANCE_RING_7_RESERVED_7A
<legal 0>
*/
#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0
#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff
/* Description REO_ENTRANCE_RING_7_RING_ID
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
It help to identify the ring that is being looked <legal
all>
*/
#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_RING_ID_LSB 20
#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_ENTRANCE_RING_H_

305
hw/qca6290/v1/reo_get_queue_stats.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_GET_QUEUE_STATS_H_
#define _REO_GET_QUEUE_STATS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 rx_reo_queue_desc_addr_31_0[31:0]
// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
struct reo_get_queue_stats {
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
clear_stats : 1, //[8]
reserved_2a : 23; //[31:9]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the REO queue descriptor
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the REO queue descriptor
<legal all>
clear_stats
Clear stat settings....
<enum 0 no_clear> Do NOT clear the stats after
generating the status
<enum 1 clear_the_stats> Clear the stats after
generating the status.
The stats actually cleared are:
Timeout_count
Forward_due_to_bar_count
Duplicate_count
Frames_in_order_count
BAR_received_count
MPDU_Frames_processed_count
MSDU_Frames_processed_count
Total_processed_byte_count
Late_receive_MPDU_count
window_jump_2k
Hole_count
<legal 0-1>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the REO queue descriptor
<legal all>
*/
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the REO queue descriptor
<legal all>
*/
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS
Clear stat settings....
<enum 0 no_clear> Do NOT clear the stats after
generating the status
<enum 1 clear_the_stats> Clear the stats after
generating the status.
The stats actually cleared are:
Timeout_count
Forward_due_to_bar_count
Duplicate_count
Frames_in_order_count
BAR_received_count
MPDU_Frames_processed_count
MSDU_Frames_processed_count
Total_processed_byte_count
Late_receive_MPDU_count
window_jump_2k
Hole_count
<legal 0-1>
*/
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8
#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100
/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9
#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00
/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0
#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0
#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0
#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0
#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0
#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0
#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_GET_QUEUE_STATS_H_

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hw/qca6290/v1/reo_get_queue_stats_status.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
#define _REO_GET_QUEUE_STATS_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 ssn[11:0], current_index[19:12], reserved_2[31:20]
// 3 pn_31_0[31:0]
// 4 pn_63_32[31:0]
// 5 pn_95_64[31:0]
// 6 pn_127_96[31:0]
// 7 last_rx_enqueue_timestamp[31:0]
// 8 last_rx_dequeue_timestamp[31:0]
// 9 rx_bitmap_31_0[31:0]
// 10 rx_bitmap_63_32[31:0]
// 11 rx_bitmap_95_64[31:0]
// 12 rx_bitmap_127_96[31:0]
// 13 rx_bitmap_159_128[31:0]
// 14 rx_bitmap_191_160[31:0]
// 15 rx_bitmap_223_192[31:0]
// 16 rx_bitmap_255_224[31:0]
// 17 current_mpdu_count[6:0], current_msdu_count[31:7]
// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
// 19 frames_in_order_count[23:0], bar_received_count[31:24]
// 20 mpdu_frames_processed_count[31:0]
// 21 msdu_frames_processed_count[31:0]
// 22 total_processed_byte_count[31:0]
// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
struct reo_get_queue_stats_status {
struct uniform_reo_status_header status_header;
uint32_t ssn : 12, //[11:0]
current_index : 8, //[19:12]
reserved_2 : 12; //[31:20]
uint32_t pn_31_0 : 32; //[31:0]
uint32_t pn_63_32 : 32; //[31:0]
uint32_t pn_95_64 : 32; //[31:0]
uint32_t pn_127_96 : 32; //[31:0]
uint32_t last_rx_enqueue_timestamp : 32; //[31:0]
uint32_t last_rx_dequeue_timestamp : 32; //[31:0]
uint32_t rx_bitmap_31_0 : 32; //[31:0]
uint32_t rx_bitmap_63_32 : 32; //[31:0]
uint32_t rx_bitmap_95_64 : 32; //[31:0]
uint32_t rx_bitmap_127_96 : 32; //[31:0]
uint32_t rx_bitmap_159_128 : 32; //[31:0]
uint32_t rx_bitmap_191_160 : 32; //[31:0]
uint32_t rx_bitmap_223_192 : 32; //[31:0]
uint32_t rx_bitmap_255_224 : 32; //[31:0]
uint32_t current_mpdu_count : 7, //[6:0]
current_msdu_count : 25; //[31:7]
uint32_t reserved_18 : 4, //[3:0]
timeout_count : 6, //[9:4]
forward_due_to_bar_count : 6, //[15:10]
duplicate_count : 16; //[31:16]
uint32_t frames_in_order_count : 24, //[23:0]
bar_received_count : 8; //[31:24]
uint32_t mpdu_frames_processed_count : 32; //[31:0]
uint32_t msdu_frames_processed_count : 32; //[31:0]
uint32_t total_processed_byte_count : 32; //[31:0]
uint32_t late_receive_mpdu_count : 12, //[11:0]
window_jump_2k : 4, //[15:12]
hole_count : 16; //[31:16]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
ssn
Starting Sequence number of the session, this changes
whenever window moves. (can be filled by SW then maintained
by REO)
<legal all>
current_index
Points to last forwarded packet
<legal all>
reserved_2
<legal 0>
pn_31_0
<legal all>
pn_63_32
Bits [63:32] of the PN number.
<legal all>
pn_95_64
Bits [95:64] of the PN number.
<legal all>
pn_127_96
Bits [127:96] of the PN number.
<legal all>
last_rx_enqueue_timestamp
Timestamp of arrival of the last MPDU for this queue
<legal all>
last_rx_dequeue_timestamp
Timestamp of forwarding an MPDU
If the queue is empty when a frame gets received, this
time shall be initialized to the 'enqueue' timestamp
Used for aging
<legal all>
rx_bitmap_31_0
When a bit is set, the corresponding frame is currently
held in the re-order queue.
The bitmap is Fully managed by HW.
SW shall init this to 0, and then never ever change it
<legal all>
rx_bitmap_63_32
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_95_64
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_127_96
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_159_128
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_191_160
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_223_192
See Rx_bitmap_31_0 description
<legal all>
rx_bitmap_255_224
See Rx_bitmap_31_0 description
<legal all>
current_mpdu_count
The number of MPDUs in the queue.
<legal all>
current_msdu_count
The number of MSDUs in the queue.
<legal all>
reserved_18
<legal 0>
timeout_count
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is Timeout
The counter saturates and freezes at 0x3F
<legal all>
forward_due_to_bar_count
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is reception of BAR frame.
The counter saturates and freezes at 0x3F
<legal all>
duplicate_count
The number of duplicate frames that have been detected
<legal all>
frames_in_order_count
The number of frames that have been received in order
(without a hole that prevented them from being forwarded
immediately)
This corresponds to the Reorder opcodes:
'FWDCUR' and 'FWD BUF'
<legal all>
bar_received_count
The number of times a BAR frame is received.
This corresponds to the Reorder opcodes with 'DROP'
The counter saturates and freezes at 0xFF
<legal all>
mpdu_frames_processed_count
The total number of MPDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
msdu_frames_processed_count
The total number of MSDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
total_processed_byte_count
An approximation of the number of bytes received for
this queue.
In 64 byte units
<legal all>
late_receive_mpdu_count
The number of MPDUs received after the window had
already moved on. The 'late' sequence window is defined as
(Window SSN - 256) - (Window SSN - 1)
This corresponds with Out of order detection in
duplicate detect FSM
The counter saturates and freezes at 0xFFF
<legal all>
window_jump_2k
The number of times the window moved more then 2K
The counter saturates and freezes at 0xF
(Note: field name can not start with number: previous
2k_window_jump)
<legal all>
hole_count
The number of times a hole was created in the receive
bitmap.
This corresponds to the Reorder opcodes with 'QCUR'
<legal all>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN
Starting Sequence number of the session, this changes
whenever window moves. (can be filled by SW then maintained
by REO)
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff
/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX
Points to last forwarded packet
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000
/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20
#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000
/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32
Bits [63:32] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64
Bits [95:64] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96
Bits [127:96] of the PN number.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP
Timestamp of arrival of the last MPDU for this queue
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP
Timestamp of forwarding an MPDU
If the queue is empty when a frame gets received, this
time shall be initialized to the 'enqueue' timestamp
Used for aging
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0
When a bit is set, the corresponding frame is currently
held in the re-order queue.
The bitmap is Fully managed by HW.
SW shall init this to 0, and then never ever change it
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224
See Rx_bitmap_31_0 description
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT
The number of MPDUs in the queue.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f
/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT
The number of MSDUs in the queue.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7
#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80
/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f
/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is Timeout
The counter saturates and freezes at 0x3F
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4
#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0
/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT
The number of times that REO started forwarding frames
even though there is a hole in the bitmap. Forwarding reason
is reception of BAR frame.
The counter saturates and freezes at 0x3F
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10
#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT
The number of duplicate frames that have been detected
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000
/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT
The number of frames that have been received in order
(without a hole that prevented them from being forwarded
immediately)
This corresponds to the Reorder opcodes:
'FWDCUR' and 'FWD BUF'
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT
The number of times a BAR frame is received.
This corresponds to the Reorder opcodes with 'DROP'
The counter saturates and freezes at 0xFF
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24
#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000
/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT
The total number of MPDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT
The total number of MSDU frames that have been processed
by REO. This includes the duplicates.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT
An approximation of the number of bytes received for
this queue.
In 64 byte units
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT
The number of MPDUs received after the window had
already moved on. The 'late' sequence window is defined as
(Window SSN - 256) - (Window SSN - 1)
This corresponds with Out of order detection in
duplicate detect FSM
The counter saturates and freezes at 0xFFF
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K
The number of times the window moved more then 2K
The counter saturates and freezes at 0xF
(Note: field name can not start with number: previous
2k_window_jump)
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000
/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT
The number of times a hole was created in the receive
bitmap.
This corresponds to the Reorder opcodes with 'QCUR'
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000
/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_GET_QUEUE_STATS_STATUS_H_

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hw/qca6290/v1/reo_reg_seq_hwiobase.h Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __REO_REG_SEQ_BASE_H__
#define __REO_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

8639
hw/qca6290/v1/reo_reg_seq_hwioreg.h Normal file
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1168
hw/qca6290/v1/rx_attention.h Normal file
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466
hw/qca6290/v1/rx_mpdu_desc_info.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MPDU_DESC_INFO_H_
#define _RX_MPDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], reserved[31]
// 1 peer_meta_data[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
struct rx_mpdu_desc_info {
uint32_t msdu_count : 8, //[7:0]
mpdu_sequence_number : 12, //[19:8]
fragment_flag : 1, //[20]
mpdu_retry_bit : 1, //[21]
ampdu_flag : 1, //[22]
bar_frame : 1, //[23]
pn_fields_contain_valid_info : 1, //[24]
sa_is_valid : 1, //[25]
sa_idx_timeout : 1, //[26]
da_is_valid : 1, //[27]
da_is_mcbc : 1, //[28]
da_idx_timeout : 1, //[29]
raw_mpdu : 1, //[30]
reserved : 1; //[31]
uint32_t peer_meta_data : 32; //[31:0]
};
/*
msdu_count
Consumer: REO/SW/FW
Producer: RXDMA
The number of MSDUs within the MPDU
<legal all>
mpdu_sequence_number
Consumer: REO/SW/FW
Producer: RXDMA
The field can have two different meanings based on the
setting of field 'BAR_frame':
'BAR_frame' is NOT set:
The MPDU sequence number of the received frame.
'BAR_frame' is set.
The MPDU Start sequence number from the BAR frame
<legal all>
fragment_flag
Consumer: REO/SW/FW
Producer: RXDMA
When set, this MPDU is a fragment and REO should forward
this fragment MPDU to the REO destination ring without any
reorder checks, pn checks or bitmap update. This implies
that REO is forwarding the pointer to the MSDU link
descriptor. The destination ring is coming from a
programmable register setting in REO
<legal all>
mpdu_retry_bit
Consumer: REO/SW/FW
Producer: RXDMA
The retry bit setting from the MPDU header of the
received frame
<legal all>
ampdu_flag
Consumer: REO/SW/FW
Producer: RXDMA
When set, the MPDU was received as part of an A-MPDU.
<legal all>
bar_frame
Consumer: REO/SW/FW
Producer: RXDMA
When set, the received frame is a BAR frame. After
processing, this frame shall be pushed to SW or deleted.
<legal all>
pn_fields_contain_valid_info
Consumer: REO/SW/FW
Producer: RXDMA
Copied here by RXDMA from RX_MPDU_END
When not set, REO will Not perform a PN sequence number
check
sa_is_valid
When set, OLE found a valid SA entry for all MSDUs in
this MPDU
<legal all>
sa_idx_timeout
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC source address search due to the expiration
of the search timer.
<legal all>
da_is_valid
When set, OLE found a valid DA entry for all MSDUs in
this MPDU
<legal all>
da_is_mcbc
Field Only valid if da_is_valid is set
When set, at least one of the DA addresses is a
Multicast or Broadcast address.
<legal all>
da_idx_timeout
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC destination address search due to the
expiration of the search timer.
<legal all>
raw_mpdu
Field only valid when first_msdu_in_mpdu_flag is set.
When set, the contents in the MSDU buffer contains a
'RAW' MPDU. This 'RAW' MPDU might be spread out over
multiple MSDU buffers.
<legal all>
reserved
<legal 0>
peer_meta_data
Meta data that SW has programmed in the Peer table entry
of the transmitting STA.
<legal all>
*/
/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT
Consumer: REO/SW/FW
Producer: RXDMA
The number of MSDUs within the MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0
#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff
/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER
Consumer: REO/SW/FW
Producer: RXDMA
The field can have two different meanings based on the
setting of field 'BAR_frame':
'BAR_frame' is NOT set:
The MPDU sequence number of the received frame.
'BAR_frame' is set.
The MPDU Start sequence number from the BAR frame
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8
#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, this MPDU is a fragment and REO should forward
this fragment MPDU to the REO destination ring without any
reorder checks, pn checks or bitmap update. This implies
that REO is forwarding the pointer to the MSDU link
descriptor. The destination ring is coming from a
programmable register setting in REO
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20
#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000
/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT
Consumer: REO/SW/FW
Producer: RXDMA
The retry bit setting from the MPDU header of the
received frame
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21
#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000
/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG
Consumer: REO/SW/FW
Producer: RXDMA
When set, the MPDU was received as part of an A-MPDU.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22
#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000
/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME
Consumer: REO/SW/FW
Producer: RXDMA
When set, the received frame is a BAR frame. After
processing, this frame shall be pushed to SW or deleted.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23
#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000
/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO
Consumer: REO/SW/FW
Producer: RXDMA
Copied here by RXDMA from RX_MPDU_END
When not set, REO will Not perform a PN sequence number
check
*/
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID
When set, OLE found a valid SA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25
#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000
/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC source address search due to the expiration
of the search timer.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26
#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000
/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID
When set, OLE found a valid DA entry for all MSDUs in
this MPDU
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27
#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000
/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC
Field Only valid if da_is_valid is set
When set, at least one of the DA addresses is a
Multicast or Broadcast address.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28
#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000
/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT
When set, at least 1 MSDU within the MPDU has an
unsuccessful MAC destination address search due to the
expiration of the search timer.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29
#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000
/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU
Field only valid when first_msdu_in_mpdu_flag is set.
When set, the contents in the MSDU buffer contains a
'RAW' MPDU. This 'RAW' MPDU might be spread out over
multiple MSDU buffers.
<legal all>
*/
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30
#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000
/* Description RX_MPDU_DESC_INFO_0_RESERVED
<legal 0>
*/
#define RX_MPDU_DESC_INFO_0_RESERVED_OFFSET 0x00000000
#define RX_MPDU_DESC_INFO_0_RESERVED_LSB 31
#define RX_MPDU_DESC_INFO_0_RESERVED_MASK 0x80000000
/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA
Meta data that SW has programmed in the Peer table entry
of the transmitting STA.
<legal all>
*/
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0
#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff
#endif // _RX_MPDU_DESC_INFO_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MPDU_DETAILS_H_
#define _RX_MPDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_mpdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info msdu_link_desc_addr_info;
// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
struct rx_mpdu_details {
struct buffer_addr_info msdu_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
};
/*
struct buffer_addr_info msdu_link_desc_addr_info
Consumer: REO/SW/FW
Producer: RXDMA
Details of the physical address of the MSDU link
descriptor that contains pointers to MSDUs related to this
MPDU
struct rx_mpdu_desc_info rx_mpdu_desc_info_details
Consumer: REO/SW/FW
Producer: RXDMA
General information related to the MPDU that should be
*/
#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0
#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0
#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#endif // _RX_MPDU_DETAILS_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MPDU_END_H_
#define _RX_MPDU_END_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_END 2
struct rx_mpdu_end {
uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
sw_frame_group_id : 7, //[8:2]
reserved_0 : 7, //[15:9]
phy_ppdu_id : 16; //[31:16]
uint32_t reserved_1a : 11, //[10:0]
unsup_ktype_short_frame : 1, //[11]
rx_in_tx_decrypt_byp : 1, //[12]
overflow_err : 1, //[13]
mpdu_length_err : 1, //[14]
tkip_mic_err : 1, //[15]
decrypt_err : 1, //[16]
unencrypted_frame_err : 1, //[17]
pn_fields_contain_valid_info : 1, //[18]
fcs_err : 1, //[19]
msdu_length_err : 1, //[20]
rxdma0_destination_ring : 2, //[22:21]
rxdma1_destination_ring : 2, //[24:23]
decrypt_status_code : 3, //[27:25]
rx_bitmap_not_updated : 1, //[28]
reserved_1b : 3; //[31:29]
};
/*
rxpcu_mpdu_filter_in_category
Field indicates what the reason was that this MPDU frame
was allowed to come into the receive path by RXPCU
<enum 0 rxpcu_filter_pass> This MPDU passed the normal
frame filter programming of rxpcu
<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
regular frame filter and would have been dropped, were it
not for the frame fitting into the 'monitor_client'
category.
<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
regular frame filter and also did not pass the
rxpcu_monitor_client filter. It would have been dropped
accept that it did pass the 'monitor_other' category.
<legal 0-2>
sw_frame_group_id
SW processes frames based on certain classifications.
This field indicates to what sw classification this MPDU is
mapped.
The classification is given in priority order
<enum 0 sw_frame_group_NDP_frame>
<enum 1 sw_frame_group_Multicast_data>
<enum 2 sw_frame_group_Unicast_data>
<enum 3 sw_frame_group_Null_data > This includes mpdus
of type Data Null as well as QoS Data Null
<enum 4 sw_frame_group_mgmt_0000 >
<enum 5 sw_frame_group_mgmt_0001 >
<enum 6 sw_frame_group_mgmt_0010 >
<enum 7 sw_frame_group_mgmt_0011 >
<enum 8 sw_frame_group_mgmt_0100 >
<enum 9 sw_frame_group_mgmt_0101 >
<enum 10 sw_frame_group_mgmt_0110 >
<enum 11 sw_frame_group_mgmt_0111 >
<enum 12 sw_frame_group_mgmt_1000 >
<enum 13 sw_frame_group_mgmt_1001 >
<enum 14 sw_frame_group_mgmt_1010 >
<enum 15 sw_frame_group_mgmt_1011 >
<enum 16 sw_frame_group_mgmt_1100 >
<enum 17 sw_frame_group_mgmt_1101 >
<enum 18 sw_frame_group_mgmt_1110 >
<enum 19 sw_frame_group_mgmt_1111 >
<enum 20 sw_frame_group_ctrl_0000 >
<enum 21 sw_frame_group_ctrl_0001 >
<enum 22 sw_frame_group_ctrl_0010 >
<enum 23 sw_frame_group_ctrl_0011 >
<enum 24 sw_frame_group_ctrl_0100 >
<enum 25 sw_frame_group_ctrl_0101 >
<enum 26 sw_frame_group_ctrl_0110 >
<enum 27 sw_frame_group_ctrl_0111 >
<enum 28 sw_frame_group_ctrl_1000 >
<enum 29 sw_frame_group_ctrl_1001 >
<enum 30 sw_frame_group_ctrl_1010 >
<enum 31 sw_frame_group_ctrl_1011 >
<enum 32 sw_frame_group_ctrl_1100 >
<enum 33 sw_frame_group_ctrl_1101 >
<enum 34 sw_frame_group_ctrl_1110 >
<enum 35 sw_frame_group_ctrl_1111 >
<enum 36 sw_frame_group_unsupported> This covers type 3
and protocol version != 0
<legal 0-37>
reserved_0
<legal 0>
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
reserved_1a
<legal 0>
unsup_ktype_short_frame
This bit will be '1' when WEP or TKIP or WAPI key type
is received for 11ah short frame. Crypto will bypass the
received packet without decryption to RxOLE after setting
this bit.
rx_in_tx_decrypt_byp
Indicates that RX packet is not decrypted as Crypto is
busy with TX packet processing.
overflow_err
RXPCU Receive FIFO ran out of space to receive the full
MPDU. Therefor this MPDU is terminated early and is thus
corrupted.
This MPDU will not be ACKed.
RXPCU might still be able to correctly receive the
following MPDUs in the PPDU if enough fifo space became
available in time
mpdu_length_err
Set by RXPCU if the expected MPDU length does not
correspond with the actually received number of bytes in the
MPDU.
tkip_mic_err
Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
for this MPDU
decrypt_err
Set by RX CRYPTO when CRYPTO detected a decrypt error
for this MPDU.
unencrypted_frame_err
Set by RX CRYPTO when CRYPTO detected an unencrypted
frame while in the peer entry field
'All_frames_shall_be_encrypted' is set.
pn_fields_contain_valid_info
Set by RX CRYPTO to indicate that there is a valid PN
field present in this MPDU
fcs_err
Set by RXPCU when there is an FCS error detected for
this MPDU
msdu_length_err
Set by RXOLE when there is an msdu length error detected
in at least 1 of the MSDUs embedded within the MPDU
rxdma0_destination_ring
The ring to which RXDMA0 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA0 might change the RXDMA0 destination
<enum 0 rxdma_release_ring > RXDMA0 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
to the REO entrance ring
<legal all>
rxdma1_destination_ring
The ring to which RXDMA1 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA1 might change the RXDMA destination
<enum 0 rxdma_release_ring > RXDMA1 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
to the REO entrance ring
<legal all>
decrypt_status_code
Field provides insight into the decryption performed
<enum 0 decrypt_ok> Frame had protection enabled and
decrypted properly
<enum 1 decrypt_unprotected_frame > Frame is unprotected
and hence bypassed
<enum 2 decrypt_data_err > Frame has protection enabled
and could not be properly decrypted due to MIC/ICV mismatch
etc.
<enum 3 decrypt_key_invalid > Frame has protection
enabled but the key that was required to decrypt this frame
was not valid
<enum 4 decrypt_peer_entry_invalid > Frame has
protection enabled but the key that was required to decrypt
this frame was not valid
<enum 5 decrypt_other > Reserved for other indications
<legal 0 - 5>
rx_bitmap_not_updated
Frame is received, but RXPCU could not update the
receive bitmap due to (temporary) fifo contraints.
<legal all>
reserved_1b
<legal 0>
*/
/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
Field indicates what the reason was that this MPDU frame
was allowed to come into the receive path by RXPCU
<enum 0 rxpcu_filter_pass> This MPDU passed the normal
frame filter programming of rxpcu
<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
regular frame filter and would have been dropped, were it
not for the frame fitting into the 'monitor_client'
category.
<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
regular frame filter and also did not pass the
rxpcu_monitor_client filter. It would have been dropped
accept that it did pass the 'monitor_other' category.
<legal 0-2>
*/
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID
SW processes frames based on certain classifications.
This field indicates to what sw classification this MPDU is
mapped.
The classification is given in priority order
<enum 0 sw_frame_group_NDP_frame>
<enum 1 sw_frame_group_Multicast_data>
<enum 2 sw_frame_group_Unicast_data>
<enum 3 sw_frame_group_Null_data > This includes mpdus
of type Data Null as well as QoS Data Null
<enum 4 sw_frame_group_mgmt_0000 >
<enum 5 sw_frame_group_mgmt_0001 >
<enum 6 sw_frame_group_mgmt_0010 >
<enum 7 sw_frame_group_mgmt_0011 >
<enum 8 sw_frame_group_mgmt_0100 >
<enum 9 sw_frame_group_mgmt_0101 >
<enum 10 sw_frame_group_mgmt_0110 >
<enum 11 sw_frame_group_mgmt_0111 >
<enum 12 sw_frame_group_mgmt_1000 >
<enum 13 sw_frame_group_mgmt_1001 >
<enum 14 sw_frame_group_mgmt_1010 >
<enum 15 sw_frame_group_mgmt_1011 >
<enum 16 sw_frame_group_mgmt_1100 >
<enum 17 sw_frame_group_mgmt_1101 >
<enum 18 sw_frame_group_mgmt_1110 >
<enum 19 sw_frame_group_mgmt_1111 >
<enum 20 sw_frame_group_ctrl_0000 >
<enum 21 sw_frame_group_ctrl_0001 >
<enum 22 sw_frame_group_ctrl_0010 >
<enum 23 sw_frame_group_ctrl_0011 >
<enum 24 sw_frame_group_ctrl_0100 >
<enum 25 sw_frame_group_ctrl_0101 >
<enum 26 sw_frame_group_ctrl_0110 >
<enum 27 sw_frame_group_ctrl_0111 >
<enum 28 sw_frame_group_ctrl_1000 >
<enum 29 sw_frame_group_ctrl_1001 >
<enum 30 sw_frame_group_ctrl_1010 >
<enum 31 sw_frame_group_ctrl_1011 >
<enum 32 sw_frame_group_ctrl_1100 >
<enum 33 sw_frame_group_ctrl_1101 >
<enum 34 sw_frame_group_ctrl_1110 >
<enum 35 sw_frame_group_ctrl_1111 >
<enum 36 sw_frame_group_unsupported> This covers type 3
and protocol version != 0
<legal 0-37>
*/
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
/* Description RX_MPDU_END_0_RESERVED_0
<legal 0>
*/
#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
#define RX_MPDU_END_0_RESERVED_0_LSB 9
#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
/* Description RX_MPDU_END_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
/* Description RX_MPDU_END_1_RESERVED_1A
<legal 0>
*/
#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
#define RX_MPDU_END_1_RESERVED_1A_LSB 0
#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
This bit will be '1' when WEP or TKIP or WAPI key type
is received for 11ah short frame. Crypto will bypass the
received packet without decryption to RxOLE after setting
this bit.
*/
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
Indicates that RX packet is not decrypted as Crypto is
busy with TX packet processing.
*/
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
/* Description RX_MPDU_END_1_OVERFLOW_ERR
RXPCU Receive FIFO ran out of space to receive the full
MPDU. Therefor this MPDU is terminated early and is thus
corrupted.
This MPDU will not be ACKed.
RXPCU might still be able to correctly receive the
following MPDUs in the PPDU if enough fifo space became
available in time
*/
#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR
Set by RXPCU if the expected MPDU length does not
correspond with the actually received number of bytes in the
MPDU.
*/
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
/* Description RX_MPDU_END_1_TKIP_MIC_ERR
Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
for this MPDU
*/
#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
/* Description RX_MPDU_END_1_DECRYPT_ERR
Set by RX CRYPTO when CRYPTO detected a decrypt error
for this MPDU.
*/
#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
Set by RX CRYPTO when CRYPTO detected an unencrypted
frame while in the peer entry field
'All_frames_shall_be_encrypted' is set.
*/
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
Set by RX CRYPTO to indicate that there is a valid PN
field present in this MPDU
*/
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
/* Description RX_MPDU_END_1_FCS_ERR
Set by RXPCU when there is an FCS error detected for
this MPDU
*/
#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_FCS_ERR_LSB 19
#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR
Set by RXOLE when there is an msdu length error detected
in at least 1 of the MSDUs embedded within the MPDU
*/
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING
The ring to which RXDMA0 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA0 might change the RXDMA0 destination
<enum 0 rxdma_release_ring > RXDMA0 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
to the REO entrance ring
<legal all>
*/
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING
The ring to which RXDMA1 shall push the frame, assuming
no MPDU level errors are detected. In case of MPDU level
errors, RXDMA1 might change the RXDMA destination
<enum 0 rxdma_release_ring > RXDMA1 shall push the
frame to the Release ring. Effectively this means the frame
needs to be dropped.
<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
the FW ring
<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
the SW ring
<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
to the REO entrance ring
<legal all>
*/
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE
Field provides insight into the decryption performed
<enum 0 decrypt_ok> Frame had protection enabled and
decrypted properly
<enum 1 decrypt_unprotected_frame > Frame is unprotected
and hence bypassed
<enum 2 decrypt_data_err > Frame has protection enabled
and could not be properly decrypted due to MIC/ICV mismatch
etc.
<enum 3 decrypt_key_invalid > Frame has protection
enabled but the key that was required to decrypt this frame
was not valid
<enum 4 decrypt_peer_entry_invalid > Frame has
protection enabled but the key that was required to decrypt
this frame was not valid
<enum 5 decrypt_other > Reserved for other indications
<legal 0 - 5>
*/
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
Frame is received, but RXPCU could not update the
receive bitmap due to (temporary) fifo contraints.
<legal all>
*/
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
/* Description RX_MPDU_END_1_RESERVED_1B
<legal 0>
*/
#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
#define RX_MPDU_END_1_RESERVED_1B_LSB 29
#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
#endif // _RX_MPDU_END_H_

2871
hw/qca6290/v1/rx_mpdu_info.h Normal file
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61
hw/qca6290/v1/rx_mpdu_link_ptr.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MPDU_LINK_PTR_H_
#define _RX_MPDU_LINK_PTR_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
struct rx_mpdu_link_ptr {
struct buffer_addr_info mpdu_link_desc_addr_info;
};
/*
struct buffer_addr_info mpdu_link_desc_addr_info
Details of the physical address of an MPDU link
descriptor
*/
#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#endif // _RX_MPDU_LINK_PTR_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MPDU_START_H_
#define _RX_MPDU_START_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-22 struct rx_mpdu_info rx_mpdu_info_details;
// 23 raw_mpdu[0], reserved_23[31:1]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MPDU_START 24
struct rx_mpdu_start {
struct rx_mpdu_info rx_mpdu_info_details;
uint32_t raw_mpdu : 1, //[0]
reserved_23 : 31; //[31:1]
};
/*
struct rx_mpdu_info rx_mpdu_info_details
Structure containing all the MPDU header details that
might be needed for other modules further down the received
path
raw_mpdu
Set by OLE when it has not performed any .11 to .3
header conversion on this MPDU.
<legal all>
reserved_23
<legal 0>
*/
#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000000
#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000004
#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000008
#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000000c
#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000010
#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000014
#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000018
#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000001c
#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000020
#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000024
#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000028
#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000002c
#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000030
#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000034
#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000038
#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000003c
#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000040
#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000044
#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000048
#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x0000004c
#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000050
#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000054
#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 0x00000058
#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB 1
#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK 0xffffffff
/* Description RX_MPDU_START_23_RAW_MPDU
Set by OLE when it has not performed any .11 to .3
header conversion on this MPDU.
<legal all>
*/
#define RX_MPDU_START_23_RAW_MPDU_OFFSET 0x0000005c
#define RX_MPDU_START_23_RAW_MPDU_LSB 0
#define RX_MPDU_START_23_RAW_MPDU_MASK 0x00000001
/* Description RX_MPDU_START_23_RESERVED_23
<legal 0>
*/
#define RX_MPDU_START_23_RESERVED_23_OFFSET 0x0000005c
#define RX_MPDU_START_23_RESERVED_23_LSB 1
#define RX_MPDU_START_23_RESERVED_23_MASK 0xfffffffe
#endif // _RX_MPDU_START_H_

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hw/qca6290/v1/rx_msdu_desc_info.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MSDU_DESC_INFO_H_
#define _RX_MSDU_DESC_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], reserved_0a[31:28]
// 1 reserved_1a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
struct rx_msdu_desc_info {
uint32_t first_msdu_in_mpdu_flag : 1, //[0]
last_msdu_in_mpdu_flag : 1, //[1]
msdu_continuation : 1, //[2]
msdu_length : 14, //[16:3]
reo_destination_indication : 5, //[21:17]
msdu_drop : 1, //[22]
sa_is_valid : 1, //[23]
sa_idx_timeout : 1, //[24]
da_is_valid : 1, //[25]
da_is_mcbc : 1, //[26]
da_idx_timeout : 1, //[27]
reserved_0a : 4; //[31:28]
uint32_t reserved_1a : 32; //[31:0]
};
/*
first_msdu_in_mpdu_flag
<enum 0 Not_first_msdu> This is not the first MSDU in
the MPDU.
<enum 1 first_msdu> This MSDU is the first one in the
MPDU. <legal all>
last_msdu_in_mpdu_flag
Consumer: WBM/REO/SW/FW
Producer: RXDMA
<enum 0 Not_last_msdu> There are more MSDUs linked to
this MSDU that belongs to this MPDU
<enum 1 Last_msdu> this MSDU is the last one in the
MPDU. This setting is only allowed in combination with
'Msdu_continuation' set to 0. This implies that when an msdu
is spread out over multiple buffers and thus
msdu_continuation is set, only for the very last buffer of
the msdu, can the 'last_msdu_in_mpdu_flag' be set.
When both first_msdu_in_mpdu_flag and
last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
belongs to only contains a single MSDU.
<legal all>
msdu_continuation
When set, this MSDU buffer was not able to hold the
entire MSDU. The next buffer will therefor contain
additional information related to this MSDU.
<legal all>
msdu_length
Field is only valid in combination with the
'first_msdu_in_mpdu_flag ' being set. When the
'first_msdu_in_mpdu_flag ' is not set, this field shall be
0.
Full MSDU length in bytes after decapsulation.
This field is still valid for MPDU frames without
A-MSDU. It still represents MSDU length after decapsulation
Or in case of RAW MPDUs, it indicates the length of the
entire MPDU (without FCS field)
<legal all>
reo_destination_indication
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
msdu_drop
When set, REO shall drop this MSDU and not forward it to
any other ring...
<legal all>
sa_is_valid
Indicates that OLE found a valid SA entry for this MSDU
<legal all>
sa_idx_timeout
Indicates an unsuccessful MAC source address search due
to the expiring of the search timer for this MSDU
<legal all>
da_is_valid
Indicates that OLE found a valid DA entry for this MSDU
<legal all>
da_is_mcbc
Field Only valid if da_is_valid is set
Indicates the DA address was a Multicast of Broadcast
address for this MSDU
<legal all>
da_idx_timeout
Indicates an unsuccessful MAC destination address search
due to the expiring of the search timer for this MSDU
<legal all>
reserved_0a
<legal 0>
reserved_1a
<legal 0>
*/
/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG
<enum 0 Not_first_msdu> This is not the first MSDU in
the MPDU.
<enum 1 first_msdu> This MSDU is the first one in the
MPDU. <legal all>
*/
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG
Consumer: WBM/REO/SW/FW
Producer: RXDMA
<enum 0 Not_last_msdu> There are more MSDUs linked to
this MSDU that belongs to this MPDU
<enum 1 Last_msdu> this MSDU is the last one in the
MPDU. This setting is only allowed in combination with
'Msdu_continuation' set to 0. This implies that when an msdu
is spread out over multiple buffers and thus
msdu_continuation is set, only for the very last buffer of
the msdu, can the 'last_msdu_in_mpdu_flag' be set.
When both first_msdu_in_mpdu_flag and
last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
belongs to only contains a single MSDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1
#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION
When set, this MSDU buffer was not able to hold the
entire MSDU. The next buffer will therefor contain
additional information related to this MSDU.
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2
#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004
/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH
Field is only valid in combination with the
'first_msdu_in_mpdu_flag ' being set. When the
'first_msdu_in_mpdu_flag ' is not set, this field shall be
0.
Full MSDU length in bytes after decapsulation.
This field is still valid for MPDU frames without
A-MSDU. It still represents MSDU length after decapsulation
Or in case of RAW MPDUs, it indicates the length of the
entire MPDU (without FCS field)
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3
#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8
/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17
#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000
/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP
When set, REO shall drop this MSDU and not forward it to
any other ring...
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22
#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000
/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID
Indicates that OLE found a valid SA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23
#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000
/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT
Indicates an unsuccessful MAC source address search due
to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24
#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000
/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID
Indicates that OLE found a valid DA entry for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25
#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000
/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC
Field Only valid if da_is_valid is set
Indicates the DA address was a Multicast of Broadcast
address for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26
#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000
/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT
Indicates an unsuccessful MAC destination address search
due to the expiring of the search timer for this MSDU
<legal all>
*/
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27
#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000
/* Description RX_MSDU_DESC_INFO_0_RESERVED_0A
<legal 0>
*/
#define RX_MSDU_DESC_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define RX_MSDU_DESC_INFO_0_RESERVED_0A_LSB 28
#define RX_MSDU_DESC_INFO_0_RESERVED_0A_MASK 0xf0000000
/* Description RX_MSDU_DESC_INFO_1_RESERVED_1A
<legal 0>
*/
#define RX_MSDU_DESC_INFO_1_RESERVED_1A_OFFSET 0x00000004
#define RX_MSDU_DESC_INFO_1_RESERVED_1A_LSB 0
#define RX_MSDU_DESC_INFO_1_RESERVED_1A_MASK 0xffffffff
#endif // _RX_MSDU_DESC_INFO_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MSDU_DETAILS_H_
#define _RX_MSDU_DETAILS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_msdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buffer_addr_info_details;
// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
struct rx_msdu_details {
struct buffer_addr_info buffer_addr_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
};
/*
struct buffer_addr_info buffer_addr_info_details
Consumer: REO/SW
Producer: RXDMA
Details of the physical address of the buffer containing
an MSDU (or entire MPDU)
struct rx_msdu_desc_info rx_msdu_desc_info_details
Consumer: REO/SW
Producer: RXDMA
General information related to the MSDU that should be
passed on from RXDMA all the way to to the REO destination
ring.
*/
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000000
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0
#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000004
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0
#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000008
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0
#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0
#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
#endif // _RX_MSDU_DETAILS_H_

1238
hw/qca6290/v1/rx_msdu_end.h Normal file
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345
hw/qca6290/v1/rx_msdu_link.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_MSDU_LINK_H_
#define _RX_MSDU_LINK_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_descriptor_header.h"
#include "buffer_addr_info.h"
#include "rx_msdu_details.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_descriptor_header descriptor_header;
// 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info;
// 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17]
// 4 pn_31_0[31:0]
// 5 pn_63_32[31:0]
// 6 pn_95_64[31:0]
// 7 pn_127_96[31:0]
// 8-11 struct rx_msdu_details msdu_0;
// 12-15 struct rx_msdu_details msdu_1;
// 16-19 struct rx_msdu_details msdu_2;
// 20-23 struct rx_msdu_details msdu_3;
// 24-27 struct rx_msdu_details msdu_4;
// 28-31 struct rx_msdu_details msdu_5;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_MSDU_LINK 32
struct rx_msdu_link {
struct uniform_descriptor_header descriptor_header;
struct buffer_addr_info next_msdu_link_desc_addr_info;
uint32_t receive_queue_number : 16, //[15:0]
first_rx_msdu_link_struct : 1, //[16]
reserved_3a : 15; //[31:17]
uint32_t pn_31_0 : 32; //[31:0]
uint32_t pn_63_32 : 32; //[31:0]
uint32_t pn_95_64 : 32; //[31:0]
uint32_t pn_127_96 : 32; //[31:0]
struct rx_msdu_details msdu_0;
struct rx_msdu_details msdu_1;
struct rx_msdu_details msdu_2;
struct rx_msdu_details msdu_3;
struct rx_msdu_details msdu_4;
struct rx_msdu_details msdu_5;
};
/*
struct uniform_descriptor_header descriptor_header
Details about which module owns this struct.
Note that sub field Buffer_type shall be set to
Receive_MSDU_Link_descriptor
struct buffer_addr_info next_msdu_link_desc_addr_info
Details of the physical address of the next MSDU link
descriptor that contains info about additional MSDUs that
are part of this MPDU.
receive_queue_number
Indicates the Receive queue to which this MPDU
descriptor belongs
Used for tracking, finding bugs and debugging.
<legal all>
first_rx_msdu_link_struct
When set, this RX_MSDU_link descriptor is the first one
in the MSDU link list. Field MSDU_0 points to the very first
MSDU buffer descriptor in the MPDU
<legal all>
reserved_3a
<legal 0>
pn_31_0
31-0 bits of the 256-bit packet number bitmap.
<legal all>
pn_63_32
63-32 bits of the 256-bit packet number bitmap.
<legal all>
pn_95_64
95-64 bits of the 256-bit packet number bitmap.
<legal all>
pn_127_96
127-96 bits of the 256-bit packet number bitmap.
<legal all>
struct rx_msdu_details msdu_0
When First_RX_MSDU_link_struct is set, this MSDU is the
first in the MPDU
When First_RX_MSDU_link_struct is NOT set, this MSDU
follows the last MSDU in the previous RX_MSDU_link data
structure
struct rx_msdu_details msdu_1
Details of next MSDU in this (MSDU flow) linked list
struct rx_msdu_details msdu_2
Details of next MSDU in this (MSDU flow) linked list
struct rx_msdu_details msdu_3
Details of next MSDU in this (MSDU flow) linked list
struct rx_msdu_details msdu_4
Details of next MSDU in this (MSDU flow) linked list
struct rx_msdu_details msdu_5
Details of next MSDU in this (MSDU flow) linked list
*/
#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000008
#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0
#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
/* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER
Indicates the Receive queue to which this MPDU
descriptor belongs
Used for tracking, finding bugs and debugging.
<legal all>
*/
#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0
#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
/* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT
When set, this RX_MSDU_link descriptor is the first one
in the MSDU link list. Field MSDU_0 points to the very first
MSDU buffer descriptor in the MPDU
<legal all>
*/
#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c
#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16
#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000
/* Description RX_MSDU_LINK_3_RESERVED_3A
<legal 0>
*/
#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c
#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17
#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000
/* Description RX_MSDU_LINK_4_PN_31_0
31-0 bits of the 256-bit packet number bitmap.
<legal all>
*/
#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010
#define RX_MSDU_LINK_4_PN_31_0_LSB 0
#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff
/* Description RX_MSDU_LINK_5_PN_63_32
63-32 bits of the 256-bit packet number bitmap.
<legal all>
*/
#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014
#define RX_MSDU_LINK_5_PN_63_32_LSB 0
#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff
/* Description RX_MSDU_LINK_6_PN_95_64
95-64 bits of the 256-bit packet number bitmap.
<legal all>
*/
#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018
#define RX_MSDU_LINK_6_PN_95_64_LSB 0
#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff
/* Description RX_MSDU_LINK_7_PN_127_96
127-96 bits of the 256-bit packet number bitmap.
<legal all>
*/
#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c
#define RX_MSDU_LINK_7_PN_127_96_LSB 0
#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff
#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000020
#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_LSB 0
#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff
#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000024
#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_LSB 0
#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff
#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x00000028
#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_LSB 0
#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff
#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_OFFSET 0x0000002c
#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_LSB 0
#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_MASK 0xffffffff
#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000030
#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_LSB 0
#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff
#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000034
#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_LSB 0
#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff
#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x00000038
#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_LSB 0
#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff
#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_OFFSET 0x0000003c
#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_LSB 0
#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_MASK 0xffffffff
#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000040
#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_LSB 0
#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff
#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000044
#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_LSB 0
#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff
#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x00000048
#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_LSB 0
#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff
#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_OFFSET 0x0000004c
#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_LSB 0
#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_MASK 0xffffffff
#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000050
#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_LSB 0
#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff
#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000054
#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_LSB 0
#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff
#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x00000058
#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_LSB 0
#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff
#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_OFFSET 0x0000005c
#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_LSB 0
#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_MASK 0xffffffff
#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000060
#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_LSB 0
#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff
#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000064
#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_LSB 0
#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff
#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x00000068
#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_LSB 0
#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff
#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_OFFSET 0x0000006c
#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_LSB 0
#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_MASK 0xffffffff
#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000070
#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_LSB 0
#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff
#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000074
#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_LSB 0
#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff
#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x00000078
#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_LSB 0
#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff
#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_OFFSET 0x0000007c
#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_LSB 0
#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_MASK 0xffffffff
#endif // _RX_MSDU_LINK_H_

1081
hw/qca6290/v1/rx_msdu_start.h Normal file
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File diff suppressed because it is too large Load diff

1662
hw/qca6290/v1/rx_reo_queue.h Normal file
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File diff suppressed because it is too large Load diff

360
hw/qca6290/v1/rx_reo_queue_ext.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_REO_QUEUE_EXT_H_
#define _RX_REO_QUEUE_EXT_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_descriptor_header.h"
#include "rx_mpdu_link_ptr.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_descriptor_header descriptor_header;
// 1 reserved_1a[31:0]
// 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0;
// 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1;
// 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2;
// 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3;
// 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4;
// 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5;
// 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6;
// 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7;
// 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8;
// 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9;
// 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10;
// 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11;
// 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12;
// 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13;
// 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
struct rx_reo_queue_ext {
struct uniform_descriptor_header descriptor_header;
uint32_t reserved_1a : 32; //[31:0]
struct rx_mpdu_link_ptr mpdu_link_pointer_0;
struct rx_mpdu_link_ptr mpdu_link_pointer_1;
struct rx_mpdu_link_ptr mpdu_link_pointer_2;
struct rx_mpdu_link_ptr mpdu_link_pointer_3;
struct rx_mpdu_link_ptr mpdu_link_pointer_4;
struct rx_mpdu_link_ptr mpdu_link_pointer_5;
struct rx_mpdu_link_ptr mpdu_link_pointer_6;
struct rx_mpdu_link_ptr mpdu_link_pointer_7;
struct rx_mpdu_link_ptr mpdu_link_pointer_8;
struct rx_mpdu_link_ptr mpdu_link_pointer_9;
struct rx_mpdu_link_ptr mpdu_link_pointer_10;
struct rx_mpdu_link_ptr mpdu_link_pointer_11;
struct rx_mpdu_link_ptr mpdu_link_pointer_12;
struct rx_mpdu_link_ptr mpdu_link_pointer_13;
struct rx_mpdu_link_ptr mpdu_link_pointer_14;
};
/*
struct uniform_descriptor_header descriptor_header
Details about which module owns this struct.
Note that sub field Buffer_type shall be set to
Receive_REO_queue_ext_descriptor
reserved_1a
<legal 0>
struct rx_mpdu_link_ptr mpdu_link_pointer_0
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_1
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_2
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_3
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_4
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_5
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_6
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_7
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_8
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_9
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_10
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_11
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_12
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_13
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
struct rx_mpdu_link_ptr mpdu_link_pointer_14
Consumer: REO
Producer: REO
Pointer to the next MPDU_link descriptor in the MPDU
queue
*/
#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
/* Description RX_REO_QUEUE_EXT_1_RESERVED_1A
<legal 0>
*/
#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004
#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0
#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x00000008
#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0
#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB 0
#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000010
#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0
#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB 0
#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x00000018
#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0
#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB 0
#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000020
#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0
#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB 0
#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x00000028
#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0
#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0
#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000030
#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0
#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0
#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x00000038
#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0
#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0
#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000040
#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0
#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0
#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x00000048
#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0
#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0
#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000050
#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0
#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0
#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x00000058
#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0
#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0
#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000060
#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0
#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0
#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x00000068
#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0
#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0
#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000070
#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0
#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0
#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x00000078
#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0
#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0
#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff
#endif // _RX_REO_QUEUE_EXT_H_

245
hw/qca6290/v1/rxpt_classify_info.h Normal file
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@ -0,0 +1,245 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RXPT_CLASSIFY_INFO_H_
#define _RXPT_CLASSIFY_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_destination_indication[4:0], use_flow_id_toeplitz_clfy[5], reserved_0a[31:6]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
struct rxpt_classify_info {
uint32_t reo_destination_indication : 5, //[4:0]
use_flow_id_toeplitz_clfy : 1, //[5]
reserved_0a : 26; //[31:6]
};
/*
reo_destination_indication
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
use_flow_id_toeplitz_clfy
indication to Rx OLE to enable classification based on
'flow_id_toeplitz' from Common Parser, in case flow search
fails
<legal all>
reserved_0a
<legal 0>
*/
/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0
#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f
/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY
indication to Rx OLE to enable classification based on
'flow_id_toeplitz' from Common Parser, in case flow search
fails
<legal all>
*/
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 5
#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000020
/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0A
<legal 0>
*/
#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_LSB 6
#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_MASK 0xffffffc0
#endif // _RXPT_CLASSIFY_INFO_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*********************************************************************************
*
* DESCRIPTION
* - This is an extension of standard msmhwio.h to support relative addressing
* scheme used in SCALe auto-generated sequences.
* - The objective of this new addressing scheme is enable the same C function
* definition to be applicable to multiple baseances of the same block.
* - Such code reuse is not feasible with the standard HWIO macros that use a
* absolute addressing scheme.
* - Compared to the standard HWIO macros, the new macros defined here take an
* additional parameter 'baseance offset'. So are the C functions generated
* by SCALe Autoseq from .seq inputs.
* - As such, macros defined in this file must be used with 'seq_msmhwiobase.h',
* 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq.
* - Macros defined in this file leverage the lower-level macros from the
* standard 'msmhwio.h', and the two sets of macros are compatible.
*
********************************************************************************/
#ifndef __SEQ_H__
#define __SEQ_H__
#include "HALhwio.h"
/**** Register Ref Read ****/
#define SEQ_INH(base, regtype, reg) \
SEQ_##regtype##_INH(base, reg)
/**** Masked Register Read ****/
#define SEQ_INMH(base, regtype, reg, mask) \
SEQ_##regtype##_INMH(base, reg, mask)
/**** Ref Reg Field Read ****/
#define SEQ_INFH(base, regtype, reg, fld) \
(SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
/**** Ref Register Write ****/
#define SEQ_OUTH(base, regtype, reg, val) \
SEQ_##regtype##_OUTH(base, reg, val)
/**** Ref Register Masked Write ****/
#define SEQ_OUTMH(base, regtype, reg, mask, val) \
SEQ_##regtype##_OUTMH(base, reg, mask, val)
/**** Ref Register Field Write ****/
#define SEQ_OUTFH(base, regtype, reg, fld, val) \
SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
/**** seq_msg() ****
typedef enum {
DEBUG,
INFO,
WARNING,
ERROR,
FATAL
} SeverityLevel ;
void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... );
*/
/************ seq_wait() ************/
typedef enum {
SEC,
MS,
US,
NS
} SEQ_TimeUnit;
extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
/************ seq_poll() ************/
extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
#endif /* __SEQ_H__ */

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _SW_XML_HEADERS_H_
#define _SW_XML_HEADERS_H_
#include "ack_report.h"
#include "addr_search_entry.h"
#include "buffer_addr_info.h"
#include "cce_rule.h"
#include "ce_src_desc.h"
#include "he_sig_a_mu_dl_info.h"
#include "he_sig_a_mu_ul_info.h"
#include "he_sig_a_su_info.h"
#include "he_sig_b1_mu_info.h"
#include "he_sig_b2_mu_info.h"
#include "he_sig_b2_ofdma_info.h"
#include "ht_sig_info.h"
#include "l_sig_a_info.h"
#include "l_sig_b_info.h"
#include "mactx_abort_request_info.h"
#include "mimo_control_info.h"
#include "no_ack_report.h"
#include "pcu_ppdu_setup_end_info.h"
#include "pdg_response_rate_setting.h"
#include "peer_table_entry.h"
#include "phyrx_abort_request_info.h"
#include "ppdu_rate_setting.h"
#include "prot_rate_setting.h"
#include "receive_rssi_info.h"
#include "receive_user_info.h"
#include "received_trigger_info_details.h"
#include "reo_destination_ring.h"
#include "reo_entrance_ring.h"
#include "reo_to_ppe_ring.h"
#include "response_rate_setting.h"
#include "rx_flow_search_entry.h"
#include "rx_location_info.h"
#include "rx_mpdu_desc_info.h"
#include "rx_mpdu_details.h"
#include "rx_mpdu_info.h"
#include "rx_mpdu_link.h"
#include "rx_mpdu_link_ptr.h"
#include "rx_msdu_desc_info.h"
#include "rx_msdu_details.h"
#include "rx_msdu_link.h"
#include "rx_peer_entry_details.h"
#include "rx_reo_queue.h"
#include "rx_reo_queue_ext.h"
#include "rx_reo_queue_reference.h"
#include "rx_rxpcu_classification_overview.h"
#include "rx_timing_offset_info.h"
#include "rxole_cce_classify_info.h"
#include "rxole_cce_info.h"
#include "rxole_cce_superrule.h"
#include "rxpt_classify_info.h"
#include "scheduler_cmd.h"
#include "service_info.h"
#include "sw_peer_info.h"
#include "tcl_cce_classify_info.h"
#include "tcl_cce_info.h"
#include "tcl_cce_superrule.h"
#include "tcl_compact_exit_ring.h"
#include "tcl_entrance_from_ppe_ring.h"
#include "tcl_exit_base.h"
#include "tcl_extended_exit_ring.h"
#include "tcl_regular_exit_ring.h"
#include "tcl_status_ring.h"
#include "tqm_entrance_ring.h"
#include "tx_flow_search_entry.h"
#include "tx_mpdu_details.h"
#include "tx_mpdu_link.h"
#include "tx_mpdu_link_ptr.h"
#include "tx_mpdu_queue_ext.h"
#include "tx_mpdu_queue_ext_ptr.h"
#include "tx_mpdu_queue_head.h"
#include "tx_msdu_details.h"
#include "tx_msdu_extension.h"
#include "tx_msdu_flow.h"
#include "tx_msdu_link.h"
#include "tx_msdu_link_entry_ptr.h"
#include "tx_rate_stats_info.h"
#include "txpcu_buffer_basics.h"
#include "txpt_classify_info.h"
#include "uniform_descriptor_header.h"
#include "uniform_reo_cmd_header.h"
#include "uniform_reo_status_header.h"
#include "uniform_tqm_cmd_header.h"
#include "uniform_tqm_status_header.h"
#include "uplink_common_info.h"
#include "uplink_user_setup_info.h"
#include "user_rate_setting.h"
#include "vht_sig_a_info.h"
#include "vht_sig_b_mu160_info.h"
#include "vht_sig_b_mu20_info.h"
#include "vht_sig_b_mu40_info.h"
#include "vht_sig_b_mu80_info.h"
#include "vht_sig_b_su160_info.h"
#include "vht_sig_b_su20_info.h"
#include "vht_sig_b_su40_info.h"
#include "vht_sig_b_su80_info.h"
#include "wbm_buffer_ring.h"
#include "wbm_link_descriptor_ring.h"
#include "wbm_release_ring.h"
#include "who_classify_info.h"
#include "macrx_abort_request_info.h"
#include "phytx_abort_request_info.h"
#include "ce_stat_desc.h"
#include "coex_mac_nap.h"
#include "coex_rx_status.h"
#include "coex_status_broadcast.h"
#include "coex_tx_req.h"
#include "coex_tx_resp.h"
#include "coex_tx_status.h"
#include "coex_tx_stop_ctrl.h"
#include "crypto_status.h"
#include "expected_response.h"
#include "mactx_abort_request.h"
#include "mactx_bf_params_common.h"
#include "mactx_coex_phy_ctrl.h"
#include "mactx_delete_cv.h"
#include "mactx_he_sig_a_mu_dl.h"
#include "mactx_he_sig_a_mu_ul.h"
#include "mactx_he_sig_a_su.h"
#include "mactx_he_sig_b1_mu.h"
#include "mactx_he_sig_b2_mu.h"
#include "mactx_he_sig_b2_ofdma.h"
#include "mactx_ht_sig.h"
#include "mactx_l_sig_a.h"
#include "mactx_l_sig_b.h"
#include "mactx_mu_uplink_common.h"
#include "mactx_phy_desc.h"
#include "mactx_phy_nap.h"
#include "mactx_pre_phy_desc.h"
#include "mactx_prefetch_cv.h"
#include "mactx_user_desc_common.h"
#include "mactx_vht_sig_a.h"
#include "mactx_vht_sig_b_su160.h"
#include "mactx_vht_sig_b_su20.h"
#include "mactx_vht_sig_b_su40.h"
#include "mactx_vht_sig_b_su80.h"
#include "ofdma_trigger_details.h"
#include "ole_buf_status.h"
#include "pcu_ppdu_setup_end.h"
#include "pcu_ppdu_setup_init.h"
#include "pcu_ppdu_setup_start.h"
#include "pdg_fes_setup.h"
#include "pdg_response.h"
#include "pdg_sw_mode_bw_start.h"
#include "pdg_tx_req.h"
#include "pdg_wait_for_mac_request.h"
#include "pdg_wait_for_phy_request.h"
#include "phyrx_cbf_read_request_ack.h"
#include "phyrx_generated_cbf_details.h"
#include "phyrx_he_sig_a_mu_dl.h"
#include "phyrx_he_sig_a_mu_ul.h"
#include "phyrx_he_sig_a_su.h"
#include "phyrx_he_sig_b1_mu.h"
#include "phyrx_he_sig_b2_mu.h"
#include "phyrx_he_sig_b2_ofdma.h"
#include "phyrx_ht_sig.h"
#include "phyrx_l_sig_a.h"
#include "phyrx_l_sig_b.h"
#include "phyrx_pkt_end.h"
#include "phyrx_rssi_ht.h"
#include "phyrx_rssi_legacy.h"
#include "phyrx_vht_sig_a.h"
#include "phyrx_vht_sig_b_su160.h"
#include "phyrx_vht_sig_b_su20.h"
#include "phyrx_vht_sig_b_su40.h"
#include "phyrx_vht_sig_b_su80.h"
#include "received_response_info.h"
#include "received_trigger_info.h"
#include "reo_descriptor_threshold_reached_status.h"
#include "reo_flush_cache.h"
#include "reo_flush_cache_status.h"
#include "reo_flush_queue.h"
#include "reo_flush_queue_status.h"
#include "reo_flush_timeout_list.h"
#include "reo_flush_timeout_list_status.h"
#include "reo_get_queue_stats.h"
#include "reo_get_queue_stats_status.h"
#include "reo_unblock_cache.h"
#include "reo_unblock_cache_status.h"
#include "reo_update_rx_reo_queue.h"
#include "reo_update_rx_reo_queue_status.h"
#include "response_end_status.h"
#include "response_start_status.h"
#include "rx_frame_bitmap_req.h"
#include "rx_frameless_bar_details.h"
#include "rx_pm_info.h"
#include "rx_ppdu_ack_report.h"
#include "rx_ppdu_end_status_done.h"
#include "rx_ppdu_no_ack_report.h"
#include "rx_ppdu_start.h"
#include "rx_preamble.h"
#include "rx_response_required_info.h"
#include "rx_ring_mask.h"
#include "rx_start_param.h"
#include "rx_trig_info.h"
#include "rxpcu_ppdu_end_info.h"
#include "rxpcu_setup.h"
#include "sch_coex_status.h"
#include "sch_wait_instr.h"
#include "scheduler_command_status.h"
#include "scheduler_rx_ppdu_no_response_status.h"
#include "scheduler_rx_sifs_response_trigger_status.h"
#include "scheduler_selfgen_response_status.h"
#include "tcl_data_cmd.h"
#include "tcl_gse_cmd.h"
#include "tqm_acked_mpdu_status.h"
#include "tqm_add_msdu_status.h"
#include "tqm_descriptor_threshold_reached_status.h"
#include "tqm_flow_empty_status.h"
#include "tqm_flow_not_empty_status.h"
#include "tqm_flush_cache.h"
#include "tqm_flush_cache_status.h"
#include "tqm_gen_mpdu_length_list.h"
#include "tqm_gen_mpdu_length_list_status.h"
#include "tqm_gen_mpdus.h"
#include "tqm_gen_mpdus_status.h"
#include "tqm_get_mpdu_head_info.h"
#include "tqm_get_mpdu_head_info_status.h"
#include "tqm_get_mpdu_queue_stats.h"
#include "tqm_get_mpdu_queue_stats_status.h"
#include "tqm_get_msdu_flow_stats.h"
#include "tqm_get_msdu_flow_stats_status.h"
#include "tqm_remove_mpdu.h"
#include "tqm_remove_mpdu_status.h"
#include "tqm_remove_msdu.h"
#include "tqm_remove_msdu_status.h"
#include "tqm_sync_cmd.h"
#include "tqm_sync_cmd_status.h"
#include "tqm_threshold_drop_notification_status.h"
#include "tqm_unblock_cache.h"
#include "tqm_unblock_cache_status.h"
#include "tqm_update_tx_mpdu_count_status.h"
#include "tqm_update_tx_mpdu_queue_head.h"
#include "tqm_update_tx_mpdu_queue_head_status.h"
#include "tqm_update_tx_msdu_flow.h"
#include "tqm_update_tx_msdu_flow_status.h"
#include "tqm_write_cmd.h"
#include "tqm_write_cmd_status.h"
#include "tx_cbf_info.h"
#include "tx_data_sync.h"
#include "tx_fes_setup.h"
#include "tx_fes_status_end.h"
#include "tx_fes_status_prot.h"
#include "tx_fes_status_start.h"
#include "tx_fes_status_start_ppdu.h"
#include "tx_fes_status_start_prot.h"
#include "tx_flush_req.h"
#include "tx_sw_mode_setup.h"
#include "txpcu_buffer_status.h"
#include "who_terminate.h"
#include "data_to_time_config.h"
#include "mactx_bf_params_per_user.h"
#include "mactx_expect_cbf_common.h"
#include "mactx_expect_cbf_per_user.h"
#include "mactx_mu_uplink_user_setup.h"
#include "mactx_service.h"
#include "mactx_user_desc_per_user.h"
#include "mactx_vht_sig_b_mu160.h"
#include "mactx_vht_sig_b_mu20.h"
#include "mactx_vht_sig_b_mu40.h"
#include "mactx_vht_sig_b_mu80.h"
#include "mpdu_info.h"
#include "mpdu_info_bitmap.h"
#include "mpdu_limit.h"
#include "pcu_ppdu_setup_user.h"
#include "pdg_user_setup.h"
#include "phyrx_common_user_info.h"
#include "phyrx_user_info.h"
#include "phyrx_vht_sig_b_mu160.h"
#include "phyrx_vht_sig_b_mu20.h"
#include "phyrx_vht_sig_b_mu40.h"
#include "phyrx_vht_sig_b_mu80.h"
#include "rx_attention.h"
#include "rx_frame_bitmap_ack.h"
#include "rx_header.h"
#include "rx_mpdu_end.h"
#include "rx_mpdu_pcu_start.h"
#include "rx_mpdu_start.h"
#include "rx_msdu_end.h"
#include "rx_msdu_start.h"
#include "rx_peer_entry.h"
#include "rx_ppdu_end_user_stats.h"
#include "rx_ppdu_end_user_stats_ext.h"
#include "rx_ppdu_start_user_info.h"
#include "rxpcu_user_setup.h"
#include "rxpcu_user_setup_ext.h"
#include "tqm_acked_mpdu.h"
#include "tqm_update_tx_mpdu_count.h"
#include "tx_11ah_setup.h"
#include "tx_cv_start.h"
#include "tx_fes_status_ack_or_ba.h"
#include "tx_fes_status_user_ppdu.h"
#include "tx_fes_status_user_response.h"
#include "tx_mpdu_start.h"
#include "tx_msdu_start.h"
#include "tx_peer_entry.h"
#include "tx_queue_extension.h"
#include "tx_raw_or_native_frame_setup.h"
#include "txpcu_user_buffer_status.h"
#include "txpcu_user_setup.h"
#include "who_anchor_value.h"
#include "who_cce_info.h"
#include "who_commit_done.h"
#include "who_l2_llc.h"
#include "who_l3_checksum.h"
#include "who_l3_info.h"
#include "who_l4_checksum.h"
#include "who_l4_info.h"
#include "who_mesh_control.h"
#include "who_msdu_misc.h"
#include "who_packet_hdr.h"
#include "who_tso.h"
#include "who_wmac_header_pv0.h"
#include "who_wmac_header_pv1.h"
#include "who_wmac_iv.h"
#include "tlv_tag_def.h"
#include "mactx_cbf_data.h"
#include "mactx_cbf_done.h"
#include "mactx_cbf_start.h"
#include "mactx_data_resp.h"
#include "phyrx_abort_request.h"
#include "phyrx_cbf_data_resp.h"
#include "phyrx_data.h"
#include "phyrx_user_abort_notification.h"
#include "macrx_abort_request.h"
#include "macrx_cbf_data_request.h"
#include "macrx_cbf_read_request.h"
#include "macrx_chain_mask.h"
#include "macrx_expect_ndp_reception.h"
#include "macrx_freeze_capture_channel.h"
#include "macrx_req_implicit_fb.h"
#include "phytx_abort_request.h"
#include "phytx_bf_cv_loading_done.h"
#include "phytx_nap_ack.h"
#include "phytx_pkt_end.h"
#include "phytx_ppdu_header_info_request.h"
#include "phytx_request_ctrl_info.h"
#endif

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TCL_DATA_CMD_H_
#define _TCL_DATA_CMD_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buf_addr_info;
// 2 buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], reserved[13:10], addrx_en[14], addry_en[15], tcl_cmd_number[31:16]
// 3 data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], dscp_to_tid_priority_table_id[22], packet_offset[31:23]
// 4 buffer_timestamp[18:0], buffer_timestamp_valid[19], mesh_enable[20], hlos_tid_overwrite[21], hlos_tid[25:22], reserved_4[31:26]
// 5 reserved_5[31:0]
// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TCL_DATA_CMD 7
struct tcl_data_cmd {
struct buffer_addr_info buf_addr_info;
uint32_t buf_or_ext_desc_type : 1, //[0]
epd : 1, //[1]
encap_type : 2, //[3:2]
encrypt_type : 4, //[7:4]
src_buffer_swap : 1, //[8]
link_meta_swap : 1, //[9]
reserved : 4, //[13:10]
addrx_en : 1, //[14]
addry_en : 1, //[15]
tcl_cmd_number : 16; //[31:16]
uint32_t data_length : 16, //[15:0]
ipv4_checksum_en : 1, //[16]
udp_over_ipv4_checksum_en : 1, //[17]
udp_over_ipv6_checksum_en : 1, //[18]
tcp_over_ipv4_checksum_en : 1, //[19]
tcp_over_ipv6_checksum_en : 1, //[20]
to_fw : 1, //[21]
dscp_to_tid_priority_table_id : 1, //[22]
packet_offset : 9; //[31:23]
uint32_t buffer_timestamp : 19, //[18:0]
buffer_timestamp_valid : 1, //[19]
mesh_enable : 1, //[20]
hlos_tid_overwrite : 1, //[21]
hlos_tid : 4, //[25:22]
reserved_4 : 6; //[31:26]
uint32_t reserved_5 : 32; //[31:0]
uint32_t reserved_6a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
struct buffer_addr_info buf_addr_info
Details of the physical address for a single buffer
It also contains return ownership info as well as some
meta data for SW related to this buffer.
In case of Buf_or_ext_desc_type indicating
'MSDU_buffer', this address indicates the start of the meta
data that is preceding the actual packet data.
The start of the actual packet data is provided by
field: Packet_offset
buf_or_ext_desc_type
<enum 0 MSDU_buffer> The address points to an MSDU
buffer.
<enum 1 extension_descriptor> The address points to an
MSDU link extension descriptor
< legal all>
epd
When this bit is set then input packet is an EPD type
<legal all>
encap_type
Indicates the encapsulation that HW will perform:
<enum 0 RAW> No encapsulation
<enum 1 Native_WiFi>
<enum 2 Ethernet> Ethernet 2 (DIX)
<enum 3 802_3> 802.3 (uses SNAP/LLC)
Used by the OLE during encapsulation.
<legal all>
encrypt_type
Field only valid for encap_type: RAW
Indicates type of decrypt cipher used (as defined in the
peer entry)
<enum 0 wep_40> WEP 40-bit
<enum 1 wep_104> WEP 104-bit
<enum 2 tkip_no_mic> TKIP without MIC
<enum 3 wep_128> WEP 128-bit
<enum 4 tkip_with_mic> TKIP with MIC
<enum 5 wapi> WAPI
<enum 6 aes_ccmp_128> AES CCMP 128
<enum 7 no_cipher> No crypto
<enum 8 aes_ccmp_256> AES CCMP 256
<enum 9 aes_gcmp_128> AES CCMP 128
<enum 10 aes_gcmp_256> AES CCMP 256
<enum 11 wapi_gcm_sm4> WAPI GCM SM4
<legal 0-11>
src_buffer_swap
Treats source memory (packet buffer) organization as
big-endian. The packets are read and byte swapped.
1'b0: Source memory is little endian
1'b1: Source memory is big endian
<legal all>
link_meta_swap
Treats link descriptor and Metadata as big-endian. The
link descriptor/Metadata is read and byte swapped.
1'b0: Memory is little endian
1'b1: Memory is big endian
<legal all>
reserved
<legal 0>
addrx_en
Address X search enable in ASE
1'b0: Search disable
1'b1: Search Enable
<legal all>
addry_en
Address Y search enable in ASE
1'b0: Search disable
1'b1: Search Enable
<legal all>
tcl_cmd_number
This number can be used by SW to track, identify and
link the created commands with the command statuses
Is set to the value 'TCL_CMD_Number' of the related
TCL_DATA command
<legal all>
data_length
Valid Data length in bytes.
MSDU length in case of direct descriptor.
Length of link extension descriptor in case of Link
extension descriptor. This is used to know the size of
Metadata.
<legal all>
ipv4_checksum_en
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable IPv4 checksum replacement
udp_over_ipv4_checksum_en
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable UDP over IPv4 checksum replacement. UDP checksum
over IPv4 is optional for TCP/IP stacks.
udp_over_ipv6_checksum_en
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable UDP over IPv6 checksum replacement. UDP checksum
over IPv6 is mandatory for TCP/IP stacks.
tcp_over_ipv4_checksum_en
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable TCP checksum over IPv4 replacement
tcp_over_ipv6_checksum_en
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable TCP checksum over IPv6 replacement
to_fw
Forward packet to FW along with classification result.
The packet will not be forward to TQM when this bit is set
1'b0: Use classification result to forward the packet.
1'b1: Override classification result and forward packet
only to FW.
dscp_to_tid_priority_table_id
The DSCP to tid conversion table to be used for this
frame
<legal all>
packet_offset
Packet offset from Metadata in case of direct buffer
descriptor. This field is valid when Buf_or_ext_desc_type is
reset(= 0).
<legal all>
buffer_timestamp
Field only valid when 'Buffer_timestamp_valid ' is set.
Frame system entrance timestamp. The timestamp is
related to the global system timer
Generally the first module (SW, TCL or TQM). that sees
this frame and this timestamp field is not valid, shall fill
in this field.
Timestamp in units of 1024 us
buffer_timestamp_valid
When set, the Buffer_timestamp field contains valid
info.
mesh_enable
If set to 1:
* For raw WiFi frames, this indicates transmission to a
mesh STA, enabling the interpretation of the 'Mesh Control
Present' bit (bit 8) of QoS Control (otherwise this bit is
ignored),
* For native WiFi frames, this indicates that a 'Mesh
Control' field is present between the header and the LLC.
hlos_tid_overwrite
When set, TCL shall ignore the IP DSCP and VLAN PCP
fields and use HLOS_TID as the final TID. Otherwise TCL
shall consider the DSCP and PCP fields as well as HLOS_TID
and choose a final TID based on the configured priority
<legal all>
hlos_tid
HLOS MSDU priority
Field is used when HLOS_TID_overwrite is set.
Field is also used when HLOS_TID_overwrite is not set
and DSCP/PCP is not available in the packet
<legal all>
reserved_4
<legal 0>
reserved_5
<legal 0>
reserved_6a
<legal 0>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000
#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28
#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff
#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004
#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 28
#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff
/* Description TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE
<enum 0 MSDU_buffer> The address points to an MSDU
buffer.
<enum 1 extension_descriptor> The address points to an
MSDU link extension descriptor
< legal all>
*/
#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0
#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001
/* Description TCL_DATA_CMD_2_EPD
When this bit is set then input packet is an EPD type
<legal all>
*/
#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008
#define TCL_DATA_CMD_2_EPD_LSB 1
#define TCL_DATA_CMD_2_EPD_MASK 0x00000002
/* Description TCL_DATA_CMD_2_ENCAP_TYPE
Indicates the encapsulation that HW will perform:
<enum 0 RAW> No encapsulation
<enum 1 Native_WiFi>
<enum 2 Ethernet> Ethernet 2 (DIX)
<enum 3 802_3> 802.3 (uses SNAP/LLC)
Used by the OLE during encapsulation.
<legal all>
*/
#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2
#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c
/* Description TCL_DATA_CMD_2_ENCRYPT_TYPE
Field only valid for encap_type: RAW
Indicates type of decrypt cipher used (as defined in the
peer entry)
<enum 0 wep_40> WEP 40-bit
<enum 1 wep_104> WEP 104-bit
<enum 2 tkip_no_mic> TKIP without MIC
<enum 3 wep_128> WEP 128-bit
<enum 4 tkip_with_mic> TKIP with MIC
<enum 5 wapi> WAPI
<enum 6 aes_ccmp_128> AES CCMP 128
<enum 7 no_cipher> No crypto
<enum 8 aes_ccmp_256> AES CCMP 256
<enum 9 aes_gcmp_128> AES CCMP 128
<enum 10 aes_gcmp_256> AES CCMP 256
<enum 11 wapi_gcm_sm4> WAPI GCM SM4
<legal 0-11>
*/
#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4
#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0
/* Description TCL_DATA_CMD_2_SRC_BUFFER_SWAP
Treats source memory (packet buffer) organization as
big-endian. The packets are read and byte swapped.
1'b0: Source memory is little endian
1'b1: Source memory is big endian
<legal all>
*/
#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008
#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8
#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100
/* Description TCL_DATA_CMD_2_LINK_META_SWAP
Treats link descriptor and Metadata as big-endian. The
link descriptor/Metadata is read and byte swapped.
1'b0: Memory is little endian
1'b1: Memory is big endian
<legal all>
*/
#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008
#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9
#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200
/* Description TCL_DATA_CMD_2_RESERVED
<legal 0>
*/
#define TCL_DATA_CMD_2_RESERVED_OFFSET 0x00000008
#define TCL_DATA_CMD_2_RESERVED_LSB 10
#define TCL_DATA_CMD_2_RESERVED_MASK 0x00003c00
/* Description TCL_DATA_CMD_2_ADDRX_EN
Address X search enable in ASE
1'b0: Search disable
1'b1: Search Enable
<legal all>
*/
#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008
#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14
#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000
/* Description TCL_DATA_CMD_2_ADDRY_EN
Address Y search enable in ASE
1'b0: Search disable
1'b1: Search Enable
<legal all>
*/
#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008
#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15
#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000
/* Description TCL_DATA_CMD_2_TCL_CMD_NUMBER
This number can be used by SW to track, identify and
link the created commands with the command statuses
Is set to the value 'TCL_CMD_Number' of the related
TCL_DATA command
<legal all>
*/
#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008
#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16
#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000
/* Description TCL_DATA_CMD_3_DATA_LENGTH
Valid Data length in bytes.
MSDU length in case of direct descriptor.
Length of link extension descriptor in case of Link
extension descriptor. This is used to know the size of
Metadata.
<legal all>
*/
#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0
#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff
/* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable IPv4 checksum replacement
*/
#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16
#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000
/* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable UDP over IPv4 checksum replacement. UDP checksum
over IPv4 is optional for TCP/IP stacks.
*/
#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
/* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable UDP over IPv6 checksum replacement. UDP checksum
over IPv6 is mandatory for TCP/IP stacks.
*/
#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
/* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable TCP checksum over IPv4 replacement
*/
#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
/* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN
Field only valid when msdu_buffer_type is set to
MSDU_buffer.
OLE related control
Enable TCP checksum over IPv6 replacement
*/
#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
/* Description TCL_DATA_CMD_3_TO_FW
Forward packet to FW along with classification result.
The packet will not be forward to TQM when this bit is set
1'b0: Use classification result to forward the packet.
1'b1: Override classification result and forward packet
only to FW.
*/
#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_TO_FW_LSB 21
#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000
/* Description TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID
The DSCP to tid conversion table to be used for this
frame
<legal all>
*/
#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_LSB 22
#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_MASK 0x00400000
/* Description TCL_DATA_CMD_3_PACKET_OFFSET
Packet offset from Metadata in case of direct buffer
descriptor. This field is valid when Buf_or_ext_desc_type is
reset(= 0).
<legal all>
*/
#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c
#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23
#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000
/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP
Field only valid when 'Buffer_timestamp_valid ' is set.
Frame system entrance timestamp. The timestamp is
related to the global system timer
Generally the first module (SW, TCL or TQM). that sees
this frame and this timestamp field is not valid, shall fill
in this field.
Timestamp in units of 1024 us
*/
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff
/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID
When set, the Buffer_timestamp field contains valid
info.
*/
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19
#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000
/* Description TCL_DATA_CMD_4_MESH_ENABLE
If set to 1:
* For raw WiFi frames, this indicates transmission to a
mesh STA, enabling the interpretation of the 'Mesh Control
Present' bit (bit 8) of QoS Control (otherwise this bit is
ignored),
* For native WiFi frames, this indicates that a 'Mesh
Control' field is present between the header and the LLC.
*/
#define TCL_DATA_CMD_4_MESH_ENABLE_OFFSET 0x00000010
#define TCL_DATA_CMD_4_MESH_ENABLE_LSB 20
#define TCL_DATA_CMD_4_MESH_ENABLE_MASK 0x00100000
/* Description TCL_DATA_CMD_4_HLOS_TID_OVERWRITE
When set, TCL shall ignore the IP DSCP and VLAN PCP
fields and use HLOS_TID as the final TID. Otherwise TCL
shall consider the DSCP and PCP fields as well as HLOS_TID
and choose a final TID based on the configured priority
<legal all>
*/
#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010
#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21
#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000
/* Description TCL_DATA_CMD_4_HLOS_TID
HLOS MSDU priority
Field is used when HLOS_TID_overwrite is set.
Field is also used when HLOS_TID_overwrite is not set
and DSCP/PCP is not available in the packet
<legal all>
*/
#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010
#define TCL_DATA_CMD_4_HLOS_TID_LSB 22
#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000
/* Description TCL_DATA_CMD_4_RESERVED_4
<legal 0>
*/
#define TCL_DATA_CMD_4_RESERVED_4_OFFSET 0x00000010
#define TCL_DATA_CMD_4_RESERVED_4_LSB 26
#define TCL_DATA_CMD_4_RESERVED_4_MASK 0xfc000000
/* Description TCL_DATA_CMD_5_RESERVED_5
<legal 0>
*/
#define TCL_DATA_CMD_5_RESERVED_5_OFFSET 0x00000014
#define TCL_DATA_CMD_5_RESERVED_5_LSB 0
#define TCL_DATA_CMD_5_RESERVED_5_MASK 0xffffffff
/* Description TCL_DATA_CMD_6_RESERVED_6A
<legal 0>
*/
#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018
#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0
#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff
/* Description TCL_DATA_CMD_6_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018
#define TCL_DATA_CMD_6_RING_ID_LSB 20
#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000
/* Description TCL_DATA_CMD_6_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28
#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000
#endif // _TCL_DATA_CMD_H_

408
hw/qca6290/v1/tcl_gse_cmd.h Normal file
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@ -0,0 +1,408 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TCL_GSE_CMD_H_
#define _TCL_GSE_CMD_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 control_buffer_addr_31_0[31:0]
// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15]
// 2 cmd_meta_data_31_0[31:0]
// 3 cmd_meta_data_63_32[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TCL_GSE_CMD 7
struct tcl_gse_cmd {
uint32_t control_buffer_addr_31_0 : 32; //[31:0]
uint32_t control_buffer_addr_39_32 : 8, //[7:0]
gse_ctrl : 4, //[11:8]
gse_sel : 1, //[12]
status_destination_ring_id : 1, //[13]
swap : 1, //[14]
reserved_1a : 17; //[31:15]
uint32_t cmd_meta_data_31_0 : 32; //[31:0]
uint32_t cmd_meta_data_63_32 : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
control_buffer_addr_31_0
Address (lower 32 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
control_buffer_addr_39_32
Address (upper 8 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
gse_ctrl
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
gse_sel
Bit to select the ASE or FSE to do the operation mention
by GSE_ctrl bit
0: FSE select
1: ASE select
status_destination_ring_id
The TCL status ring to which the GSE status needs to be
send.
<enum 0 tcl_status_0_ring>
<enum 1 tcl_status_1_ring>
<legal all>
swap
Bit to enable byte swapping of contents of buffer
<enum 0 Byte_swap_disable >
<enum 1 byte_swap_enable >
<legal all>
reserved_1a
<legal 0>
cmd_meta_data_31_0
Meta data to be returned in the status descriptor
<legal all>
cmd_meta_data_63_32
Meta data to be returned in the status descriptor
<legal all>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
ring_id
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0
Address (lower 32 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
*/
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0
#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32
Address (upper 8 bits) of a control buffer containing
additional info needed for this command execution.
<legal all>
*/
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0
#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description TCL_GSE_CMD_1_GSE_CTRL
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
*/
#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004
#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8
#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00
/* Description TCL_GSE_CMD_1_GSE_SEL
Bit to select the ASE or FSE to do the operation mention
by GSE_ctrl bit
0: FSE select
1: ASE select
*/
#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004
#define TCL_GSE_CMD_1_GSE_SEL_LSB 12
#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000
/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID
The TCL status ring to which the GSE status needs to be
send.
<enum 0 tcl_status_0_ring>
<enum 1 tcl_status_1_ring>
<legal all>
*/
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13
#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000
/* Description TCL_GSE_CMD_1_SWAP
Bit to enable byte swapping of contents of buffer
<enum 0 Byte_swap_disable >
<enum 1 byte_swap_enable >
<legal all>
*/
#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004
#define TCL_GSE_CMD_1_SWAP_LSB 14
#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000
/* Description TCL_GSE_CMD_1_RESERVED_1A
<legal 0>
*/
#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004
#define TCL_GSE_CMD_1_RESERVED_1A_LSB 15
#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000
/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0
Meta data to be returned in the status descriptor
<legal all>
*/
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0
#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff
/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32
Meta data to be returned in the status descriptor
<legal all>
*/
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0
#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff
/* Description TCL_GSE_CMD_4_RESERVED_4A
<legal 0>
*/
#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010
#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0
#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff
/* Description TCL_GSE_CMD_5_RESERVED_5A
<legal 0>
*/
#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014
#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0
#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff
/* Description TCL_GSE_CMD_6_RESERVED_6A
<legal 0>
*/
#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018
#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0
#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff
/* Description TCL_GSE_CMD_6_RING_ID
Helps with debugging when dumping ring contents.
<legal all>
*/
#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018
#define TCL_GSE_CMD_6_RING_ID_LSB 20
#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000
/* Description TCL_GSE_CMD_6_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28
#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000
#endif // _TCL_GSE_CMD_H_

414
hw/qca6290/v1/tcl_status_ring.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TCL_STATUS_RING_H_
#define _TCL_STATUS_RING_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], reserved_0a[7], msdu_cnt_n[31:8]
// 1 msdu_byte_cnt_n[31:0]
// 2 msdu_timestmp_n[31:0]
// 3 cmd_meta_data_31_0[31:0]
// 4 cmd_meta_data_63_32[31:0]
// 5 hash_indx_val[19:0], reserved_5a[31:20]
// 6 reserved_6a[31:0]
// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TCL_STATUS_RING 8
struct tcl_status_ring {
uint32_t gse_ctrl : 4, //[3:0]
ase_fse_sel : 1, //[4]
cache_op_res : 2, //[6:5]
reserved_0a : 1, //[7]
msdu_cnt_n : 24; //[31:8]
uint32_t msdu_byte_cnt_n : 32; //[31:0]
uint32_t msdu_timestmp_n : 32; //[31:0]
uint32_t cmd_meta_data_31_0 : 32; //[31:0]
uint32_t cmd_meta_data_63_32 : 32; //[31:0]
uint32_t hash_indx_val : 20, //[19:0]
reserved_5a : 12; //[31:20]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
gse_ctrl
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
ase_fse_sel
Search Engine for which operation is done.
1'b0: Address Search Engine Result
1'b1: Flow Search Engine result
cache_op_res
Cache operation result. Following are results of cache
operation.
<enum 0 op_done> Operation successful
<enum 1 not_fnd> Entry not found in Table
<enum 2 timeout_er> Timeout Error
<legal 0-2>
reserved_0a
<legal 0>
msdu_cnt_n
MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
4'b1000
msdu_byte_cnt_n
MSDU byte count for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
msdu_timestmp_n
MSDU timestamp for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
cmd_meta_data_31_0
Meta data from input ring
<legal all>
cmd_meta_data_63_32
Meta data from input ring
<legal all>
hash_indx_val
Hash value of the entry in table in case of search
failed or search disable.
<legal all>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
ring_id
The buffer pointer ring ID.
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description TCL_STATUS_RING_0_GSE_CTRL
GSE control operations. This includes cache operations
and table entry statistics read/clear operation.
<enum 0 rd_stat> Report or Read statistics
<enum 1 srch_dis> Search disable. Report only Hash
<enum 2 Wr_bk_single> Write Back single entry
<enum 3 wr_bk_all> Write Back entire cache entry
<enum 4 inval_single> Invalidate single cache entry
<enum 5 inval_all> Invalidate entire cache
<enum 6 wr_bk_inval_single> Write back and Invalidate
single entry in cache
<enum 7 wr_bk_inval_all> write back and invalidate
entire cache
<enum 8 clr_stat_single> Clear statistics for single
entry
<legal 0-8>
Rest of the values reserved.
For all single entry control operations (write back,
Invalidate or both)Statistics will be reported
*/
#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000
#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0
#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f
/* Description TCL_STATUS_RING_0_ASE_FSE_SEL
Search Engine for which operation is done.
1'b0: Address Search Engine Result
1'b1: Flow Search Engine result
*/
#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000
#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4
#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010
/* Description TCL_STATUS_RING_0_CACHE_OP_RES
Cache operation result. Following are results of cache
operation.
<enum 0 op_done> Operation successful
<enum 1 not_fnd> Entry not found in Table
<enum 2 timeout_er> Timeout Error
<legal 0-2>
*/
#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000
#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5
#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060
/* Description TCL_STATUS_RING_0_RESERVED_0A
<legal 0>
*/
#define TCL_STATUS_RING_0_RESERVED_0A_OFFSET 0x00000000
#define TCL_STATUS_RING_0_RESERVED_0A_LSB 7
#define TCL_STATUS_RING_0_RESERVED_0A_MASK 0x00000080
/* Description TCL_STATUS_RING_0_MSDU_CNT_N
MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
4'b1000
*/
#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000
#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8
#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00
/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N
MSDU byte count for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
*/
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0
#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff
/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N
MSDU timestamp for entry 1. Valid when GSE_CTRL is
4'b0111 and 4'b1000
*/
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0
#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff
/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0
Meta data from input ring
<legal all>
*/
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0
#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff
/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32
Meta data from input ring
<legal all>
*/
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0
#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff
/* Description TCL_STATUS_RING_5_HASH_INDX_VAL
Hash value of the entry in table in case of search
failed or search disable.
<legal all>
*/
#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014
#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0
#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff
/* Description TCL_STATUS_RING_5_RESERVED_5A
<legal 0>
*/
#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014
#define TCL_STATUS_RING_5_RESERVED_5A_LSB 20
#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xfff00000
/* Description TCL_STATUS_RING_6_RESERVED_6A
<legal 0>
*/
#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018
#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0
#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff
/* Description TCL_STATUS_RING_7_RESERVED_7A
<legal 0>
*/
#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0
#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff
/* Description TCL_STATUS_RING_7_RING_ID
The buffer pointer ring ID.
Helps with debugging when dumping ring contents.
<legal all>
*/
#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_RING_ID_LSB 20
#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000
/* Description TCL_STATUS_RING_7_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28
#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000
#endif // _TCL_STATUS_RING_H_

82
hw/qca6290/v1/tlv_hdr.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TLV_HDR_H_
#define _TLV_HDR_H_
#if !defined(__ASSEMBLER__)
#endif
struct tlv_usr_16_hdr {
volatile uint16_t tlv_cflg_reserved : 1,
tlv_tag : 5,
tlv_len : 4,
tlv_usrid : 6;
};
struct tlv_16_hdr {
volatile uint16_t tlv_cflg_reserved : 1,
tlv_tag : 5,
tlv_len : 4,
tlv_reserved : 6;
};
struct tlv_usr_32_hdr {
volatile uint32_t tlv_cflg_reserved : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_usrid : 6;
};
struct tlv_32_hdr {
volatile uint32_t tlv_cflg_reserved : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_reserved : 6;
};
struct tlv_usr_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_usrid : 6,
tlv_reserved : 10,
pad_42to64_bit : 22;
};
struct tlv_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_tag : 9,
tlv_len : 16,
tlv_reserved : 16,
pad_42to64_bit : 22;
};
struct tlv_usr_c_42_hdr {
volatile uint64_t tlv_compression : 1,
tlv_ctag : 3,
tlv_usrid : 6,
tlv_cdata : 32,
pad_42to64_bit : 22;
};
#endif

453
hw/qca6290/v1/tlv_tag_def.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/**
* Generated file ... Do not hand edit ...
*/
#ifndef _TLV_TAG_DEF_
#define _TLV_TAG_DEF_
typedef enum {
WIFIMACTX_CBF_START_E = 0 /* 0x0 */,
WIFIPHYRX_DATA_E = 1 /* 0x1 */,
WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */,
WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */,
WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */,
WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */,
WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */,
WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */,
WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */,
WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */,
WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */,
WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */,
WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */,
WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */,
WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */,
WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */,
WIFIMACRX_NAP_USER_E = 16 /* 0x10 */,
WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */,
WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */,
WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */,
WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */,
WIFIPHYTX_PKT_END_E = 21 /* 0x15 */,
WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */,
WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */,
WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */,
WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */,
WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */,
WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */,
WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */,
WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */,
WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */,
WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */,
WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */,
WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */,
WIFIMACTX_PKT_END_E = 34 /* 0x22 */,
WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */,
WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */,
WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */,
WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */,
WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */,
WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */,
WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */,
WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */,
WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */,
WIFIMACTX_PHY_ON_E = 44 /* 0x2c */,
WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */,
WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */,
WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */,
WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */,
WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */,
WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */,
WIFIMACTX_HT_SIG_E = 51 /* 0x33 */,
WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */,
WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */,
WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */,
WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */,
WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */,
WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */,
WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */,
WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */,
WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */,
WIFIMACTX_SERVICE_E = 61 /* 0x3d */,
WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */,
WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */,
WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */,
WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */,
WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */,
WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */,
WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */,
WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */,
WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */,
WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */,
WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */,
WIFIMACTX_DEBUG_E = 73 /* 0x49 */,
WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */,
WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */,
WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */,
WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */,
WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */,
WIFIPHYRX_PKT_END_E = 79 /* 0x4f */,
WIFIPHYRX_DEBUG_E = 80 /* 0x50 */,
WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */,
WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */,
WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */,
WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */,
WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */,
WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */,
WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */,
WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */,
WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */,
WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */,
WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */,
WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */,
WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */,
WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */,
WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */,
WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */,
WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */,
WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */,
WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */,
WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */,
WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */,
WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */,
WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */,
WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */,
WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */,
WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */,
WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */,
WIFICOEX_TX_REQ_E = 108 /* 0x6c */,
WIFIDUMMY_E = 109 /* 0x6d */,
WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */,
WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */,
WIFIMPDU_LIMIT_E = 112 /* 0x70 */,
WIFINA_LENGTH_END_E = 113 /* 0x71 */,
WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */,
WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */,
WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */,
WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */,
WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */,
WIFIPDG_FES_SETUP_E = 119 /* 0x77 */,
WIFIPDG_RESPONSE_E = 120 /* 0x78 */,
WIFIPDG_TX_REQ_E = 121 /* 0x79 */,
WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */,
WIFISCHEDULER_TLV_E = 123 /* 0x7b */,
WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */,
WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */,
WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */,
WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */,
WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */,
WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */,
WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */,
WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */,
WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */,
WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */,
WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */,
WIFITQM_WRITE_CMD_E = 135 /* 0x87 */,
WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */,
WIFITX_DATA_E = 137 /* 0x89 */,
WIFITX_FES_SETUP_E = 138 /* 0x8a */,
WIFIRX_PACKET_E = 139 /* 0x8b */,
WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */,
WIFITX_MPDU_END_E = 141 /* 0x8d */,
WIFITX_MPDU_START_E = 142 /* 0x8e */,
WIFITX_MSDU_END_E = 143 /* 0x8f */,
WIFITX_MSDU_START_E = 144 /* 0x90 */,
WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */,
WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */,
WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */,
WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */,
WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */,
WIFIMPDU_INFO_E = 150 /* 0x96 */,
WIFIPDG_USER_SETUP_E = 151 /* 0x97 */,
WIFITX_11AH_SETUP_E = 152 /* 0x98 */,
WIFITX_CV_START_E = 153 /* 0x99 */,
WIFITX_PEER_ENTRY_E = 154 /* 0x9a */,
WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */,
WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */,
WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */,
WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */,
WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */,
WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */,
WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */,
WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */,
WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */,
WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */,
WIFISCHEDULER_CMD_E = 165 /* 0xa5 */,
WIFITX_FLUSH_E = 166 /* 0xa6 */,
WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */,
WIFITX_DATA_WORD_E = 168 /* 0xa8 */,
WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */,
WIFITX_MPDU_LINK_E = 170 /* 0xaa */,
WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */,
WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */,
WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */,
WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */,
WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */,
WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */,
WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */,
WIFITX_MSDU_LINK_E = 178 /* 0xb2 */,
WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */,
WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */,
WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */,
WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */,
WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */,
WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */,
WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */,
WIFIWBM_BUFFER_RING_E = 186 /* 0xba */,
WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */,
WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */,
WIFITX_FLUSH_REQ_E = 189 /* 0xbd */,
WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */,
WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */,
WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */,
WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */,
WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */,
WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */,
WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */,
WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */,
WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */,
WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */,
WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */,
WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */,
WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */,
WIFICOEX_RX_STATUS_E = 203 /* 0xcb */,
WIFIRX_START_PARAM_E = 204 /* 0xcc */,
WIFIRX_PPDU_START_E = 205 /* 0xcd */,
WIFIRX_PPDU_END_E = 206 /* 0xce */,
WIFIRX_MPDU_START_E = 207 /* 0xcf */,
WIFIRX_MPDU_END_E = 208 /* 0xd0 */,
WIFIRX_MSDU_START_E = 209 /* 0xd1 */,
WIFIRX_MSDU_END_E = 210 /* 0xd2 */,
WIFIRX_ATTENTION_E = 211 /* 0xd3 */,
WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */,
WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */,
WIFIRX_HEADER_E = 214 /* 0xd6 */,
WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */,
WIFIRX_FLUSH_E = 216 /* 0xd8 */,
WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */,
WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */,
WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */,
WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */,
WIFITX_CBF_INFO_E = 221 /* 0xdd */,
WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */,
WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */,
WIFIRX_PM_INFO_E = 224 /* 0xe0 */,
WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */,
WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */,
WIFIRX_PREAMBLE_E = 227 /* 0xe3 */,
WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */,
WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */,
WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */,
WIFIRXPCU_SETUP_E = 231 /* 0xe7 */,
WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */,
WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */,
WIFITQM_ACKED_MPDU_E = 234 /* 0xea */,
WIFICOEX_TX_RESP_E = 235 /* 0xeb */,
WIFICOEX_TX_STATUS_E = 236 /* 0xec */,
WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */,
WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */,
WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */,
WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */,
WIFICRYPTO_STATUS_E = 241 /* 0xf1 */,
WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */,
WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */,
WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */,
WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */,
WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */,
WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */,
WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */,
WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */,
WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */,
WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */,
WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */,
WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */,
WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */,
WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */,
WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */,
WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */,
WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */,
WIFIWHO_CCE_INFO_E = 259 /* 0x103 */,
WIFIWHO_COMMIT_E = 260 /* 0x104 */,
WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */,
WIFIWHO_FLUSH_E = 262 /* 0x106 */,
WIFIWHO_L2_LLC_E = 263 /* 0x107 */,
WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */,
WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */,
WIFIWHO_L3_INFO_E = 266 /* 0x10a */,
WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */,
WIFIWHO_L4_INFO_E = 268 /* 0x10c */,
WIFIWHO_MSDU_E = 269 /* 0x10d */,
WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */,
WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */,
WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */,
WIFIWHO_PPDU_END_E = 273 /* 0x111 */,
WIFIWHO_PPDU_START_E = 274 /* 0x112 */,
WIFIWHO_TSO_E = 275 /* 0x113 */,
WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */,
WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */,
WIFIWHO_WMAC_IV_E = 278 /* 0x116 */,
WIFIMPDU_INFO_END_E = 279 /* 0x117 */,
WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */,
WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */,
WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */,
WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */,
WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */,
WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */,
WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */,
WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */,
WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */,
WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */,
WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */,
WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */,
WIFIWHO_TERMINATE_E = 292 /* 0x124 */,
WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */,
WIFITX_CV_DATA_E = 294 /* 0x126 */,
WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */,
WIFIPPDU_TX_END_E = 296 /* 0x128 */,
WIFIPROT_TX_END_E = 297 /* 0x129 */,
WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */,
WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */,
WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */,
WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */,
WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */,
WIFINO_ACK_REPORT_E = 303 /* 0x12f */,
WIFIACK_REPORT_E = 304 /* 0x130 */,
WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */,
WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */,
WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */,
WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */,
WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */,
WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */,
WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */,
WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */,
WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */,
WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */,
WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */,
WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */,
WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */,
WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */,
WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */,
WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */,
WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */,
WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */,
WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */,
WIFITCL_DATA_CMD_E = 324 /* 0x144 */,
WIFITCL_GSE_CMD_E = 325 /* 0x145 */,
WIFITCL_EXIT_BASE_E = 326 /* 0x146 */,
WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */,
WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */,
WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */,
WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */,
WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */,
WIFITX_DATA_SYNC_E = 332 /* 0x14c */,
WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */,
WIFITCL_STATUS_RING_E = 334 /* 0x14e */,
WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */,
WIFITQM_SYNC_CMD_E = 336 /* 0x150 */,
WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */,
WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */,
WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */,
WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */,
WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */,
WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */,
WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */,
WIFIRX_MPDU_INFO_E = 344 /* 0x158 */,
WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */,
WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */,
WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */,
WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */,
WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */,
WIFIRX_RING_MASK_E = 350 /* 0x15e */,
WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */,
WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */,
WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */,
WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */,
WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */,
WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */,
WIFICOEX_MAC_NAP_E = 357 /* 0x165 */,
WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */,
WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */,
WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */,
WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */,
WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */,
WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */,
WIFIL_SIG_A_INFO_E = 364 /* 0x16c */,
WIFIL_SIG_B_INFO_E = 365 /* 0x16d */,
WIFIHT_SIG_INFO_E = 366 /* 0x16e */,
WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */,
WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */,
WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */,
WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */,
WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */,
WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */,
WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */,
WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */,
WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */,
WIFISERVICE_INFO_E = 376 /* 0x178 */,
WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */,
WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */,
WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */,
WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */,
WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */,
WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */,
WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */,
WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */,
WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */,
WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */,
WIFISCHEDULER_END_E = 387 /* 0x183 */,
WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */,
WIFISW_PEER_INFO_E = 389 /* 0x185 */,
WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */,
WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */,
WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */,
WIFITCL_CCE_INFO_E = 393 /* 0x189 */,
WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */,
WIFICCE_RULE_E = 395 /* 0x18b */,
WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */,
WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */,
WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */,
WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */,
WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */,
WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */,
WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */,
WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */,
WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */,
WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */,
WIFICE_SRC_DESC_E = 406 /* 0x196 */,
WIFICE_STAT_DESC_E = 407 /* 0x197 */,
WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */,
WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */,
WIFICMD_PART_0_END_E = 410 /* 0x19a */,
WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */,
WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */,
WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */,
WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */,
WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */,
WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */,
WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */,
WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */,
WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 420 /* 0x1a4 */,
WIFITLV_BASE_E = 511 /* 0x1ff */
} tlv_tag_def__e; ///< tlv_tag_def Enum Type
#endif // _TLV_TAG_DEF_

827
hw/qca6290/v1/tx_msdu_extension.h Normal file
View file

@ -0,0 +1,827 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TX_MSDU_EXTENSION_H_
#define _TX_MSDU_EXTENSION_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 tso_enable[0], ipv4_checksum_en[1], udp_over_ipv4_checksum_en[2], udp_over_ipv6_checksum_en[3], tcp_over_ipv4_checksum_en[4], tcp_over_ipv6_checksum_en[5], reserved_0a[6], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25]
// 1 l2_length[15:0], ip_length[31:16]
// 2 tcp_seq_number[31:0]
// 3 ip_identification[15:0], udp_length[31:16]
// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30]
// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17]
// 6 buf0_ptr_31_0[31:0]
// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16]
// 8 buf1_ptr_31_0[31:0]
// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16]
// 10 buf2_ptr_31_0[31:0]
// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16]
// 12 buf3_ptr_31_0[31:0]
// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16]
// 14 buf4_ptr_31_0[31:0]
// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16]
// 16 buf5_ptr_31_0[31:0]
// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
struct tx_msdu_extension {
uint32_t tso_enable : 1, //[0]
ipv4_checksum_en : 1, //[1]
udp_over_ipv4_checksum_en : 1, //[2]
udp_over_ipv6_checksum_en : 1, //[3]
tcp_over_ipv4_checksum_en : 1, //[4]
tcp_over_ipv6_checksum_en : 1, //[5]
reserved_0a : 1, //[6]
tcp_flag : 9, //[15:7]
tcp_flag_mask : 9, //[24:16]
reserved_0b : 7; //[31:25]
uint32_t l2_length : 16, //[15:0]
ip_length : 16; //[31:16]
uint32_t tcp_seq_number : 32; //[31:0]
uint32_t ip_identification : 16, //[15:0]
udp_length : 16; //[31:16]
uint32_t checksum_offset : 14, //[13:0]
partial_checksum_en : 1, //[14]
reserved_4a : 1, //[15]
payload_start_offset : 14, //[29:16]
reserved_4b : 2; //[31:30]
uint32_t payload_end_offset : 14, //[13:0]
reserved_5a : 2, //[15:14]
wds : 1, //[16]
reserved_5b : 15; //[31:17]
uint32_t buf0_ptr_31_0 : 32; //[31:0]
uint32_t buf0_ptr_39_32 : 8, //[7:0]
reserved_7a : 8, //[15:8]
buf0_len : 16; //[31:16]
uint32_t buf1_ptr_31_0 : 32; //[31:0]
uint32_t buf1_ptr_39_32 : 8, //[7:0]
reserved_9a : 8, //[15:8]
buf1_len : 16; //[31:16]
uint32_t buf2_ptr_31_0 : 32; //[31:0]
uint32_t buf2_ptr_39_32 : 8, //[7:0]
reserved_11a : 8, //[15:8]
buf2_len : 16; //[31:16]
uint32_t buf3_ptr_31_0 : 32; //[31:0]
uint32_t buf3_ptr_39_32 : 8, //[7:0]
reserved_13a : 8, //[15:8]
buf3_len : 16; //[31:16]
uint32_t buf4_ptr_31_0 : 32; //[31:0]
uint32_t buf4_ptr_39_32 : 8, //[7:0]
reserved_15a : 8, //[15:8]
buf4_len : 16; //[31:16]
uint32_t buf5_ptr_31_0 : 32; //[31:0]
uint32_t buf5_ptr_39_32 : 8, //[7:0]
reserved_17a : 8, //[15:8]
buf5_len : 16; //[31:16]
};
/*
tso_enable
Enable transmit segmentation offload <legal all>
ipv4_checksum_en
Enable IPv4 checksum replacement
udp_over_ipv4_checksum_en
Enable UDP over IPv4 checksum replacement. UDP checksum
over IPv4 is optional for TCP/IP stacks.
udp_over_ipv6_checksum_en
Enable UDP over IPv6 checksum replacement. UDP checksum
over IPv6 is mandatory for TCP/IP stacks.
tcp_over_ipv4_checksum_en
Enable TCP checksum over IPv4 replacement
tcp_over_ipv6_checksum_en
Enable TCP checksum over IPv6 eplacement
reserved_0a
FW will set to 0, MAC will ignore.  <legal 0>
tcp_flag
TCP flags
{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
tcp_flag_mask
TCP flag mask. Tcp_flag is inserted into the header
based on the mask, if tso is enabled
reserved_0b
FW will set to 0, MAC will ignore.  <legal 0>
l2_length
L2 length for the msdu, if tso is enabled <legal all>
ip_length
Ip length for the msdu, if tso is enabled <legal all>
tcp_seq_number
Tcp_seq_number for the msdu, if tso is enabled <legal
all>
ip_identification
Ip_identification for the msdu, if tso is enabled <legal
all>
udp_length
TXDMA is copies this field into MSDU START TLV
checksum_offset
The calculated checksum from start offset to end offset
will be added to the checksum at the offset given by this
field<legal all>
partial_checksum_en
Partial Checksum Enable Bit.
<legal 0-1>
reserved_4a
<Legal 0>
payload_start_offset
L4 checksum calculations will start fromt this offset
<Legal all>
reserved_4b
<Legal 0>
payload_end_offset
L4 checksum calculations will end at this offset.
<Legal all>
reserved_5a
<Legal 0>
wds
If set the current packet is 4-address frame. Required
because an aggregate can include some frames with 3 address
format and other frames with 4 address format. Used by the
OLE during encapsulation.
Note: there is also global wds tx control in the
TX_PEER_ENTRY
<legal all>
reserved_5b
<Legal 0>
buf0_ptr_31_0
Lower 32 bits of the first buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf0_ptr_39_32
Upper 8 bits of the first buffer pointer <legal all>
reserved_7a
<Legal 0>
buf0_len
Length of the first buffer <legal all>
buf1_ptr_31_0
Lower 32 bits of the second buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf1_ptr_39_32
Upper 8 bits of the second buffer pointer <legal all>
reserved_9a
<Legal 0>
buf1_len
Length of the second buffer <legal all>
buf2_ptr_31_0
Lower 32 bits of the third buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf2_ptr_39_32
Upper 8 bits of the third buffer pointer <legal all>
reserved_11a
<Legal 0>
buf2_len
Length of the third buffer <legal all>
buf3_ptr_31_0
Lower 32 bits of the fourth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf3_ptr_39_32
Upper 8 bits of the fourth buffer pointer <legal all>
reserved_13a
<Legal 0>
buf3_len
Length of the fourth buffer <legal all>
buf4_ptr_31_0
Lower 32 bits of the fifth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf4_ptr_39_32
Upper 8 bits of the fifth buffer pointer <legal all>
reserved_15a
<Legal 0>
buf4_len
Length of the fifth buffer <legal all>
buf5_ptr_31_0
Lower 32 bits of the sixth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
buf5_ptr_39_32
Upper 8 bits of the sixth buffer pointer <legal all>
reserved_17a
<Legal 0>
buf5_len
Length of the sixth buffer <legal all>
*/
/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE
Enable transmit segmentation offload <legal all>
*/
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0
#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001
/* Description TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN
Enable IPv4 checksum replacement
*/
#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_LSB 1
#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_MASK 0x00000002
/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN
Enable UDP over IPv4 checksum replacement. UDP checksum
over IPv4 is optional for TCP/IP stacks.
*/
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_LSB 2
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000004
/* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN
Enable UDP over IPv6 checksum replacement. UDP checksum
over IPv6 is mandatory for TCP/IP stacks.
*/
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_LSB 3
#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000008
/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN
Enable TCP checksum over IPv4 replacement
*/
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_LSB 4
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000010
/* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN
Enable TCP checksum over IPv6 eplacement
*/
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_LSB 5
#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000020
/* Description TX_MSDU_EXTENSION_0_RESERVED_0A
FW will set to 0, MAC will ignore.  <legal 0>
*/
#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 6
#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x00000040
/* Description TX_MSDU_EXTENSION_0_TCP_FLAG
TCP flags
{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
*/
#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80
/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK
TCP flag mask. Tcp_flag is inserted into the header
based on the mask, if tso is enabled
*/
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16
#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000
/* Description TX_MSDU_EXTENSION_0_RESERVED_0B
FW will set to 0, MAC will ignore.  <legal 0>
*/
#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000
#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25
#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000
/* Description TX_MSDU_EXTENSION_1_L2_LENGTH
L2 length for the msdu, if tso is enabled <legal all>
*/
#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0
#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff
/* Description TX_MSDU_EXTENSION_1_IP_LENGTH
Ip length for the msdu, if tso is enabled <legal all>
*/
#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004
#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER
Tcp_seq_number for the msdu, if tso is enabled <legal
all>
*/
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0
#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION
Ip_identification for the msdu, if tso is enabled <legal
all>
*/
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0
#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff
/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH
TXDMA is copies this field into MSDU START TLV
*/
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16
#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET
The calculated checksum from start offset to end offset
will be added to the checksum at the offset given by this
field<legal all>
*/
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff
/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN
Partial Checksum Enable Bit.
<legal 0-1>
*/
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14
#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000
/* Description TX_MSDU_EXTENSION_4_RESERVED_4A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15
#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000
/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET
L4 checksum calculations will start fromt this offset
<Legal all>
*/
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16
#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000
/* Description TX_MSDU_EXTENSION_4_RESERVED_4B
<Legal 0>
*/
#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010
#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30
#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000
/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET
L4 checksum calculations will end at this offset.
<Legal all>
*/
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0
#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff
/* Description TX_MSDU_EXTENSION_5_RESERVED_5A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14
#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000
/* Description TX_MSDU_EXTENSION_5_WDS
If set the current packet is 4-address frame. Required
because an aggregate can include some frames with 3 address
format and other frames with 4 address format. Used by the
OLE during encapsulation.
Note: there is also global wds tx control in the
TX_PEER_ENTRY
<legal all>
*/
#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_WDS_LSB 16
#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000
/* Description TX_MSDU_EXTENSION_5_RESERVED_5B
<Legal 0>
*/
#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014
#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17
#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000
/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0
Lower 32 bits of the first buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32
Upper 8 bits of the first buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_7_RESERVED_7A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8
#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_7_BUF0_LEN
Length of the first buffer <legal all>
*/
#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c
#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16
#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0
Lower 32 bits of the second buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32
Upper 8 bits of the second buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_9_RESERVED_9A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8
#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_9_BUF1_LEN
Length of the second buffer <legal all>
*/
#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024
#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16
#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0
Lower 32 bits of the third buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32
Upper 8 bits of the third buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_11_RESERVED_11A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8
#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_11_BUF2_LEN
Length of the third buffer <legal all>
*/
#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c
#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16
#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0
Lower 32 bits of the fourth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32
Upper 8 bits of the fourth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_13_RESERVED_13A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8
#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_13_BUF3_LEN
Length of the fourth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034
#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16
#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0
Lower 32 bits of the fifth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32
Upper 8 bits of the fifth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_15_RESERVED_15A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8
#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_15_BUF4_LEN
Length of the fifth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c
#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16
#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000
/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0
Lower 32 bits of the sixth buffer pointer
NOTE: SW/FW manages the 'cookie' info related to this
buffer together with the 'cookie' info for this
MSDU_EXTENSION descriptor
<legal all>
*/
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0
#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff
/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32
Upper 8 bits of the sixth buffer pointer <legal all>
*/
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0
#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff
/* Description TX_MSDU_EXTENSION_17_RESERVED_17A
<Legal 0>
*/
#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8
#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00
/* Description TX_MSDU_EXTENSION_17_BUF5_LEN
Length of the sixth buffer <legal all>
*/
#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044
#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16
#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000
#endif // _TX_MSDU_EXTENSION_H_

458
hw/qca6290/v1/tx_rate_stats_info.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _TX_RATE_STATS_INFO_H_
#define _TX_RATE_STATS_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28]
// 1 tsf_directly_after_ppdu_transmission[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
struct tx_rate_stats_info {
uint32_t tx_rate_stats_info_valid : 1, //[0]
transmit_bw : 2, //[2:1]
transmit_pkt_type : 4, //[6:3]
transmit_stbc : 1, //[7]
transmit_ldpc : 1, //[8]
transmit_sgi : 2, //[10:9]
transmit_mcs : 4, //[14:11]
ofdma_transmission : 1, //[15]
tones_in_ru : 12, //[27:16]
reserved_0a : 4; //[31:28]
uint32_t tsf_directly_after_ppdu_transmission: 32; //[31:0]
};
/*
tx_rate_stats_info_valid
When set all other fields in this STRUCT contain valid
info.
<legal all>
transmit_bw
Field only valid when Tx_rate_stats_info_valid is set
Indicates the BW of the upcoming transmission that shall
likely start in about 3 -4 us on the medium
<enum 0 transmit_bw_20_MHz>
<enum 1 transmit_bw_40_MHz>
<enum 2 transmit_bw_80_MHz>
<enum 3 transmit_bw_160_MHz>
<legal all>
transmit_pkt_type
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The packet type
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
transmit_stbc
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, STBC transmission rate was used.
transmit_ldpc
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, use LDPC transmission rates
transmit_sgi
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
<enum 0 0_8_us_sgi > Legacy normal GI
<enum 1 0_4_us_sgi > Legacy short GI
<enum 2 1_6_us_sgi > HE related GI
<enum 3 3_2_us_sgi > HE related GI
<legal 0 - 3>
transmit_mcs
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
For details, refer to MCS_TYPE description
<legal all>
ofdma_transmission
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Set when the transmission was an OFDMA transmission (DL
or UL).
<legal all>
tones_in_ru
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The number of tones in the RU used.
TODO: not clear yet what the number of tones is for RUs
of 160 or 80 + 80 ???
For now assumption is that this value for this scenario
will indicate: 0x7FF
<legal all>
reserved_0a
<legal 0>
tsf_directly_after_ppdu_transmission
Field only valid when Tx_rate_stats_info_valid is set
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame finished.
<legal all>
*/
/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID
When set all other fields in this STRUCT contain valid
info.
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0
#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW
Field only valid when Tx_rate_stats_info_valid is set
Indicates the BW of the upcoming transmission that shall
likely start in about 3 -4 us on the medium
<enum 0 transmit_bw_20_MHz>
<enum 1 transmit_bw_40_MHz>
<enum 2 transmit_bw_80_MHz>
<enum 3 transmit_bw_160_MHz>
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1
#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The packet type
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3
#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, STBC transmission rate was used.
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7
#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
When set, use LDPC transmission rates
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8
#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
<enum 0 0_8_us_sgi > Legacy normal GI
<enum 1 0_4_us_sgi > Legacy short GI
<enum 2 1_6_us_sgi > HE related GI
<enum 3 3_2_us_sgi > HE related GI
<legal 0 - 3>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9
#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600
/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
For details, refer to MCS_TYPE description
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11
#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800
/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Set when the transmission was an OFDMA transmission (DL
or UL).
<legal all>
*/
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15
#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000
/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU
Field only valid when Tx_rate_stats_info_valid is set
Field filled in by PDG.
Not valid when in SW transmit mode
The number of tones in the RU used.
TODO: not clear yet what the number of tones is for RUs
of 160 or 80 + 80 ???
For now assumption is that this value for this scenario
will indicate: 0x7FF
<legal all>
*/
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16
#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000
/* Description TX_RATE_STATS_INFO_0_RESERVED_0A
<legal 0>
*/
#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000
#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28
#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000
/* Description TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION
Field only valid when Tx_rate_stats_info_valid is set
Lower 32 bits of the TSF, snapshot of this value when
transmission of the PPDU containing the frame finished.
<legal all>
*/
#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_OFFSET 0x00000004
#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_LSB 0
#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_MASK 0xffffffff
#endif // _TX_RATE_STATS_INFO_H_

229
hw/qca6290/v1/uniform_descriptor_header.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
#define _UNIFORM_DESCRIPTOR_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
struct uniform_descriptor_header {
uint32_t owner : 4, //[3:0]
buffer_type : 4, //[7:4]
reserved_0a : 24; //[31:8]
};
/*
owner
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
The owner of this data structure:
<enum 0 WBM_owned> Buffer Manager currently owns this
data structure.
<enum 1 SW_OR_FW_owned> Software of FW currently owns
this data structure.
<enum 2 TQM_owned> Transmit Queue Manager currently owns
this data structure.
<enum 3 RXDMA_owned> Receive DMA currently owns this
data structure.
<enum 4 REO_owned> Reorder currently owns this data
structure.
<enum 5 SWITCH_owned> SWITCH currently owns this data
structure.
<legal 0-5>
buffer_type
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Field describing what contents format is of this
descriptor
<enum 0 Transmit_MSDU_Link_descriptor >
<enum 1 Transmit_MPDU_Link_descriptor >
<enum 2 Transmit_MPDU_Queue_head_descriptor>
<enum 3 Transmit_MPDU_Queue_ext_descriptor>
<enum 4 Transmit_flow_descriptor>
<enum 5 Transmit_buffer >
<enum 6 Receive_MSDU_Link_descriptor >
<enum 7 Receive_MPDU_Link_descriptor >
<enum 8 Receive_REO_queue_descriptor >
<enum 9 Receive_REO_queue_ext_descriptor >
<enum 10 Receive_buffer >
<enum 11 Idle_link_list_entry>
<legal 0-11>
reserved_0a
<legal 0>
*/
/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
The owner of this data structure:
<enum 0 WBM_owned> Buffer Manager currently owns this
data structure.
<enum 1 SW_OR_FW_owned> Software of FW currently owns
this data structure.
<enum 2 TQM_owned> Transmit Queue Manager currently owns
this data structure.
<enum 3 RXDMA_owned> Receive DMA currently owns this
data structure.
<enum 4 REO_owned> Reorder currently owns this data
structure.
<enum 5 SWITCH_owned> SWITCH currently owns this data
structure.
<legal 0-5>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0
#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f
/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE
Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
Field describing what contents format is of this
descriptor
<enum 0 Transmit_MSDU_Link_descriptor >
<enum 1 Transmit_MPDU_Link_descriptor >
<enum 2 Transmit_MPDU_Queue_head_descriptor>
<enum 3 Transmit_MPDU_Queue_ext_descriptor>
<enum 4 Transmit_flow_descriptor>
<enum 5 Transmit_buffer >
<enum 6 Receive_MSDU_Link_descriptor >
<enum 7 Receive_MPDU_Link_descriptor >
<enum 8 Receive_REO_queue_descriptor >
<enum 9 Receive_REO_queue_ext_descriptor >
<enum 10 Receive_buffer >
<enum 11 Idle_link_list_entry>
<legal 0-11>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4
#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0
/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8
#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00
#endif // _UNIFORM_DESCRIPTOR_HEADER_H_

141
hw/qca6290/v1/uniform_reo_cmd_header.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _UNIFORM_REO_CMD_HEADER_H_
#define _UNIFORM_REO_CMD_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
struct uniform_reo_cmd_header {
uint32_t reo_cmd_number : 16, //[15:0]
reo_status_required : 1, //[16]
reserved_0a : 15; //[31:17]
};
/*
reo_cmd_number
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
reo_status_required
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
reserved_0a
<legal 0>
*/
/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER
Consumer: REO/SW/DEBUG
Producer: SW
This number can be used by SW to track, identify and
link the created commands with the command statusses
<legal all>
*/
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0
#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff
/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED
Consumer: REO
Producer: SW
<enum 0 NoStatus> REO does not need to generate a status
TLV for the execution of this command
<enum 1 StatusRequired> REO shall generate a status TLV
for the execution of this command
<legal all>
*/
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16
#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000
/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17
#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000
#endif // _UNIFORM_REO_CMD_HEADER_H_

250
hw/qca6290/v1/uniform_reo_status_header.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _UNIFORM_REO_STATUS_HEADER_H_
#define _UNIFORM_REO_STATUS_HEADER_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28]
// 1 timestamp[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
struct uniform_reo_status_header {
uint32_t reo_status_number : 16, //[15:0]
cmd_execution_time : 10, //[25:16]
reo_cmd_execution_status : 2, //[27:26]
reserved_0a : 4; //[31:28]
uint32_t timestamp : 32; //[31:0]
};
/*
reo_status_number
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
cmd_execution_time
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
reo_cmd_execution_status
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
reserved_0a
<legal 0>
timestamp
Timestamp at the moment that this status report is
written.
<legal all>
*/
/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER
Consumer: SW , DEBUG
Producer: REO
The value in this field is equal to value of the
'REO_CMD_Number' field the REO command
This field helps to correlate the statuses with the REO
commands.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0
#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff
/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME
Consumer: DEBUG
Producer: REO
The amount of time REO took to excecute the command.
Note that this time does not include the duration of the
command waiting in the command ring, before the execution
started.
In us.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16
#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000
/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS
Consumer: DEBUG
Producer: REO
Execution status of the command.
<enum 0 reo_successful_execution> Command has
successfully be executed
<enum 1 reo_blocked_execution> Command could not be
executed as the queue or cache was blocked
<enum 2 reo_failed_execution> Command has encountered
problems when executing, like the queue descriptor not being
valid. None of the status fields in the entire STATUS TLV
are valid.
<enum 3 reo_resource_blocked> Command is NOT executed
because one or more descriptors were blocked. This is SW
programming mistake.
None of the status fields in the entire STATUS TLV are
valid.
<legal 0-3>
*/
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26
#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A
<legal 0>
*/
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28
#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000
/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP
Timestamp at the moment that this status report is
written.
<legal all>
*/
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0
#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff
#endif // _UNIFORM_REO_STATUS_HEADER_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _WBM_BUFFER_RING_H_
#define _WBM_BUFFER_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buf_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
struct wbm_buffer_ring {
struct buffer_addr_info buf_addr_info;
};
/*
struct buffer_addr_info buf_addr_info
Consumer: WBM
Producer: WBM
Details of the physical address of the buffer + source
buffer owner + some SW meta data.
All modules getting this buffer address info, shall keep
all the 64 bits of info in this descriptor together and
eventually all 64 bits shall be given back to WMB when the
buffer is released.
*/
#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000000
#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0
#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff
#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 0x00000004
#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB 0
#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK 0xffffffff
#endif // _WBM_BUFFER_RING_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
#define _WBM_LINK_DESCRIPTOR_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info desc_addr_info;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
struct wbm_link_descriptor_ring {
struct buffer_addr_info desc_addr_info;
};
/*
struct buffer_addr_info desc_addr_info
Consumer: WBM
Producer: WBM
Details of the physical address of the buffer + source
buffer owner + some SW meta data
All modules getting this link descriptor address info,
shall keep all the 64 bits in this descriptor together and
eventually all 64 bits shall be given back to WBM when the
link descriptor is released.
*/
#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000000
#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0
#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff
#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000004
#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0
#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff
#endif // _WBM_LINK_DESCRIPTOR_RING_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WBM_REG_SEQ_BASE_H__
#define __WBM_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

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hw/qca6290/v1/wbm_release_ring.h Normal file
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hw/qca6290/v1/wcss_seq_hwiobase.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WCSS_SEQ_BASE_H__
#define __WCSS_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcss
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WCSS_ECAHB_OFFSET 0x00008000
#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000
#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000
#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00240000
#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET 0x00250000
#define SEQ_WCSS_PHYA0_OFFSET 0x00400000
#define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000
#define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET 0x00480000
#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400
#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800
#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00
#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000
#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400
#define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET 0x00484000
#define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET 0x00488000
#define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET 0x00500000
#define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET 0x00520000
#define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET 0x00528000
#define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00530000
#define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000
#define SEQ_WCSS_PHYA1_OFFSET 0x00600000
#define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00600000
#define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET 0x00680000
#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00680400
#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00680800
#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00680c00
#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00681000
#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00681400
#define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET 0x00684000
#define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET 0x00688000
#define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET 0x00700000
#define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET 0x00720000
#define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET 0x00728000
#define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00730000
#define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET 0x007a0000
#define SEQ_WCSS_PHYB_OFFSET 0x00800000
#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000
#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000
#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400
#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000
#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000
#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00900000
#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000
#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000
#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000
#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000
#define SEQ_WCSS_UMAC_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000
#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000
#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000
#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000
#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000
#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000
#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000
#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000
#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000
#define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000
#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000
#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000
#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000
#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000
#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000
#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000
#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000
#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000
#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000
#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000
#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000
#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000
#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000
#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000
#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000
#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000
#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000
#define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000
#define SEQ_WCSS_WMAC1_OFFSET 0x00ac0000
#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00ac0000
#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00ac3000
#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00ac6000
#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00ac9000
#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00acc000
#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00acf000
#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00ad2000
#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00ad5000
#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00ad8000
#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00adb000
#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00ade000
#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00ae1000
#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00ae4000
#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00ae7000
#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00aea000
#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00af0000
#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000
#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000
#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000
#define SEQ_WCSS_WMAC2_OFFSET 0x00b00000
#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000
#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000
#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000
#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000
#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000
#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000
#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000
#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000
#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000
#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000
#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000
#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000
#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000
#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000
#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000
#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000
#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000
#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000
#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000
#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000
#define SEQ_WCSS_WCMN_OFFSET 0x00b50000
#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000
#define SEQ_WCSS_PMM_OFFSET 0x00b70000
#define SEQ_WCSS_ZINC_RFA_CMN_OFFSET 0x00b80000
#define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET 0x00b80000
#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET 0x00b80100
#define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET 0x00b82000
#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET 0x00b82100
#define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00b84000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00b88000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00b88100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00b88200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00b88300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00b88500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00b88600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00b88800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00b88900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00b88a00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00b88b00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00b88d00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00b88e00
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00b89000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00b89100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00b89200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00b89300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00b89500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00b89600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00b89800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00b89900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00b89a00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00b89b00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00b89d00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00b89e00
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x00b8a000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x00b8a100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x00b8a200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x00b8a300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x00b8a500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x00b8a600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x00b8a800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x00b8a900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x00b8aa00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x00b8ab00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x00b8ad00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x00b8ae00
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x00b8b000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x00b8b100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x00b8b200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x00b8b300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x00b8b500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x00b8b600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x00b8b800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x00b8b900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x00b8ba00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x00b8bb00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x00b8bd00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x00b8be00
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x00b8c000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x00b8c100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x00b8c200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x00b8c300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x00b8c440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x00b8c4c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x00b8c500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x00b8c600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x00b8c800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x00b8c900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x00b8ca00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x00b8cb00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x00b8cc40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x00b8ccc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x00b8cd00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x00b8ce00
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x00b8d000
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x00b8d100
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x00b8d200
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x00b8d300
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x00b8d440
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x00b8d4c0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x00b8d500
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x00b8d600
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x00b8d800
#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x00b8d900
#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x00b8da00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x00b8db00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x00b8dc40
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x00b8dcc0
#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x00b8dd00
#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x00b8de00
#define SEQ_WCSS_DBG_OFFSET 0x00b90000
#define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000
#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000
#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000
#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000
#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000
#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280
#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280
#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000
#define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000
#define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000
#define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000
#define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000
#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000
#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000
#define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000
#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000
#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET 0x00bbf000
#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000
#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000
#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000
#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000
#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000
#define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000
#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000
#define SEQ_WCSS_CC_OFFSET 0x00c30000
#define SEQ_WCSS_ACMT_OFFSET 0x00c40000
#define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000
#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00c60000
#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000
#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000
#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000
#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfax_top
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000
#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000
#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400
#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000
#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000
#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000
#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000
#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000
#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00130000
#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfax_top_b
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000
#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400
#define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000
#define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000
#define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000
#define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000
#define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000
#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000
#define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block umac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000
#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000
#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000
#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000
#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000
#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000
#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000
#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000
#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000
#define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfss_ce_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block cxc_top_reg_14lpp
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET 0x00000000
#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET 0x00002000
#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET 0x00004000
#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET 0x00006000
#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET 0x00008000
#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET 0x0000a000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wmac_top_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000
#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000
#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000
#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000
#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000
#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000
#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000
#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000
#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000
#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000
#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000
#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000
#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000
#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000
#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000
#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_cmn
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_CMN_PLL_A_OFFSET 0x00000000
#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET 0x00000100
#define SEQ_RFA_CMN_PLL_B_OFFSET 0x00002000
#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET 0x00002100
#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET 0x00004000
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET 0x00008000
#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET 0x00008100
#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET 0x00008200
#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET 0x00008300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00008400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00008440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00008480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x000084c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET 0x00008500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET 0x00008600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET 0x00008800
#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET 0x00008900
#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET 0x00008a00
#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET 0x00008b00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00008c00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00008c40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00008c80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00008cc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET 0x00008d00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET 0x00008e00
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET 0x00009000
#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET 0x00009100
#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET 0x00009200
#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET 0x00009300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00009400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00009440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00009480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x000094c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET 0x00009500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET 0x00009600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET 0x00009800
#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET 0x00009900
#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET 0x00009a00
#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET 0x00009b00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00009c00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00009c40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00009c80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00009cc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET 0x00009d00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET 0x00009e00
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET 0x0000a000
#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET 0x0000a100
#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET 0x0000a200
#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET 0x0000a300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x0000a400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x0000a440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x0000a480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x0000a4c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET 0x0000a500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET 0x0000a600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET 0x0000a800
#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET 0x0000a900
#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET 0x0000aa00
#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET 0x0000ab00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x0000ac00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x0000ac40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x0000ac80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x0000acc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET 0x0000ad00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET 0x0000ae00
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET 0x0000b000
#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET 0x0000b100
#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET 0x0000b200
#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET 0x0000b300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x0000b400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x0000b440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x0000b480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x0000b4c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET 0x0000b500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET 0x0000b600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET 0x0000b800
#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET 0x0000b900
#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET 0x0000ba00
#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET 0x0000bb00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x0000bc00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x0000bc40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x0000bc80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x0000bcc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET 0x0000bd00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET 0x0000be00
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET 0x0000c000
#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET 0x0000c100
#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET 0x0000c200
#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET 0x0000c300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x0000c400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET 0x0000c440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x0000c480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET 0x0000c4c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET 0x0000c500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET 0x0000c600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET 0x0000c800
#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET 0x0000c900
#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET 0x0000ca00
#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET 0x0000cb00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x0000cc00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET 0x0000cc40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x0000cc80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET 0x0000ccc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET 0x0000cd00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET 0x0000ce00
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET 0x0000d000
#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET 0x0000d100
#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET 0x0000d200
#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET 0x0000d300
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x0000d400
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET 0x0000d440
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x0000d480
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET 0x0000d4c0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET 0x0000d500
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET 0x0000d600
#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET 0x0000d800
#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET 0x0000d900
#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET 0x0000da00
#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET 0x0000db00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x0000dc00
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET 0x0000dc40
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x0000dc80
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET 0x0000dcc0
#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET 0x0000dd00
#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET 0x0000de00
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcssdbg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000
#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000
#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000
#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000
#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000
#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280
#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280
#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000
#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000
#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000
#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000
#define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000
#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000
#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000
#define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000
#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000
#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET 0x0002f000
#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000
#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000
#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000
#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000
#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET 0x00060000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280
#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wrapper_acmt
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6ss_public
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block qdsp6ss_private
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000
#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000
#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000
#define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000
#define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000
#define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000
#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000
#endif

70
hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WFSS_CE_REG_SEQ_BASE_H__
#define __WFSS_CE_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wfss_ce_reg
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000
#endif

2361
hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h Normal file
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52
hw/qca6290/v1/wfss_pmm_base_struct.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
//////////////////////////////////////////////////////////////////////////////
// wfss_pmm_base_struct.h generated by: GenCStruct.pm
//////////////////////////////////////////////////////////////////////////////
// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
//////////////////////////////////////////////////////////////////////////////
// RCS File : -USE CVS LOG-
// Revision : -USE CVS LOG-
// Last Check In : -USE CVS LOG-
//////////////////////////////////////////////////////////////////////////////
// Description : Top C Struct file
//
//////////////////////////////////////////////////////////////////////////////
#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#ifdef _LSB_TO_MSB_REGS
#ifdef _MSB_TO_LSB_REGS
#error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS!
#endif
#define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#include "wfss_pmm_base_struct_ltm.h"
#endif
#ifdef _MSB_TO_LSB_REGS
#define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#include "wfss_pmm_base_struct_mtl.h"
#endif
#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
#error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS
#endif
#endif

131
hw/qca8074/v1/HALcomdef.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_COMDEF_H
#define HAL_COMDEF_H
/*
==============================================================================
FILE: HALcomdef.h
DESCRIPTION:
==============================================================================
Edit History
$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $
when who what, where, why
-------- --- -----------------------------------------------------------
06/17/10 sc Included com_dtypes.h and cleaned up typedefs
05/15/08 gfr Added HAL_ENUM_32BITS macro.
02/14/08 gfr Added bool32 type.
11/13/07 gfr Removed dependency on comdef.h
01/08/07 hxw Created
*/
/*
* Assembly wrapper
*/
#ifndef _ARM_ASM_
/*
* C++ wrapper
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "com_dtypes.h"
/* -----------------------------------------------------------------------
** Types
** ----------------------------------------------------------------------- */
/*
* Standard integer types.
*
* bool32 - boolean, 32 bit (TRUE or FALSE)
*/
#ifndef _BOOL32_DEFINED
typedef unsigned long int bool32;
#define _BOOL32_DEFINED
#endif
/*
* Macro to allow forcing an enum to 32 bits. The argument should be
* an identifier in the namespace of the enumeration in question, i.e.
* for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
*/
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
/*===========================================================================
FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
DESCRIPTION
IN/OUT port macros for byte and word ports, typically inlined by compilers
which support these routines
PARAMETERS
inp( xx_addr )
inpw( xx_addr )
inpdw( xx_addr )
outp( xx_addr, xx_byte_val )
outpw( xx_addr, xx_word_val )
outpdw( xx_addr, xx_dword_val )
xx_addr - Address of port to read or write (may be memory mapped)
xx_byte_val - 8 bit value to write
xx_word_val - 16 bit value to write
xx_dword_val - 32 bit value to write
DEPENDENCIES
None
RETURN VALUE
inp/inpw/inpdw: the byte, word or dword read from the given address
outp/outpw/outpdw: the byte, word or dword written to the given address
SIDE EFFECTS
None.
===========================================================================*/
/* ARM based targets use memory mapped i/o, so the inp/outp calls are
** macroized to access memory directly
*/
#define inp(port) (*((volatile byte *) (port)))
#define inpw(port) (*((volatile word *) (port)))
#define inpdw(port) (*((volatile dword *)(port)))
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
#ifdef __cplusplus
}
#endif
#endif /* !_ARM_ASM_ */
#endif /* HAL_COMDEF_H */

490
hw/qca8074/v1/HALhwio.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HAL_HWIO_H
#define HAL_HWIO_H
/*
===========================================================================
*/
/**
@file HALhwio.h
Public interface include file for accessing the HWIO HAL definitions.
The HALhwio.h file is the public API interface to the HW I/O (HWIO)
register access definitions.
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Common types.
*/
#include "HALcomdef.h"
/* -----------------------------------------------------------------------
** Macros
** ----------------------------------------------------------------------- */
/**
@addtogroup macros
@{
*/
/**
* Map a base name to the pointer to access the base.
*
* This macro maps a base name to the pointer to access the base.
* This is generally just used internally.
*
*/
#define HWIO_BASE_PTR(base) base##_BASE_PTR
/**
* Declare a HWIO base pointer.
*
* This macro will declare a HWIO base pointer data structure. The pointer
* will always be declared as a weak symbol so multiple declarations will
* resolve correctly to the same data at link-time.
*/
#ifdef __ARMCC_VERSION
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
#else
#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
#endif
/**
@}
*/
/**
@addtogroup hwio_macros
@{
*/
/**
* @name Address Macros
*
* Macros for getting register addresses.
* These macros are used for retrieving the address of a register.
* HWIO_ADDR* will return the directly accessible address (virtual or physical based
* on environment), HWIO_PHYS* will always return the physical address.
* The offset from the base region can be retrieved using HWIO_OFFS*.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* @{
*/
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
/** @} */
/**
* @name Input Macros
*
* These macros are used for reading from a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the input will be masked with the supplied mask. The HWIO_INF*
* macros take a field name and will do the appropriate masking and shifting
* to return just the value of that field.
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
*
* Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
*
* @{
*/
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
/** @} */
/**
* @name Output Macros
*
* These macros are used for writing to a named hardware register. Register
* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
* indicates that the output will be masked with the supplied mask (meaning these
* macros do a read first, mask in the supplied data, then write it back).
* The "X" extension is used for explicit addressing where the base address of
* the module in question is provided as an argument to the macro.
* The HWIO_OUTF* macros take a field name and will do the appropriate masking
* and shifting to output just the value of that field.
* HWIO_OUTV* registers take a named value instead of a numeric value and
* do the same masking/shifting as HWIO_OUTF.
*
* Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
*
* @{
*/
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
/** @} */
/**
* @name Shift and Mask Macros
*
* Macros for getting shift and mask values for fields and registers.
* HWIO_RMSK: The mask value for accessing an entire register. For example:
* @code
* HWIO_RMSK(REG) -> 0xFFFFFFFF
* @endcode
* HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
* HWIO_SHFT: The right-shift value for accessing a field in a register. For example:
* @code
* HWIO_SHFT(REG, FLD) -> 8
* @endcode
* HWIO_FMSK: The mask value for accessing a field in a register. For example:
* @code
* HWIO_FMSK(REG, FLD) -> 0xFF00
* @endcode
* HWIO_VAL: The value for a field in a register. For example:
* @code
* HWIO_VAL(REG, FLD, ON) -> 0x1
* @endcode
* HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
* the given field position. For example:
* @code
* HWIO_FVAL(REG, FLD, 0x1) -> 0x100
* @endcode
* HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
* into the given field position. For example:
* @code
* HWIO_FVALV(REG, FLD, ON) -> 0x100
* @endcode
*
* @{
*/
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
/** @} */
/**
* @name Shadow Register Macros
*
* These macros are used for directly reading the value stored in a
* shadow register.
* Shadow registers are defined for write-only registers. Generally these
* macros should not be necessary as HWIO_OUTM* macros will automatically use
* the shadow values internally.
*
* @{
*/
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
/** @} */
/**
@}
*/ /* end_group */
/** @cond */
/*
* Map to final symbols. This remapping is done to allow register
* redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
* then remappings like "#define xreg xregnew" do not work as expected.
*/
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
}
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
}
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
}
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
/*
* HWIO_INTLOCK
*
* Macro used by autogenerated code for mutual exclusion around
* read-mask-write operations. This is not supported in HAL
* code but can be overridden by non-HAL code.
*/
#define HWIO_INTLOCK()
#define HWIO_INTFREE()
/*
* Input/output port macros for memory mapped IO.
*/
#define __inp(port) (*((volatile uint8 *) (port)))
#define __inpw(port) (*((volatile uint16 *) (port)))
#define __inpdw(port) (*((volatile uint32 *) (port)))
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
#ifdef HAL_HWIO_EXTERNAL
/*
* Replace macros with externally supplied functions.
*/
#undef __inp
#undef __inpw
#undef __inpdw
#undef __outp
#undef __outpw
#undef __outpdw
#define __inp(port) __inp_extern(port)
#define __inpw(port) __inpw_extern(port)
#define __inpdw(port) __inpdw_extern(port)
#define __outp(port, val) __outp_extern(port, val)
#define __outpw(port, val) __outpw_extern(port, val)
#define __outpdw(port, val) __outpdw_extern(port, val)
extern uint8 __inp_extern ( uint32 nAddr );
extern uint16 __inpw_extern ( uint32 nAddr );
extern uint32 __inpdw_extern ( uint32 nAddr );
extern void __outp_extern ( uint32 nAddr, uint8 nData );
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
#endif /* HAL_HWIO_EXTERNAL */
/*
* Base 8-bit byte accessing macros.
*/
#define in_byte(addr) (__inp(addr))
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
#define out_byte(addr, val) __outp(addr,val)
#define out_byte_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
out_byte( io, shadow); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
HWIO_INTFREE()
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 16-bit word accessing macros.
*/
#define in_word(addr) (__inpw(addr))
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
#define out_word(addr, val) __outpw(addr,val)
#define out_word_masked(io, mask, val, shadow) \
HWIO_INTLOCK( ); \
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
out_word( io, shadow); \
HWIO_INTFREE( )
#define out_word_masked_ns(io, mask, val, current_reg_content) \
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
((uint16)((val) & (mask)))) )
/*
* Base 32-bit double-word accessing macros.
*/
#define in_dword(addr) (__inpdw(addr))
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
#define out_dword(addr, val) __outpdw(addr,val)
#define out_dword_masked(io, mask, val, shadow) \
HWIO_INTLOCK(); \
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
out_dword( io, shadow); \
HWIO_INTFREE()
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
((uint32)((val) & (mask)))) )
/** @endcond */
#endif /* HAL_HWIO_H */

283
hw/qca8074/v1/buffer_addr_info.h Normal file
View file

@ -0,0 +1,283 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _BUFFER_ADDR_INFO_H_
#define _BUFFER_ADDR_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 buffer_addr_31_0[31:0]
// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
struct buffer_addr_info {
uint32_t buffer_addr_31_0 : 32; //[31:0]
uint32_t buffer_addr_39_32 : 8, //[7:0]
return_buffer_manager : 3, //[10:8]
sw_buffer_cookie : 21; //[31:11]
};
/*
buffer_addr_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
buffer_addr_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
return_buffer_manager
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<legal 0-6>
sw_buffer_cookie
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE:
The two most significant bits can have a special meaning
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
and field transmit_bw_restriction is set
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
<legal all>
*/
/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
Address (lower 32 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
Address (upper 8 bits) of the MSDU buffer OR
MSDU_EXTENSION descriptor OR Link Descriptor
In case of 'NULL' pointer, this field is set to 0
<legal all>
*/
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
Consumer: WBM
Producer: SW/FW
In case of 'NULL' pointer, this field is set to 0
Indicates to which buffer manager the buffer OR
MSDU_EXTENSION descriptor OR link descriptor that is being
pointed to shall be returned after the frame has been
processed. It is used by WBM for routing purposes.
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
to the WMB buffer idle list
<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
returned to the WMB idle link descriptor idle list
<enum 2 FW_BM> This buffer shall be returned to the FW
<enum 3 SW0_BM> This buffer shall be returned to the SW,
ring 0
<enum 4 SW1_BM> This buffer shall be returned to the SW,
ring 1
<enum 5 SW2_BM> This buffer shall be returned to the SW,
ring 2
<enum 6 SW3_BM> This buffer shall be returned to the SW,
ring 3
<legal 0-6>
*/
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700
/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
Cookie field exclusively used by SW.
In case of 'NULL' pointer, this field is set to 0
HW ignores the contents, accept that it passes the
programmed value on to other descriptors together with the
physical address
Field can be used by SW to for example associate the
buffers physical address with the virtual address
The bit definitions as used by SW are within SW HLD
specification
NOTE:
The two most significant bits can have a special meaning
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
and field transmit_bw_restriction is set
Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
<legal all>
*/
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800
#endif // _BUFFER_ADDR_INFO_H_

360
hw/qca8074/v1/ce_src_desc.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _CE_SRC_DESC_H_
#define _CE_SRC_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 src_buffer_low[31:0]
// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
// 2 fw_metadata[15:0], ce_res_1[31:16]
// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_SRC_DESC 4
struct ce_src_desc {
uint32_t src_buffer_low : 32; //[31:0]
uint32_t src_buffer_high : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_0 : 4, //[15:12]
length : 16; //[31:16]
uint32_t fw_metadata : 16, //[15:0]
ce_res_1 : 16; //[31:16]
uint32_t ce_res_2 : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
src_buffer_low
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
src_buffer_high
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
toeplitz_en
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
src_swap
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
dest_swap
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
gather
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
ce_res_0
Reserved
<legal all>
length
Length of the buffer in units of octets of the current
descriptor
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_1
Reserved
<legal all>
ce_res_2
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW
LSB 32 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff
/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH
MSB 8 bits of the 40 Bit Pointer to the source buffer
<legal all>
*/
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff
/* Description CE_SRC_DESC_1_TOEPLITZ_EN
Enable generation of 32-bit Toeplitz-LFSR hash for the
data transfer
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_SRC_DESC_1_SRC_SWAP
Treats source memory organization as big-endian. For
each dword read (4 bytes), the byte 0 is swapped with byte 3
and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200
/* Description CE_SRC_DESC_1_DEST_SWAP
Treats destination memory organization as big-endian.
For each dword write (4 bytes), the byte 0 is swapped with
byte 3 and byte 1 is swapped with byte 2.
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400
/* Description CE_SRC_DESC_1_GATHER
Enables gather of multiple copy engine source
descriptors to one destination.
<legal all>
*/
#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
#define CE_SRC_DESC_1_GATHER_LSB 11
#define CE_SRC_DESC_1_GATHER_MASK 0x00000800
/* Description CE_SRC_DESC_1_CE_RES_0
Reserved
<legal all>
*/
#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
#define CE_SRC_DESC_1_CE_RES_0_LSB 12
#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000
/* Description CE_SRC_DESC_1_LENGTH
Length of the buffer in units of octets of the current
descriptor
<legal all>
*/
#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
#define CE_SRC_DESC_1_LENGTH_LSB 16
#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000
/* Description CE_SRC_DESC_2_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
#define CE_SRC_DESC_2_FW_METADATA_LSB 0
#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff
/* Description CE_SRC_DESC_2_CE_RES_1
Reserved
<legal all>
*/
#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
#define CE_SRC_DESC_2_CE_RES_1_LSB 16
#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000
/* Description CE_SRC_DESC_3_CE_RES_2
Reserved
<legal all>
*/
#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
#define CE_SRC_DESC_3_CE_RES_2_LSB 0
#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff
/* Description CE_SRC_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_SRC_DESC_3_RING_ID_LSB 20
#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_SRC_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_SRC_DESC_H_

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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _CE_STAT_DESC_H_
#define _CE_STAT_DESC_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
// 1 toeplitz_hash_0[31:0]
// 2 toeplitz_hash_1[31:0]
// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_CE_STAT_DESC 4
struct ce_stat_desc {
uint32_t ce_res_5 : 8, //[7:0]
toeplitz_en : 1, //[8]
src_swap : 1, //[9]
dest_swap : 1, //[10]
gather : 1, //[11]
ce_res_6 : 4, //[15:12]
length : 16; //[31:16]
uint32_t toeplitz_hash_0 : 32; //[31:0]
uint32_t toeplitz_hash_1 : 32; //[31:0]
uint32_t fw_metadata : 16, //[15:0]
ce_res_7 : 4, //[19:16]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
ce_res_5
Reserved
<legal all>
toeplitz_en
<legal all>
src_swap
Source memory buffer swapped
<legal all>
dest_swap
Destination memory buffer swapped
<legal all>
gather
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
ce_res_6
Reserved
<legal all>
length
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
toeplitz_hash_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
toeplitz_hash_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
fw_metadata
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
ce_res_7
Reserved
<legal all>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
/* Description CE_STAT_DESC_0_CE_RES_5
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_5_LSB 0
#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff
/* Description CE_STAT_DESC_0_TOEPLITZ_EN
<legal all>
*/
#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000
#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8
#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100
/* Description CE_STAT_DESC_0_SRC_SWAP
Source memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_SRC_SWAP_LSB 9
#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200
/* Description CE_STAT_DESC_0_DEST_SWAP
Destination memory buffer swapped
<legal all>
*/
#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000
#define CE_STAT_DESC_0_DEST_SWAP_LSB 10
#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400
/* Description CE_STAT_DESC_0_GATHER
Gather of multiple copy engine source descriptors to one
destination enabled
<legal all>
*/
#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000
#define CE_STAT_DESC_0_GATHER_LSB 11
#define CE_STAT_DESC_0_GATHER_MASK 0x00000800
/* Description CE_STAT_DESC_0_CE_RES_6
Reserved
<legal all>
*/
#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000
#define CE_STAT_DESC_0_CE_RES_6_LSB 12
#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000
/* Description CE_STAT_DESC_0_LENGTH
Sum of all the Lengths of the source descriptor in the
gather chain
<legal all>
*/
#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000
#define CE_STAT_DESC_0_LENGTH_LSB 16
#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000
/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0
32 LS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0
#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff
/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1
32 MS bits of 64 bit Toeplitz LFSR hash result
<legal all>
*/
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0
#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff
/* Description CE_STAT_DESC_3_FW_METADATA
Meta data used by FW
In case of gather field in first source ring entry of
the gather copy cycle in taken into account.
<legal all>
*/
#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c
#define CE_STAT_DESC_3_FW_METADATA_LSB 0
#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff
/* Description CE_STAT_DESC_3_CE_RES_7
Reserved
<legal all>
*/
#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c
#define CE_STAT_DESC_3_CE_RES_7_LSB 16
#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000
/* Description CE_STAT_DESC_3_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c
#define CE_STAT_DESC_3_RING_ID_LSB 20
#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000
/* Description CE_STAT_DESC_3_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into the Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28
#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000
#endif // _CE_STAT_DESC_H_

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hw/qca8074/v1/com_dtypes.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef COM_DTYPES_H
#define COM_DTYPES_H
/**
@file com_dtypes.h
@brief This header file contains general data types that are of use to all
modules.
*/
/*===========================================================================
NOTE: The @brief description and any detailed descriptions above do not appear
in the PDF.
The Utility_Services_API_mainpage.dox file contains all file/group
descriptions that are in the output PDF generated using Doxygen and
Latex. To edit or update any of the file/group text in the PDF, edit
the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
The above description for this file is part of the "utils_services"
group description in the Utility_Services_API_mainpage.dox file.
===========================================================================*/
/*===========================================================================
S T A N D A R D D E C L A R A T I O N S
DESCRIPTION
This header file contains general data types that are of use to all modules.
The values or definitions are dependent on the specified
target. T_WINNT specifies Windows NT based targets, otherwise the
default is for ARM targets.
T_WINNT Software is hosted on an NT platforn, triggers macro and
type definitions, unlike definition above which triggers
actual OS calls
===========================================================================*/
/*===========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $
when who what, where, why
-------- --- ----------------------------------------------------------
03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup.
11/09/10 EBR Doxygenated file.
09/15/09 pc Created file.
===========================================================================*/
/*===========================================================================
Data Declarations
===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
/* For NT apps we want to use the Win32 definitions and/or those
supplied by the Win32 compiler for things like NULL, MAX, MIN
abs, labs, etc.
*/
#ifdef T_WINNT
#ifndef WIN32
#define WIN32
#endif
#include <stdlib.h>
#endif
/* ------------------------------------------------------------------------
** Constants
** ------------------------------------------------------------------------ */
#ifdef TRUE
#undef TRUE
#endif
#ifdef FALSE
#undef FALSE
#endif
/** @addtogroup utils_services
@{ */
/** @name Macros for Common Data Types
@{ */
#define TRUE 1 /**< Boolean TRUE value. */
#define FALSE 0 /**< Boolean FALSE value. */
#define ON 1 /**< ON value. */
#define OFF 0 /**< OFF value. */
#ifndef NULL
#define NULL 0 /**< NULL value. */
#endif
/** @} */ /* end_name_group Macros for Common Data Types */
/* -----------------------------------------------------------------------
** Standard Types
** ----------------------------------------------------------------------- */
/** @} */ /* end_addtogroup utils_services */
/* The following definitions are the same across platforms. This first
group are the sanctioned types.
*/
#ifndef _ARM_ASM_
#ifndef _BOOLEAN_DEFINED
/** @addtogroup utils_services
@{ */
/** Boolean value type.
*/
typedef unsigned char boolean;
#define _BOOLEAN_DEFINED
#endif
/** @cond
*/
#if defined(DALSTDDEF_H) /* guards against a known re-definer */
#define _BOOLEAN_DEFINED
#define _UINT32_DEFINED
#define _UINT16_DEFINED
#define _UINT8_DEFINED
#define _INT32_DEFINED
#define _INT16_DEFINED
#define _INT8_DEFINED
#define _UINT64_DEFINED
#define _INT64_DEFINED
#define _BYTE_DEFINED
#endif /* #if !defined(DALSTDDEF_H) */
/** @endcond */
#ifndef _UINT32_DEFINED
/** Unsigned 32-bit value.
*/
typedef unsigned long int uint32;
#define _UINT32_DEFINED
#endif
#ifndef _UINT16_DEFINED
/** Unsigned 16-bit value.
*/
typedef unsigned short uint16;
#define _UINT16_DEFINED
#endif
#ifndef _UINT8_DEFINED
/** Unsigned 8-bit value.
*/
typedef unsigned char uint8;
#define _UINT8_DEFINED
#endif
#ifndef _INT32_DEFINED
/** Signed 32-bit value.
*/
typedef signed long int int32;
#define _INT32_DEFINED
#endif
#ifndef _INT16_DEFINED
/** Signed 16-bit value.
*/
typedef signed short int16;
#define _INT16_DEFINED
#endif
#ifndef _INT8_DEFINED
/** Signed 8-bit value.
*/
typedef signed char int8;
#define _INT8_DEFINED
#endif
/** @cond
*/
/* This group are the deprecated types. Their use should be
** discontinued and new code should use the types above
*/
#ifndef _BYTE_DEFINED
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char byte;
#define _BYTE_DEFINED
#endif
/** DEPRECATED: Unsinged 16 bit value type.
*/
typedef unsigned short word;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long dword;
/** DEPRECATED: Unsigned 8 bit value type.
*/
typedef unsigned char uint1;
/** DEPRECATED: Unsigned 16 bit value type.
*/
typedef unsigned short uint2;
/** DEPRECATED: Unsigned 32 bit value type.
*/
typedef unsigned long uint4;
/** DEPRECATED: Signed 8 bit value type.
*/
typedef signed char int1;
/** DEPRECATED: Signed 16 bit value type.
*/
typedef signed short int2;
/** DEPRECATED: Signed 32 bit value type.
*/
typedef long int int4;
/** DEPRECATED: Signed 32 bit value.
*/
typedef signed long sint31;
/** DEPRECATED: Signed 16 bit value.
*/
typedef signed short sint15;
/** DEPRECATED: Signed 8 bit value.
*/
typedef signed char sint7;
typedef uint16 UWord16 ;
typedef uint32 UWord32 ;
typedef int32 Word32 ;
typedef int16 Word16 ;
typedef uint8 UWord8 ;
typedef int8 Word8 ;
typedef int32 Vect32 ;
/** @endcond */
#if (! defined T_WINNT) && (! defined __GNUC__)
/* Non WinNT Targets */
#ifndef _INT64_DEFINED
/** Signed 64-bit value.
*/
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
/** Unsigned 64-bit value.
*/
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
/* WINNT or SOLARIS based targets */
#if (defined __GNUC__)
#ifndef _INT64_DEFINED
typedef long long int64;
#define _INT64_DEFINED
#endif
#ifndef _UINT64_DEFINED
typedef unsigned long long uint64;
#define _UINT64_DEFINED
#endif
#else
typedef __int64 int64; /* Signed 64-bit value */
#ifndef _UINT64_DEFINED
typedef unsigned __int64 uint64; /* Unsigned 64-bit value */
#define _UINT64_DEFINED
#endif
#endif
#endif /* T_WINNT */
#endif /* _ARM_ASM_ */
#ifdef __cplusplus
}
#endif
/** @} */ /* end_addtogroup utils_services */
#endif /* COM_DTYPES_H */

38
hw/qca8074/v1/lithium_top_reg.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
//////////////////////////////////////////////////////////////////////////////
// lithium_top_reg.h generated by: GenArmCHeader.pl
//////////////////////////////////////////////////////////////////////////////
// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
//////////////////////////////////////////////////////////////////////////////
// RCS File : -USE CVS LOG-
// Revision : -USE CVS LOG-
// Last Check In : -USE CVS LOG-
//////////////////////////////////////////////////////////////////////////////
// Description : Constants related to Hardware Registers
//
// Byte Addresses are used for all BASES and ADDRESSES
//////////////////////////////////////////////////////////////////////////////
#ifndef LITHIUM_TOP_REG_H
#define LITHIUM_TOP_REG_H
#define UMAC_CE_COMMON_CE_HOST_IE_0 (0x00A18034)
#define UMAC_CE_COMMON_CE_HOST_IE_1 (0x00A18038)
#endif

39
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.3 7/29/2016
// User Name:pgohil
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __MAC_TCL_REG_SEQ_BASE_H__
#define __MAC_TCL_REG_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "HALhwio.h"
#else
#include "msmhwio.h"
#endif
#endif

6821
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51
hw/qca8074/v1/msmhwio.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef MSMHWIO_H
#define MSMHWIO_H
/*
===========================================================================
*/
/**
@file msmhwio.h
Deprecated public interface include file for accessing the HWIO macro
definitions.
The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO)
register access definitions. See HALhwio.h and DDIHWIO.h for the new
interfaces.
*/
/*
====================================================================
$Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $
====================================================================
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Include main HWIO macros.
*/
#include "HALhwio.h"
#endif /* MSMHWIO_H */

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hw/qca8074/v1/reo_destination_ring.h Normal file
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/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_DESTINATION_RING_H_
#define _REO_DESTINATION_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "buffer_addr_info.h"
#include "rx_mpdu_desc_info.h"
#include "rx_msdu_desc_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info;
// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details;
// 6 rx_reo_queue_desc_addr_31_0[31:0]
// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
struct reo_destination_ring {
struct buffer_addr_info buf_or_link_desc_addr_info;
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
struct rx_msdu_desc_info rx_msdu_desc_info_details;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
reo_dest_buffer_type : 1, //[8]
reo_push_reason : 2, //[10:9]
reo_error_code : 5, //[15:11]
receive_queue_number : 16; //[31:16]
uint32_t soft_reorder_info_valid : 1, //[0]
reorder_opcode : 4, //[4:1]
reorder_slot_index : 8, //[12:5]
reserved_8a : 19; //[31:13]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15 : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
struct buffer_addr_info buf_or_link_desc_addr_info
Consumer: REO/SW/FW
Producer: RXDMA
Details of the physical address of the a buffer or MSDU
link descriptor
struct rx_mpdu_desc_info rx_mpdu_desc_info_details
Consumer: REO/SW/FW
Producer: RXDMA
General information related to the MPDU that is passed
on from REO entrance ring to the REO destination ring
struct rx_msdu_desc_info rx_msdu_desc_info_details
General information related to the MSDU that is passed
on from RXDMA all the way to to the REO destination ring.
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
reo_dest_buffer_type
Indicates the type of address provided in the
'Buf_or_link_desc_addr_info'
<enum 0 MSDU_buf_address> The address of an MSDU buffer
<enum 1 MSDU_link_desc_address> The address of the MSDU
link descriptor.
<legal all>
reo_push_reason
Indicates why REO pushed the frame to this exit ring
<enum 0 reo_error_detected> Reo detected an error an
pushed this frame to this queue
<enum 1 reo_routing_instruction> Reo pushed the frame to
this queue per received routing instructions. No error
within REO was detected
<legal 0 - 1>
reo_error_code
Field only valid when 'Reo_push_reason' set to
'reo_error_detected'.
<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
provided in the REO_ENTRANCE ring is set to 0
<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
valid bit is NOT set
<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
session having been setup.
<enum 3 non_ba_duplicate> Non-BA session, SN equal to
SSN, Retry bit set: duplicate frame
<enum 4 ba_duplicate> BA session, duplicate frame
<enum 5 regular_frame_2k_jump> A normal (management/data
frame) received with 2K jump in SN
<enum 6 bar_frame_2k_jump> A bar received with 2K jump
in SSN
<enum 7 regular_frame_OOR> A normal (management/data
frame) received with SN falling within the OOR window
<enum 8 bar_frame_OOR> A bar received with SSN falling
within the OOR window
<enum 9 bar_frame_no_ba_session> A bar received without
a BA session
<enum 10 bar_frame_sn_equals_ssn> A bar received with
SSN equal to SN
<enum 11 pn_check_failed> PN Check Failed packet.
<enum 12 2k_error_handling_flag_set> Frame is forwarded
as a result of the 'Seq_2k_error_detected_flag' been set in
the REO Queue descriptor
<enum 13 pn_error_handling_flag_set> Frame is forwarded
as a result of the 'pn_error_detected_flag' been set in the
REO Queue descriptor
<enum 14 queue_descriptor_blocked_set> Frame is
forwarded as a result of the queue descriptor(address) being
blocked as SW/FW seems to be currently in the process of
making updates to this descriptor...
<legal 0-14>
receive_queue_number
This field indicates the REO MPDU reorder queue ID from
which this frame originated. This field is populated from a
field with the same name in the RX_REO_QUEUE descriptor.
<legal all>
soft_reorder_info_valid
When set, REO has been instructed to not perform the
actual re-ordering of frames for this queue, but just to
insert the reorder opcodes
<legal all>
reorder_opcode
Field is valid when 'Soft_reorder_info_valid' is set.
This field is always valid for debug purpose as well.
Details are in the MLD.
<enum 0 invalid>
<enum 1 fwdcur_fwdbuf>
<enum 2 fwdbuf_fwdcur>
<enum 3 qcur>
<enum 4 fwdbuf_qcur>
<enum 5 fwdbuf_drop>
<enum 6 fwdall_drop>
<enum 7 fwdall_qcur>
<enum 8 reserved_reo_opcode_1>
<enum 9 dropcur> the error reason code is in
reo_error_code field.
<enum 10 reserved_reo_opcode_2>
<enum 11 reserved_reo_opcode_3>
<enum 12 reserved_reo_opcode_4>
<enum 13 reserved_reo_opcode_5>
<enum 14 reserved_reo_opcode_6>
<enum 15 reserved_reo_opcode_7>
<legal all>
reorder_slot_index
Field only valid when 'Soft_reorder_info_valid' is set.
TODO: add description
<legal all>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15
<legal 0>
ring_id
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE
Indicates the type of address provided in the
'Buf_or_link_desc_addr_info'
<enum 0 MSDU_buf_address> The address of an MSDU buffer
<enum 1 MSDU_link_desc_address> The address of the MSDU
link descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8
#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100
/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON
Indicates why REO pushed the frame to this exit ring
<enum 0 reo_error_detected> Reo detected an error an
pushed this frame to this queue
<enum 1 reo_routing_instruction> Reo pushed the frame to
this queue per received routing instructions. No error
within REO was detected
<legal 0 - 1>
*/
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9
#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600
/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE
Field only valid when 'Reo_push_reason' set to
'reo_error_detected'.
<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
provided in the REO_ENTRANCE ring is set to 0
<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
valid bit is NOT set
<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
session having been setup.
<enum 3 non_ba_duplicate> Non-BA session, SN equal to
SSN, Retry bit set: duplicate frame
<enum 4 ba_duplicate> BA session, duplicate frame
<enum 5 regular_frame_2k_jump> A normal (management/data
frame) received with 2K jump in SN
<enum 6 bar_frame_2k_jump> A bar received with 2K jump
in SSN
<enum 7 regular_frame_OOR> A normal (management/data
frame) received with SN falling within the OOR window
<enum 8 bar_frame_OOR> A bar received with SSN falling
within the OOR window
<enum 9 bar_frame_no_ba_session> A bar received without
a BA session
<enum 10 bar_frame_sn_equals_ssn> A bar received with
SSN equal to SN
<enum 11 pn_check_failed> PN Check Failed packet.
<enum 12 2k_error_handling_flag_set> Frame is forwarded
as a result of the 'Seq_2k_error_detected_flag' been set in
the REO Queue descriptor
<enum 13 pn_error_handling_flag_set> Frame is forwarded
as a result of the 'pn_error_detected_flag' been set in the
REO Queue descriptor
<enum 14 queue_descriptor_blocked_set> Frame is
forwarded as a result of the queue descriptor(address) being
blocked as SW/FW seems to be currently in the process of
making updates to this descriptor...
<legal 0-14>
*/
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11
#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800
/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
This field indicates the REO MPDU reorder queue ID from
which this frame originated. This field is populated from a
field with the same name in the RX_REO_QUEUE descriptor.
<legal all>
*/
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16
#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000
/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
When set, REO has been instructed to not perform the
actual re-ordering of frames for this queue, but just to
insert the reorder opcodes
<legal all>
*/
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0
#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001
/* Description REO_DESTINATION_RING_8_REORDER_OPCODE
Field is valid when 'Soft_reorder_info_valid' is set.
This field is always valid for debug purpose as well.
Details are in the MLD.
<enum 0 invalid>
<enum 1 fwdcur_fwdbuf>
<enum 2 fwdbuf_fwdcur>
<enum 3 qcur>
<enum 4 fwdbuf_qcur>
<enum 5 fwdbuf_drop>
<enum 6 fwdall_drop>
<enum 7 fwdall_qcur>
<enum 8 reserved_reo_opcode_1>
<enum 9 dropcur> the error reason code is in
reo_error_code field.
<enum 10 reserved_reo_opcode_2>
<enum 11 reserved_reo_opcode_3>
<enum 12 reserved_reo_opcode_4>
<enum 13 reserved_reo_opcode_5>
<enum 14 reserved_reo_opcode_6>
<enum 15 reserved_reo_opcode_7>
<legal all>
*/
#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1
#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e
/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX
Field only valid when 'Soft_reorder_info_valid' is set.
TODO: add description
<legal all>
*/
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5
#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0
/* Description REO_DESTINATION_RING_8_RESERVED_8A
<legal 0>
*/
#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020
#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13
#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000
/* Description REO_DESTINATION_RING_9_RESERVED_9A
<legal 0>
*/
#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024
#define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0
#define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_10_RESERVED_10A
<legal 0>
*/
#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028
#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0
#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_11_RESERVED_11A
<legal 0>
*/
#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0
#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_12_RESERVED_12A
<legal 0>
*/
#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030
#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0
#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_13_RESERVED_13A
<legal 0>
*/
#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034
#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0
#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_14_RESERVED_14A
<legal 0>
*/
#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038
#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0
#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_DESTINATION_RING_15_RESERVED_15
<legal 0>
*/
#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0
#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff
/* Description REO_DESTINATION_RING_15_RING_ID
The buffer pointer ring ID.
0 refers to the IDLE ring
1 - N refers to other rings
Helps with debugging when dumping ring contents.
<legal all>
*/
#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_RING_ID_LSB 20
#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000
/* Description REO_DESTINATION_RING_15_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c
#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28
#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_DESTINATION_RING_H_

722
hw/qca8074/v1/reo_entrance_ring.h Normal file
View file

@ -0,0 +1,722 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// $ATH_LICENSE_HW_HDR_C$
//
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_ENTRANCE_RING_H_
#define _REO_ENTRANCE_RING_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_mpdu_details.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info;
// 4 rx_reo_queue_desc_addr_31_0[31:0]
// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7]
// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
struct reo_entrance_ring {
struct rx_mpdu_details reo_level_mpdu_frame_info;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
rounded_mpdu_byte_count : 14, //[21:8]
reo_destination_indication : 5, //[26:22]
frameless_bar : 1, //[27]
reserved_5a : 4; //[31:28]
uint32_t rxdma_push_reason : 2, //[1:0]
rxdma_error_code : 5, //[6:2]
reserved_6a : 25; //[31:7]
uint32_t reserved_7a : 20, //[19:0]
ring_id : 8, //[27:20]
looping_count : 4; //[31:28]
};
/*
struct rx_mpdu_details reo_level_mpdu_frame_info
Consumer: REO
Producer: RXDMA
Details related to the MPDU being pushed into the REO
rx_reo_queue_desc_addr_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
rx_reo_queue_desc_addr_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
rounded_mpdu_byte_count
An approximation of the number of bytes received in this
MPDU.
Used to keeps stats on the amount of data flowing
through a queue.
<legal all>
reo_destination_indication
RXDMA copy the MPDU's first MSDU's destination
indication field here. This is used for REO to be able to
re-route the packet to a different SW destination ring if
the packet is detected as error in REO.
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
frameless_bar
When set, this REO entrance ring struct contains BAR
info from a multi TID BAR frame. The original multi TID BAR
frame itself contained all the REO info for the first TID,
but all the subsequent TID info and their linkage to the REO
descriptors is passed down as 'frameless' BAR info.
The only fields valid in this descriptor when this bit
is set are:
Rx_reo_queue_desc_addr_31_0
RX_reo_queue_desc_addr_39_32
And within the
Reo_level_mpdu_frame_info:
Within Rx_mpdu_desc_info_details:
Mpdu_Sequence_number
BAR_frame
Peer_meta_data
All other fields shall be set to 0
<legal all>
reserved_5a
<legal 0>
rxdma_push_reason
Indicates why rxdma pushed the frame to this ring
<enum 0 rxdma_error_detected> RXDMA detected an error an
pushed this frame to this queue
<enum 1 rxdma_routing_instruction> RXDMA pushed the
frame to this queue per received routing instructions. No
error within RXDMA was detected
This field is ignored by REO.
<legal 0 - 1>
rxdma_error_code
Field only valid when 'rxdma_push_reason' set to
'rxdma_error_detected'.
This field is ignored by REO.
<enum 0 rxdma_overflow_err>MPDU frame is not complete
due to a FIFO overflow error in RXPCU.
<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
due to receiving incomplete MPDU from the PHY
<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
error
<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
error
<enum 5 rxdma_unecrypted_err>CRYPTO reported an
unencrypted frame error when encrypted was expected
<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
length error
<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
number of MSDUs allowed in an MPDU got exceeded
<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
error
<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
parsing error
<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
during SA search
<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
during DA search
<enum 12 rxdma_flow_timeout_err>RX OLE reported a
timeout during flow search
<enum 13 Rxdma_flush_request>RXDMA received a flush
request
reserved_6a
<legal 0>
reserved_7a
<legal 0>
ring_id
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
It help to identify the ring that is being looked <legal
all>
looping_count
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
Consumer: REO
Producer: RXDMA
Address (lower 32 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
Consumer: REO
Producer: RXDMA
Address (upper 8 bits) of the REO queue descriptor.
<legal all>
*/
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
An approximation of the number of bytes received in this
MPDU.
Used to keeps stats on the amount of data flowing
through a queue.
<legal all>
*/
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
RXDMA copy the MPDU's first MSDU's destination
indication field here. This is used for REO to be able to
re-route the packet to a different SW destination ring if
the packet is detected as error in REO.
The ID of the REO exit ring where the MSDU frame shall
push after (MPDU level) reordering has finished.
<enum 0 reo_destination_tcl> Reo will push the frame
into the REO2TCL ring
<enum 1 reo_destination_sw1> Reo will push the frame
into the REO2SW1 ring
<enum 2 reo_destination_sw2> Reo will push the frame
into the REO2SW1 ring
<enum 3 reo_destination_sw3> Reo will push the frame
into the REO2SW1 ring
<enum 4 reo_destination_sw4> Reo will push the frame
into the REO2SW1 ring
<enum 5 reo_destination_release> Reo will push the frame
into the REO_release ring
<enum 6 reo_destination_fw> Reo will push the frame into
the REO2FW ring
<enum 7 reo_destination_7> REO remaps this
<enum 8 reo_destination_8> REO remaps this <enum 9
reo_destination_9> REO remaps this <enum 10
reo_destination_10> REO remaps this
<enum 11 reo_destination_11> REO remaps this
<enum 12 reo_destination_12> REO remaps this <enum 13
reo_destination_13> REO remaps this
<enum 14 reo_destination_14> REO remaps this
<enum 15 reo_destination_15> REO remaps this
<enum 16 reo_destination_16> REO remaps this
<enum 17 reo_destination_17> REO remaps this
<enum 18 reo_destination_18> REO remaps this
<enum 19 reo_destination_19> REO remaps this
<enum 20 reo_destination_20> REO remaps this
<enum 21 reo_destination_21> REO remaps this
<enum 22 reo_destination_22> REO remaps this
<enum 23 reo_destination_23> REO remaps this
<enum 24 reo_destination_24> REO remaps this
<enum 25 reo_destination_25> REO remaps this
<enum 26 reo_destination_26> REO remaps this
<enum 27 reo_destination_27> REO remaps this
<enum 28 reo_destination_28> REO remaps this
<enum 29 reo_destination_29> REO remaps this
<enum 30 reo_destination_30> REO remaps this
<enum 31 reo_destination_31> REO remaps this
<legal all>
*/
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR
When set, this REO entrance ring struct contains BAR
info from a multi TID BAR frame. The original multi TID BAR
frame itself contained all the REO info for the first TID,
but all the subsequent TID info and their linkage to the REO
descriptors is passed down as 'frameless' BAR info.
The only fields valid in this descriptor when this bit
is set are:
Rx_reo_queue_desc_addr_31_0
RX_reo_queue_desc_addr_39_32
And within the
Reo_level_mpdu_frame_info:
Within Rx_mpdu_desc_info_details:
Mpdu_Sequence_number
BAR_frame
Peer_meta_data
All other fields shall be set to 0
<legal all>
*/
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
/* Description REO_ENTRANCE_RING_5_RESERVED_5A
<legal 0>
*/
#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
Indicates why rxdma pushed the frame to this ring
<enum 0 rxdma_error_detected> RXDMA detected an error an
pushed this frame to this queue
<enum 1 rxdma_routing_instruction> RXDMA pushed the
frame to this queue per received routing instructions. No
error within RXDMA was detected
This field is ignored by REO.
<legal 0 - 1>
*/
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
Field only valid when 'rxdma_push_reason' set to
'rxdma_error_detected'.
This field is ignored by REO.
<enum 0 rxdma_overflow_err>MPDU frame is not complete
due to a FIFO overflow error in RXPCU.
<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
due to receiving incomplete MPDU from the PHY
<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
error
<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
error
<enum 5 rxdma_unecrypted_err>CRYPTO reported an
unencrypted frame error when encrypted was expected
<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
length error
<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
number of MSDUs allowed in an MPDU got exceeded
<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
error
<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
parsing error
<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
during SA search
<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
during DA search
<enum 12 rxdma_flow_timeout_err>RX OLE reported a
timeout during flow search
<enum 13 Rxdma_flush_request>RXDMA received a flush
request
*/
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
/* Description REO_ENTRANCE_RING_6_RESERVED_6A
<legal 0>
*/
#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 7
#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xffffff80
/* Description REO_ENTRANCE_RING_7_RESERVED_7A
<legal 0>
*/
#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0
#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff
/* Description REO_ENTRANCE_RING_7_RING_ID
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
It help to identify the ring that is being looked <legal
all>
*/
#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_RING_ID_LSB 20
#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT
Consumer: SW/REO/DEBUG
Producer: SRNG (of RXDMA)
For debugging.
This field is filled in by the SRNG module.
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_ENTRANCE_RING_H_

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