Merge "clk: avoid returning local variable pointers during clock registration"

This commit is contained in:
qctecmdr 2019-09-05 17:25:09 -07:00 • committed by Gerrit - the friendly Code Review server
commit 7d612332ab
8 changed files with 25 additions and 13 deletions

View file

@ -510,6 +510,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
/* register the clock */
hw = &div->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(div);
hw = ERR_PTR(ret);

View file

@ -98,6 +98,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
ret = clk_hw_register(dev, hw);
else
ret = of_clk_hw_register(np, hw);
hw->init = NULL;
if (ret) {
kfree(fix);
hw = ERR_PTR(ret);

View file

@ -80,6 +80,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
/* register the clock */
hw = &fixed->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(fixed);
hw = ERR_PTR(ret);

View file

@ -185,6 +185,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
hw = &fd->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(fd);
hw = ERR_PTR(ret);

View file

@ -171,6 +171,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
hw = &gate->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(gate);
hw = ERR_PTR(ret);

View file

@ -149,7 +149,7 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
err = devm_clk_hw_register(dev, hw);
else
err = clk_hw_register(NULL, hw);
hw->init = NULL;
if (!err)
return hw;

View file

@ -190,6 +190,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
hw = &mux->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(mux);
hw = ERR_PTR(ret);

View file

@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
@ -8,16 +8,22 @@
/* RPMh controlled clocks */
#define RPMH_CXO_CLK 0
#define RPMH_CXO_CLK_A 1
#define RPMH_LN_BB_CLK2 2
#define RPMH_LN_BB_CLK2_A 3
#define RPMH_LN_BB_CLK3 4
#define RPMH_LN_BB_CLK3_A 5
#define RPMH_RF_CLK1 6
#define RPMH_RF_CLK1_A 7
#define RPMH_RF_CLK2 8
#define RPMH_RF_CLK2_A 9
#define RPMH_RF_CLK3 10
#define RPMH_RF_CLK3_A 11
#define RPMH_IPA_CLK 12
#define RPMH_LN_BB_CLK1 2
#define RPMH_LN_BB_CLK1_A 3
#define RPMH_LN_BB_CLK2 4
#define RPMH_LN_BB_CLK2_A 5
#define RPMH_LN_BB_CLK3 6
#define RPMH_LN_BB_CLK3_A 7
#define RPMH_RF_CLK1 8
#define RPMH_RF_CLK1_A 9
#define RPMH_RF_CLK2 10
#define RPMH_RF_CLK2_A 11
#define RPMH_RF_CLK3 12
#define RPMH_RF_CLK3_A 13
#define RPMH_RF_CLKD3 14
#define RPMH_RF_CLKD3_A 15
#define RPMH_RF_CLKD4 16
#define RPMH_RF_CLKD4_A 17
#define RPMH_IPA_CLK 18
#endif