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dsi_phy_v3.0: Get strength offset from dtsi file and set

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The clock and data lanes have a calibration circuitry feature. To offset the drive
strength from the calibrated value in an increasing or decreasing manner, use 6 bit two’s
complement values.

Change-Id: I1cb612b4f62ea6af07165ffd1fb8e15528200e5e
Signed-off-by: houdz1 <houdz1@lenovo.com>
Reviewed-on: https://gerrit.mot.com/1850370
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Yeqing Wang <wangyq13@motorola.com>
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
houdz1 2021-01-13 16:24:50 +08:00 • committed by tongkun1
commit 83d72184f0
2 changed files with 3 additions and 3 deletions
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2
msm/dsi/dsi_phy.c
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@ -63,7 +63,7 @@ static const struct dsi_ver_spec_info dsi_phy_v2_0 = {
static const struct dsi_ver_spec_info dsi_phy_v3_0 = {
.version = DSI_PHY_VERSION_3_0,
.lane_cfg_count = 4,
.strength_cfg_count = 2,
.strength_cfg_count = 4,
.regulator_cfg_count = 0,
.timing_cfg_count = 12,
};

4
msm/dsi/dsi_phy_hw_v3_0.c
View file

@ -194,8 +194,8 @@ static void dsi_phy_hw_v3_0_lane_settings(struct dsi_phy_hw *phy,
DSI_W32(phy, DSIPHY_LNX_CFG1(i), cfg->lanecfg.lane[i][1]);
DSI_W32(phy, DSIPHY_LNX_CFG2(i), cfg->lanecfg.lane[i][2]);
DSI_W32(phy, DSIPHY_LNX_CFG3(i), cfg->lanecfg.lane[i][3]);
DSI_W32(phy, DSIPHY_LNX_OFFSET_TOP_CTRL(i), 0x0);
DSI_W32(phy, DSIPHY_LNX_OFFSET_BOT_CTRL(i), 0x0);
DSI_W32(phy, DSIPHY_LNX_OFFSET_TOP_CTRL(i), cfg->strength.lane[i][2]);
DSI_W32(phy, DSIPHY_LNX_OFFSET_BOT_CTRL(i), cfg->strength.lane[i][3]);
DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]);
}
}