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Merge "ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL on lahaina"

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qctecmdr 2020-05-15 20:31:08 -07:00 • committed by Gerrit - the friendly Code Review server
commit b28d735669
1 changed files with 35 additions and 7 deletions
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42
qcom/lahaina-pcie.dtsi
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@ -109,7 +109,12 @@
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,pcie-phy-ver = <10921>;
qcom,phy-manage-pll = <1>;
qcom,phy-resetsm-cntrl2 = <0xa0>;
qcom,phy-core-pll-en-mux = <7>;
qcom,phy-c-ready-status = <0x178>;
qcom,pcie-phy-ver = <10971>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
@ -144,26 +149,49 @@
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