A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-11 07:03:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "dt-bindings: clock: Add support for YUPIK clock controllers"

Browse source
This commit is contained in:
qctecmdr 2020-11-19 06:55:47 -08:00 • committed by Gerrit - the friendly Code Review server
commit caeff04a66
6 changed files with 11 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

1
bindings/clock/qcom,camcc.txt
View file

@ -11,6 +11,7 @@ Required properties :
"qcom,sm8150-camcc-v2"
"qcom,sa8155-camcc"
"qcom,sa8155-camcc-v2"
"qcom,yupik-camcc"
- reg : shall contain base register location and length.
- reg-names: names of registers listed in the same order as in

1
bindings/clock/qcom,debugcc.txt
View file

@ -9,6 +9,7 @@ Required properties :
"qcom,holi-debugcc"
"qcom,sdxlemur-debugcc"
"qcom,sm8150-debugcc"
"qcom,yupik-debugcc"
- qcom,gcc: phandle to the GCC device node.
- qcom,videocc: phandle to the Video CC device node.

1
bindings/clock/qcom,dispcc.txt
View file

@ -11,6 +11,7 @@ Required properties :
"qcom,holi-dispcc"
"qcom,sm8150-dispcc"
"qcom,sm8150-dispcc-v2"
"qcom,yupik-dispcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.

1
bindings/clock/qcom,gcc.txt
View file

@ -31,6 +31,7 @@ Required properties :
"qcom,shima-gcc"
"qcom,holi-gcc"
"qcom,sdxlemur-gcc"
"qcom,yupik-gcc"
- reg : shall contain base register location and length
- vdd_cx-supply: The vdd_cx logic rail supply.

11
bindings/clock/qcom,gpucc.txt
View file

@ -3,11 +3,12 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
Required properties :
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
"qcom,lahaina-gpucc",
"qcom,shima-gpucc",
"qcom,holi-gpucc",
"qcom,sm8150-gpucc",
"qcom,sa8155-gpucc".
"qcom,lahaina-gpucc"
"qcom,shima-gpucc"
"qcom,holi-gpucc"
"qcom,sm8150-gpucc"
"qcom,sa8155-gpucc"
"qcom,yupik-gpucc"
- reg: shall contain base register offset and size.
- reg-names: names of registers listed in the same order as in the reg property.

1
bindings/clock/qcom,videocc.txt
View file

@ -11,6 +11,7 @@ Required properties :
"qcom,sm8150-videocc-v2"
"qcom,sa8155-videocc"
"qcom,sa8155-videocc-v2"
"qcom,yupik-videocc"
- reg : shall contain base register location and length
- #clock-cells : from common clock binding, shall contain 1.