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Merge "dt-bindings: input: add qpnp-power-on bindings"
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247
bindings/input/qpnp-power-on.txt
Normal file
247
bindings/input/qpnp-power-on.txt
Normal file
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@ -0,0 +1,247 @@
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Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral Device Tree Bindings
|
||||
|
||||
qpnp-power-on devices support the power-on (PON) peripheral found on
|
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Qualcomm Technologies, Inc. PMICs. The supported functionality includes power
|
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on/off reason, key press/release detection, PMIC reset configurations and other
|
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PON specific features. The PON module supports multiple physical power-on
|
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(KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This
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peripheral is connected to the host processor via the SPMI interface.
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Required properties:
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- compatible: Must be "qcom,qpnp-power-on"
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- reg: Specifies the SPMI base address for this PON
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(power-on) peripheral.
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Optional properties:
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- interrupts: Specifies the interrupts associated with PON.
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- interrupt-names: Specifies the interrupt names associated with
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the interrupts property. Must be a subset of
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"kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
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"cblpwr", "kpdpwr-resin-bark", and
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"pmic-wd-bark". Bark interrupts are associated
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with system reset configuration to allow default
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reset configuration to be activated. If system
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reset configuration is not supported then bark
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interrupts are nops. Additionally, the
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"pmic-wd-bark" interrupt can be added if the
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system needs to handle PMIC watchdog barks.
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- qcom,pon-dbc-delay: The debounce delay for the power-key interrupt
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specified in us.
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Possible values for GEN1 PON are:
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15625, 31250, 62500, 125000, 250000, 500000,
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1000000 and 2000000.
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Possible values for GEN2 PON are:
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62, 123, 245, 489, 977, 1954, 3907, 7813,
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15625, 31250, 62500, 125000 and 250000.
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Intermediate value is rounded down to the
|
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nearest valid value.
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- qcom,system-reset: Boolean which specifies that this PON peripheral
|
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can be used to reset the system. This property
|
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can only be used by one device on the system. It
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is an error to include it more than once.
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- qcom,modem-reset: Boolean which specifies that this PON peripheral
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can be used to reset the attached modem chip.
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This property can only be used by one PON device
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on the system. qcom,modem-reset and
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qcom,system-reset cannot be specified for the
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same PON device.
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- qcom,s3-debounce: The debounce delay for stage 3 reset trigger in
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secs. The values range from 0 to 128.
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- qcom,s3-src: The source for stage 3 reset. It can be one of
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"kpdpwr", "resin", "kpdpwr-or-resin" or
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"kpdpwr-and-resin".
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- qcom,uvlo-panic: Boolean indicating that the device should
|
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trigger a controlled panic shutdown if a restart
|
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was caused by under voltage lock-out (UVLO).
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- qcom,clear-warm-reset: Boolean which specifies that the WARM_RESET
|
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reason registers need to be cleared for this
|
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target. The property is used for the targets
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which have a hardware feature to catch resets
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which aren't triggered by the application
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processor. In such cases clearing WARM_REASON
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registers across processor resets keeps the
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registers in a useful state.
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- qcom,secondary-pon-reset: Boolean property which indicates that the PON
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peripheral is a secondary PON device which
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needs to be configured during reset in addition
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to the primary PON device that is configured
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for system reset through qcom,system-reset
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property.
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This should not be defined along with the
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qcom,system-reset or qcom,modem-reset property.
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- qcom,store-hard-reset-reason: Boolean property which if set will store the
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hardware reset reason to SOFT_RB_SPARE register
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of the core PMIC PON peripheral.
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- qcom,warm-reset-poweroff-type: Poweroff type required to be configured
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on PS_HOLD reset control register when the
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system goes for warm reset. If this property is
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not specified, then the default type, warm reset
|
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will be configured to PS_HOLD reset control
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register.
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Supported values: PON_POWER_OFF_TYPE_* found in
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include/dt-bindings/input/qcom,qpnp-power-on.h
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- qcom,hard-reset-poweroff-type: Same description as
|
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qcom,warm-reset-poweroff-type but this applies
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||||
for the system hard reset case.
|
||||
- qcom,shutdown-poweroff-type: Same description as qcom,warm-reset-poweroff-
|
||||
type but this applies for the system shutdown
|
||||
case.
|
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- qcom,kpdpwr-sw-debounce: Boolean property to enable the debounce logic
|
||||
on the KPDPWR_N rising edge.
|
||||
- qcom,resin-pon-reset: Boolean property which indicates that resin
|
||||
needs to be configured during reset in addition
|
||||
to the primary PON device that is configured
|
||||
for system reset through qcom,system-reset
|
||||
property.
|
||||
- qcom,resin-warm-reset-type: Poweroff type required to be configured on
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RESIN reset control register when the system
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initiates warm reset. If this property is not
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specified, then the default type, warm reset
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will be configured to RESIN reset control
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register. This property is effective only if
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qcom,resin-pon-reset is defined.
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Supported values: PON_POWER_OFF_TYPE_* found in
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include/dt-bindings/input/qcom,qpnp-power-on.h
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- qcom,resin-hard-reset-type: Same description as qcom,resin-warm-reset-type
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but this applies for the system hard reset case.
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- qcom,resin-shutdown-type: Same description as qcom,resin-warm-reset-type
|
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but this applies for the system shutdown case.
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- qcom,resin-shutdown-disable: Boolean property to disable RESIN power off
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trigger during system shutdown case.
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This property is effective only if
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qcom,resin-pon-reset is defined.
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- qcom,resin-hard-reset-disable: Boolean property to disable RESIN power
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||||
off trigger during system hard reset case.
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This property is effective only if
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qcom,resin-pon-reset is defined.
|
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- qcom,ps-hold-shutdown-disable: Boolean property to disable PS_HOLD
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power off trigger during system shutdown case.
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- qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD
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power off trigger during system hard reset case.
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Optional Sub-nodes:
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- qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features
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supported by the PON peripheral including reset
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configurations, pushbutton keys, and regulators.
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Sub-node properties:
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Sub-nodes (if defined) should belong to either a PON configuration or a
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regulator configuration.
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Regulator sub-node required properties:
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- regulator-name: Regulator name for the PON regulator that is
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being configured.
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- qcom,pon-spare-reg-addr: Register offset from the base address of the
|
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PON peripheral that needs to be configured for
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||||
the regulator being controlled.
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- qcom,pon-spare-reg-bit: Bit position in the specified register that
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needs to be configured for the regulator being
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controlled.
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PON sub-node required properties:
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- qcom,pon-type: The type of PON/RESET source. Supported values:
|
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0 = KPDPWR
|
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1 = RESIN
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2 = CBLPWR
|
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3 = KPDPWR_RESIN
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These values are PON_POWER_ON_TYPE_* found in
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include/dt-bindings/input/qcom,qpnp-power-on.h
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PON sub-node optional properties:
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- qcom,pull-up: Boolean flag indicating if a pull-up resistor
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should be enabled for the input.
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- qcom,support-reset: Indicates if this PON source supports
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reset functionality.
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0 = Not supported
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1 = Supported
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If this property is not defined, then default S2
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reset configurations should not be modified.
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- qcom,use-bark: Specify if this PON type needs to handle a bark
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interrupt.
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- linux,code: The input key-code associated with the reset
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source. The reset source in its default
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configuration can be used to support standard
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keys.
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The below mentioned properties are required only when qcom,support-reset DT
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property is defined and is set to 1.
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- qcom,s1-timer: The debounce timer for the BARK interrupt for
|
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the reset source. Value is specified in ms.
|
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Supported values are:
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0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
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1352, 2048, 3072, 4480, 6720, 10256
|
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- qcom,s2-timer: The debounce timer for the S2 reset specified
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in ms. On the expiry of this timer, the PMIC
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executes the reset sequence.
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Supported values are:
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0, 10, 50, 100, 250, 500, 1000, 2000
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- qcom,s2-type: The type of reset associated with this source.
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Supported values:
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0 = SOFT_RESET (legacy)
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1 = WARM_RESET
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4 = SHUTDOWN
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5 = DVDD_SHUTDOWN
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7 = HARD_RESET
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8 = DVDD_HARD_RESET
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These values are PON_POWER_OFF_TYPE_* found in
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include/dt-bindings/input/qcom,qpnp-power-on.h
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Examples:
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
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<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
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<0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
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<0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "kpdpwr", "resin", "resin-bark",
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"kpdpwr-resin-bark";
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qcom,pon-dbc-delay = <15625>;
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qcom,system-reset;
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qcom,s3-debounce = <32>;
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qcom,s3-src = "resin";
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qcom,clear-warm-reset;
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qcom,store-hard-reset-reason;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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qcom,pull-up;
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linux,code = <KEY_POWER>;
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};
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qcom,pon_2 {
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qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
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qcom,support-reset = <1>;
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qcom,pull-up;
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qcom,s1-timer = <0>;
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qcom,s2-timer = <2000>;
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qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
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linux,code = <KEY_VOLUMEDOWN>;
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qcom,use-bark;
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};
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qcom,pon_3 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
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qcom,support-reset = <1>;
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qcom,s1-timer = <6720>;
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qcom,s2-timer = <2000>;
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qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
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qcom,pull-up;
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qcom,use-bark;
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};
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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qcom,secondary-pon-reset;
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qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
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pon_perph_reg: qcom,pon_perph_reg {
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regulator-name = "pon_spare_reg";
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qcom,pon-spare-reg-addr = <0x8c>;
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qcom,pon-spare-reg-bit = <1>;
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};
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};
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@ -64,6 +64,7 @@ The below bindings specify the set of valid subnodes.
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"qcom,pm8921-rtc"
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"qcom,pm8941-rtc"
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"qcom,pm8018-rtc"
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"qcom,pmk8350-rtc"
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||||
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- reg:
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||||
Usage: required
|
||||
|
|
|
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|
|
@ -0,0 +1,5 @@
|
|||
#include "lahaina-pmic-overlay.dtsi"
|
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|
||||
&spmi_debug_bus {
|
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status = "ok"
|
||||
};
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#include "lahaina-pmic-overlay.dtsi"
|
||||
|
||||
&spmi_debug_bus {
|
||||
status = "ok"
|
||||
};
|
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8
qcom/lahaina-pmic-overlay.dtsi
Normal file
8
qcom/lahaina-pmic-overlay.dtsi
Normal file
|
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@ -0,0 +1,8 @@
|
|||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
|
||||
#include "pmk8350.dtsi"
|
||||
#include "pm8350.dtsi"
|
||||
#include "pm8350c.dtsi"
|
||||
#include "pm8350b.dtsi"
|
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#include "pmr735a.dtsi"
|
||||
#include "pmr735b.dtsi"
|
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|
|
@ -0,0 +1,5 @@
|
|||
#include "lahaina-pmic-overlay.dtsi"
|
||||
|
||||
&spmi_debug_bus {
|
||||
status = "ok"
|
||||
};
|
||||
|
|
@ -1,4 +1,9 @@
|
|||
#include "lahaina.dtsi"
|
||||
#include "lahaina-pmic-overlay.dtsi"
|
||||
|
||||
&spmi_debug_bus {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qrbtc-sdm845";
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <dt-bindings/interconnect/qcom,lahaina.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
|
@ -876,6 +877,9 @@
|
|||
qcom,retain-regs;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
};
|
||||
|
||||
cache-controller@9200000 {
|
||||
compatible = "qcom,lahaina-llcc", "qcom,llcc-v2";
|
||||
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
|
||||
|
|
@ -1202,6 +1206,66 @@
|
|||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
spmi_debug_bus: qcom,spmi-debug@6b12000 {
|
||||
compatible = "qcom,spmi-pmic-arb-debug";
|
||||
reg = <0x6b12000 0x60>, <0x7820a8 0x4>;
|
||||
reg-names = "core", "fuse";
|
||||
clocks = <&clock_aop QDSS_CLK>;
|
||||
clock-names = "core_clk";
|
||||
qcom,fuse-disable-bit = <24>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
qcom,pmk8350-debug@0 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <0 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
|
||||
qcom,pm8350-debug@1 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <1 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
|
||||
qcom,pm8350c-debug@2 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <2 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
|
||||
qcom,pm8350b-debug@3 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <3 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
|
||||
qcom,pmr735a-debug@4 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <4 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
|
||||
qcom,pmr735b-debug@5 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <5 SPMI_USID>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
qcom,can-sleep;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,msm-cdsp-loader {
|
||||
compatible = "qcom,cdsp-loader";
|
||||
qcom,proc-img-to-load = "cdsp";
|
||||
|
|
|
|||
61
qcom/pm8350.dtsi
Normal file
61
qcom/pm8350.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pm8350@1 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8350_tz: qcom,temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm8350_gpios: pinctrl@8800 {
|
||||
compatible = "qcom,pm8350-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pm8350_temp_alarm: pm8350_tz {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-governor = "step_wise";
|
||||
thermal-sensors = <&pm8350_tz>;
|
||||
|
||||
trips {
|
||||
pm8350_trip0: trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350_trip2: trip2 {
|
||||
temperature = <145000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
61
qcom/pm8350b.dtsi
Normal file
61
qcom/pm8350b.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pm8350b@3 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <3 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8350b_tz: qcom,temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm8350b_gpios: pinctrl@8800 {
|
||||
compatible = "qcom,pm8350b-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pm8350b_temp_alarm: pm8350b_tz {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-governor = "step_wise";
|
||||
thermal-sensors = <&pm8350b_tz>;
|
||||
|
||||
trips {
|
||||
pm8350b_trip0: trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350b_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350b_trip2: trip2 {
|
||||
temperature = <145000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
61
qcom/pm8350c.dtsi
Normal file
61
qcom/pm8350c.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pm8350c@2 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <2 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm8350c_tz: qcom,temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm8350c_gpios: pinctrl@8800 {
|
||||
compatible = "qcom,pm8350c-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pm8350c_temp_alarm: pm8350c_tz {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-governor = "step_wise";
|
||||
thermal-sensors = <&pm8350c_tz>;
|
||||
|
||||
trips {
|
||||
pm8350c_trip0: trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350c_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pm8350c_trip2: trip2 {
|
||||
temperature = <145000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
38
qcom/pmk8350.dtsi
Normal file
38
qcom/pmk8350.dtsi
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pmk8350@0 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmk8350_sdam_2: sdam@7100 {
|
||||
compatible = "qcom,spmi-sdam";
|
||||
reg = <0x7100>;
|
||||
};
|
||||
|
||||
pmk8350_gpios: pinctrl@b000 {
|
||||
compatible = "qcom,pmk8350-gpio";
|
||||
reg = <0xb000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pmk8350_rtc: rtc@6100 {
|
||||
compatible = "qcom,pmk8350-rtc";
|
||||
reg = <0x6100>, <0x6200>;
|
||||
reg-names = "rtc", "alarm";
|
||||
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
61
qcom/pmr735a.dtsi
Normal file
61
qcom/pmr735a.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pmr735a@4 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <4 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmr735a_tz: qcom,temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmr735a_gpios: pinctrl@8800 {
|
||||
compatible = "qcom,pmr735a-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pmr735a_temp_alarm: pmr735a_tz {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-governor = "step_wise";
|
||||
thermal-sensors = <&pmr735a_tz>;
|
||||
|
||||
trips {
|
||||
pmr735a_trip0: trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pmr735a_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pmr735a_trip2: trip2 {
|
||||
temperature = <145000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
61
qcom/pmr735b.dtsi
Normal file
61
qcom/pmr735b.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
&spmi_bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
|
||||
qcom,pmr735b@5 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
reg = <5 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmr735b_tz: qcom,temp-alarm@a00 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0xa00>;
|
||||
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pmr735b_gpios: pinctrl@8800 {
|
||||
compatible = "qcom,pmr735b-gpio";
|
||||
reg = <0x8800>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pmr735b_temp_alarm: pmr735b_tz {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay = <0>;
|
||||
thermal-governor = "step_wise";
|
||||
thermal-sensors = <&pmr735b_tz>;
|
||||
|
||||
trips {
|
||||
pmr735b_trip0: trip0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pmr735b_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
pmr735b_trip2: trip2 {
|
||||
temperature = <145000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue