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Merge 00f1532751 on remote branch

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Change-Id: I5dca6c43d83582c1deb3d10ad4044b84dd02244b
This commit is contained in:
Linux Build Service Account 2020-11-06 03:37:02 -08:00
commit eeaa0c9ab9
85 changed files with 8150 additions and 519 deletions
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6
bindings/arm/coresight.txt
View file

@ -137,6 +137,12 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* cti-reset-trig-num: Specifies the reset CTI trigger number for TMC
ETR and TMC ETF.
* cti-flush-trig-num: Specifies the flush CTI trigger number for TMC
ETR and TMC ETF.
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error for CATU and four interrupts for TGU to get trigger from four

3
bindings/arm/msm/msm.txt
View file

@ -192,6 +192,9 @@ compatible = "qcom,sa8155p-adp-star"
compatible = "qcom,sa8155-adp-air"
compatible = "qcom,sa8155-v2-adp-air"
compatible = "qcom,sa8155p-v2-adp-air"
compatible = "qcom,sa8195p-adp-star"
compatible = "qcom,sa8195p-v2-adp-air"
compatible = "qcom,sa8195p"
compatible = "qcom,adp-air"
compatible = "qcom,kona-rumi"
compatible = "qcom,kona-mtp"

2
bindings/mailbox/qcom,apcs-kpss-global.txt
View file

@ -17,6 +17,8 @@ platforms.
"qcom,sm8150-apss-shared"
"qcom,ipq8074-apcs-apps-global"
"qcom,sdxlemur-apcs-gcc"
"qcom,scuba-apcs-hmss-global"
"qcom,monaco-apcs-hmss-global"
- reg:
Usage: required

185
bindings/pinctrl/qcom,sdmshrike-pinctrl.txt Normal file
View file

@ -0,0 +1,185 @@
Qualcomm Technologies, Inc. SDMSHRIKE TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
sdmshrike platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,sdmshrike-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the north, south, west
and east TLMM tiles.
- reg-names:
Usage: required
Value type: <prop-encoded-array>
Defintiion: names for the cells of reg, must contain "north", "south"
"west" and "east".
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Value type: <prop-encoded-array>
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
ufs_reset
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
atest_char0, atest_char1, atest_char2, atest_char3,
audio_ref, atest_usb1, atest_usb2, atest_usb10,
atest_usb11, atest_usb12, atest_usb13, atest_usb20,
atest_usb21, atest_usb22, atest_usb2, atest_usb23,
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
pa_indicator, pci_e0, phase_flag, pll_bypassnl,
pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@3000000 {
compatible = "qcom,sdmshrike-pinctrl";
reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>;
reg-names = "pinctrl", "spi_cfg";
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

9
bindings/thermal/qti-qmi-sensor.txt
View file

@ -62,6 +62,15 @@ Subsystem properties:
29. mmw_pa3
30. sdr_mmw_therm
31. msm_skin_therm
32. beamer_n_therm
33. beamer_e_therm
34. beamer_w_therm
35. qfe_ret_pa0_fr1
36. qfe_wtr_pa0_fr1
37. qfe_wtr_pa1_fr1
38. qfe_wtr_pa2_fr1
39. qfe_wtr_pa3_fr1
40. qfe_wtr0_fr1
Example:

40
qcom/Makefile
View file

@ -144,26 +144,35 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SM8150) += \
sm8150-cdp-overlay.dtbo \
sa8155-adp-star-overlay.dtbo \
sa8155p-adp-star-overlay.dtbo \
sa8155-v2-adp-air-overlay.dtbo \
sa8155p-v2-adp-air-overlay.dtbo
dtbo-$(CONFIG_ARCH_SA8155) += \
sa8155-adp-star-overlay.dtbo \
sa8155p-adp-star-overlay.dtbo \
sa8155-v2-adp-air-overlay.dtbo \
sa8155p-v2-adp-air-overlay.dtbo
sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb
sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb
sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb
sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb
sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb
else
dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \
sa8155-adp-star.dtb \
sa8155p-adp-star.dtb \
sa8155-v2-adp-star.dtb \
sa8155p-v2-adp-star.dtb \
sa8155-v2-adp-air.dtb \
sa8155p-v2-adp-air.dtb
dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \
sa8155p-adp-star.dtb \
sa8155-v2-adp-star.dtb \
sa8155p-v2-adp-star.dtb \
sa8155-v2-adp-air.dtb \
sa8155p-v2-adp-air.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SA8195) += \
sa8195p-adp-star-overlay.dtbo \
sa8195p-v2-adp-air-overlay.dtbo
sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb
sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb
else
dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \
sa8195p-v2-adp-air.dtb
endif
endif
@ -171,7 +180,8 @@ ifeq ($(CONFIG_ARCH_LAHAINA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \
lahaina-vm-cdp.dtb \
lahaina-vm-qrd.dtb
lahaina-vm-qrd.dtb \
lahaina-vm-mtp-v2.1.dtb
endif
endif

2
qcom/holi-atp.dtsi
View file

@ -21,7 +21,7 @@
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
qcom,vdd-io-current-level = <325000 325000>;
};
&sdhc_2 {

5
qcom/holi-audio-overlay.dtsi
View file

@ -55,6 +55,11 @@
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <1>;
qcom,swr-phy-dev-addr = <0x0A 0x01170223>,
<0x08 0x58350223>,
<0x08 0x58350222>,
<0x08 0x58350221>,
<0x08 0x58350220>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
qcom,is-always-on = <1>;

7
qcom/holi-coresight.dtsi
View file

@ -1134,7 +1134,7 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
funnel_gpu_out_tpda_center2: endpoint {
@ -1959,6 +1959,9 @@
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "apb_pclk";
coresight-ctis = <&cti0 &cti6>;
cti-reset-trig-num = <5>;
cti-flush-trig-num = <1>;
in-ports {
port {
tmc_etf_in_funnel_merge: endpoint {
@ -2039,6 +2042,8 @@
qcom,sw-usb;
coresight-ctis = <&cti0 &cti6>;
cti-reset-trig-num = <5>;
cti-flush-trig-num = <3>;
coresight-csr = <&csr>;
interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "byte-cntr-irq";

12
qcom/holi-gdsc.dtsi
View file

@ -97,6 +97,16 @@
reg = <0x5991008 0x4>;
};
gpu_gx_acd_reset: syscon@5991160 {
compatible = "syscon";
reg = <0x5991160 0x4>;
};
gpu_gx_acd_misc_reset: syscon@5998004 {
compatible = "syscon";
reg = <0x5998004 0x4>;
};
gpu_cx_gdsc: qcom,gdsc@599106c {
compatible = "qcom,gdsc";
reg = <0x599106c 0x4>;
@ -113,6 +123,8 @@
reg = <0x599100c 0x4>;
regulator-name = "gpu_gx_gdsc";
sw-reset = <&gpu_gx_sw_reset>;
acd-reset = <&gpu_gx_acd_reset>;
acd-misc-reset = <&gpu_gx_acd_misc_reset>;
domain-addr = <&gpu_gx_domain_addr>;
qcom,reset-aon-logic;
status = "disabled";

4
qcom/holi-qrd.dtsi
View file

@ -232,6 +232,10 @@
};
};
&pm6150a_l1 {
qcom,init-voltage = <1860000>;
};
&pm6150a_amoled {
status = "ok"
};

6
qcom/holi-qupv3.dtsi
View file

@ -26,7 +26,8 @@
<MASTER_QUP_0 SLAVE_EBI>;
qcom,vote-for-bw;
iommus = <&apps_smmu 0x0003 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
};
@ -190,7 +191,8 @@
<MASTER_QUP_1 SLAVE_EBI>;
qcom,vote-for-bw;
iommus = <&apps_smmu 0x00c3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
};

2
qcom/holi-regulators.dtsi
View file

@ -459,7 +459,7 @@
L1E: pm6150a_l1: regulator-l1 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1650000>;
qcom,init-voltage = <1800000>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-current = <62000>;
status = "okay";

9
qcom/holi.dtsi
View file

@ -2131,8 +2131,8 @@
sdhc_1: sdhci@4744000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
reg-names = "hc_mem", "cqhci_mem";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>;
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
iommus = <&apps_smmu 0x20 0x0>;
qcom,iommu-dma = "fastmap";
@ -2509,8 +2509,8 @@
qcom_hwkm: hwkm@4440000 {
compatible = "qcom,hwkm";
reg = <0x4440000 0x9000>, <0x04810000 0x9000>;
reg-names = "km_master", "ice_slave";
reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>;
reg-names = "km_master", "ice_slave", "sdcc_ice_slave";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
@ -2569,6 +2569,7 @@
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,wlan-msa-fixed-region = <&pil_wlan_mem>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
vdd-cx-mx-supply = <&L4A>;
vdd-1.8-xo-supply = <&L7A>;
vdd-1.3-rfa-supply = <&L2E>;

6
qcom/lahaina-cdp.dtsi
View file

@ -102,6 +102,12 @@
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
atmel_mxt_ts@4a {

8
qcom/lahaina-coresight.dtsi
View file

@ -107,7 +107,9 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0_swao &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <1>;
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@ -154,7 +156,9 @@
qcom,sw-usb;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0 &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <3>;
coresight-csr = <&csr>;
clocks = <&clock_aop QDSS_CLK>;

6
qcom/lahaina-mtp.dtsi
View file

@ -104,6 +104,12 @@
panel = <&dsi_r66451_amoled_cmd
&dsi_r66451_amoled_video>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

2
qcom/lahaina-pcie.dtsi
View file

@ -100,6 +100,7 @@
<0x100 &apps_smmu 0x1c01 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,l1ss-sleep-disable = <0x1>;
qcom,drv-l1ss-timeout-us = <5000>;
@ -328,6 +329,7 @@
<0x100 &apps_smmu 0x1c81 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,wr-halt-size = <0x8>;
qcom,no-l0s-supported;

30
qcom/lahaina-thermal-modem.dtsi
View file

@ -292,36 +292,6 @@
};
};
modem-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MODEM_TSENS)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-1-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MODEM_TSENS_1)>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-streamer-usr {
polling-delay-passive = <0>;
polling-delay = <0>;

21
qcom/lahaina-thermal-overlay.dtsi
View file

@ -184,12 +184,6 @@
THERMAL_MAX_LIMIT>;
};
pm8350_cpu0_freq {
trip = <&pm8350_trip0>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
pm8350_cpu4_freq {
trip = <&pm8350_trip0>;
cooling-device = <&CPU4 THERMAL_MAX_LIMIT
@ -202,21 +196,6 @@
THERMAL_MAX_LIMIT>;
};
pm8350_cpu1 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu1_isolate 1 1>;
};
pm8350_cpu2 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu2_isolate 1 1>;
};
pm8350_cpu3 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu3_isolate 1 1>;
};
pm8350_cpu4 {
trip = <&pm8350_trip0>;
cooling-device = <&cpu4_isolate 1 1>;

24
qcom/lahaina-thermal.dtsi
View file

@ -792,12 +792,6 @@
cooling-device = <&cpu0_isolate 1 1>;
};
cpu00_cdev1 {
trip = <&cpu00_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu00_cdev2 {
trip = <&cpu00_config1>;
cooling-device = <&cpu0_hotplug 1 1>;
@ -830,12 +824,6 @@
cooling-device = <&cpu1_isolate 1 1>;
};
cpu01_cdev1 {
trip = <&cpu01_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu01_cdev2 {
trip = <&cpu01_config1>;
cooling-device = <&cpu1_hotplug 1 1>;
@ -868,12 +856,6 @@
cooling-device = <&cpu2_isolate 1 1>;
};
cpu02_cdev1 {
trip = <&cpu02_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu02_cdev2 {
trip = <&cpu02_config1>;
cooling-device = <&cpu2_hotplug 1 1>;
@ -906,12 +888,6 @@
cooling-device = <&cpu3_isolate 1 1>;
};
cpu03_cdev1 {
trip = <&cpu03_config>;
cooling-device = <&CPU0 THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpu03_cdev2 {
trip = <&cpu03_config1>;
cooling-device = <&cpu3_hotplug 1 1>;

10
qcom/lahaina-vm-mtp-v2.1.dts Normal file
View file

@ -0,0 +1,10 @@
/dts-v1/;
#include "lahaina-vm-v2.dtsi"
#include "lahaina-vm-mtp-v2.1.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina SVM MTP V2.1";
compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp";
qcom,board-id = <0x20108 0>;
};

19
qcom/lahaina-vm-mtp-v2.1.dtsi Normal file
View file

@ -0,0 +1,19 @@
&qupv3_se4_i2c {
status = "ok"
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>;
};

7
qcom/lahaina-vm-v2.dtsi Normal file
View file

@ -0,0 +1,7 @@
#include "lahaina-vm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Lahaina VM v2";
compatible = "qcom,lahaina";
qcom,msm-id = <415 0x20000>;
};

557
qcom/lahaina.dtsi
View file

@ -32,7 +32,13 @@
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
mem-offline {
compatible = "qcom,mem-offline";
@ -57,6 +63,8 @@
usb1 = &usb1;
};
firmware: firmware {};
cpus {
#address-cells = <2>;
#size-cells = <0>;
@ -261,292 +269,288 @@
};
soc: soc { };
};
firmware: firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
&firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_region@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: reserved-memory@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
cdsp_secure_heap: cdsp_secure_heap@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0x4600000>;
};
pil_camera_mem: pil_camera_region@85200000 {
no-map;
reg = <0x0 0x85200000 0x0 0x500000>;
};
pil_video_mem: pil_video_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x500000>;
};
pil_cvp_mem: pil_cvp_region@85c00000 {
no-map;
reg = <0x0 0x85c00000 0x0 0x500000>;
};
pil_adsp_mem: pil_adsp_region@86100000 {
no-map;
reg = <0x0 0x86100000 0x0 0x2100000>;
};
pil_slpi_mem: pil_slpi_region@88200000 {
no-map;
reg = <0x0 0x88200000 0x0 0x1500000>;
};
pil_cdsp_mem: pil_cdsp_region@89700000 {
no-map;
reg = <0x0 0x89700000 0x0 0x1e00000>;
};
pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 {
no-map;
reg = <0x0 0x8b500000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 {
no-map;
reg = <0x0 0x8b510000 0x0 0xa000>;
};
pil_gpu_mem: pil_gpu_region@8b51a000 {
no-map;
reg = <0x0 0x8b51a000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@8b600000 {
no-map;
reg = <0x0 0x8b600000 0x0 0x100000>;
};
pil_modem_mem: modem_region@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0x10000000>;
};
hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0x800000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
reg = <0x0 0xd0800000 0x0 0x76f7000>;
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
removed_mem: removed_region@d8800000 {
no-map;
reg = <0x0 0xd8800000 0x0 0x6800000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA400000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x3000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_region";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
xbl_aop_mem: xbl_aop_region@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: reserved-memory@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
cdsp_secure_heap: cdsp_secure_heap@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0x4600000>;
};
pil_camera_mem: pil_camera_region@85200000 {
no-map;
reg = <0x0 0x85200000 0x0 0x500000>;
};
pil_video_mem: pil_video_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x500000>;
};
pil_cvp_mem: pil_cvp_region@85c00000 {
no-map;
reg = <0x0 0x85c00000 0x0 0x500000>;
};
pil_adsp_mem: pil_adsp_region@86100000 {
no-map;
reg = <0x0 0x86100000 0x0 0x2100000>;
};
pil_slpi_mem: pil_slpi_region@88200000 {
no-map;
reg = <0x0 0x88200000 0x0 0x1500000>;
};
pil_cdsp_mem: pil_cdsp_region@89700000 {
no-map;
reg = <0x0 0x89700000 0x0 0x1e00000>;
};
pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 {
no-map;
reg = <0x0 0x8b500000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 {
no-map;
reg = <0x0 0x8b510000 0x0 0xa000>;
};
pil_gpu_mem: pil_gpu_region@8b51a000 {
no-map;
reg = <0x0 0x8b51a000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@8b600000 {
no-map;
reg = <0x0 0x8b600000 0x0 0x100000>;
};
pil_modem_mem: modem_region@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0x10000000>;
};
hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0x800000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
reg = <0x0 0xd0800000 0x0 0x76f7000>;
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
removed_mem: removed_region@d8800000 {
no-map;
reg = <0x0 0xd8800000 0x0 0x6800000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA400000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x3000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_region";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
};
@ -3148,9 +3152,6 @@
qcom,iommu-dma = "fastmap";
dma-coherent;
rpm-level = <3>;
spm-level = <5>;
status = "disabled";
qos0 {
mask = <0xf0>;

246
qcom/msm-arm-smmu-yupik.dtsi Normal file
View file

@ -0,0 +1,246 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@3da0000 {
status = "disabled";
compatible = "qcom,qsmmu-v500";
reg = <0x3da0000 0x20000>,
<0x3dd6000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
#global-interrupts = <2>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
gfx_0_tbu: gfx_0_tbu@3dd9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3dd9000 0x1000>,
<0x3dd6200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
};
gfx_1_tbu: gfx_1_tbu@3ddd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3ddd000 0x1000>,
<0x3dd6208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
};
};
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>,
<0x151da000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
#global-interrupts = <2>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
anoc_1_tbu: anoc_1_tbu@151dd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151dd000 0x1000>,
<0x151da200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
};
anoc_2_tbu: anoc_2_tbu@151e1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e1000 0x1000>,
<0x151da208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
};
mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e5000 0x1000>,
<0x151da210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
};
mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e9000 0x1000>,
<0x151da218 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0xc00 0x400>;
};
compute_dsp_1_tbu: compute_dsp_1_tbu@151ed000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151ed000 0x1000>,
<0x151da220 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1000 0x400>;
};
compute_dsp_0_tbu: compute_dsp_0_tbu@151f1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f1000 0x1000>,
<0x151da228 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1400 0x400>;
};
adsp_tbu: adsp_tbu@151f5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f5000 0x1000>,
<0x151da230 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1800 0x400>;
};
anoc_1_pcie_tbu: anoc_1_pcie_tbu@151f9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f9000 0x1000>,
<0x151da238 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1c00 0x400>;
};
mnoc_sf_0_tbu: mnoc_sf_0_tbu@151fd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151fd000 0x1000>,
<0x151da240 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x2000 0x400>;
};
};
kgsl_iommu_test_device {
status = "disabled";
compatible = "iommu-debug-test";
iommus = <&kgsl_smmu 0x7 0>;
qcom,iommu-dma = "disabled";
};
kgsl_iommu_coherent_test_device {
status = "disabled";
compatible = "iommu-debug-test";
iommus = <&kgsl_smmu 0x407 0>;
qcom,iommu-dma = "disabled";
dma-coherent;
};
apps_iommu_test_device {
compatible = "iommu-debug-test";
iommus = <&apps_smmu 0x0 0>;
qcom,iommu-dma = "disabled";
};
apps_iommu_coherent_test_device {
compatible = "iommu-debug-test";
iommus = <&apps_smmu 0x1 0>;
qcom,iommu-dma = "disabled";
dma-coherent;
};
};

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@ -0,0 +1,5 @@
#include <dt-bindings/gpio/gpio.h>
&qupv3_id_1 {
status = "ok"
};

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@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "sa8195p-adp-star.dtsi"
/ {
model = "ADP-STAR";
compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p",
"qcom,adp-star";
qcom,msm-id = <405 0x20000>;
qcom,board-id = <0x010019 0>;
};

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@ -0,0 +1,11 @@
/dts-v1/;
#include "sa8195p.dtsi"
#include "sa8195p-adp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR";
compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p",
"qcom,adp-star";
qcom,board-id = <25 0>;
};

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@ -0,0 +1 @@
#include "sa8195p-adp-common.dtsi"

13
qcom/sa8195p-v2-adp-air-overlay.dts Normal file
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@ -0,0 +1,13 @@
/dts-v1/;
/plugin/;
#include "sa8195p-v2-adp-air.dtsi"
/ {
model = "ADP-AIR";
compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p",
"qcom,adp-air";
qcom,msm-id = <405 0x20000>;
qcom,board-id = <0x02010019 0>;
};

10
qcom/sa8195p-v2-adp-air.dts Normal file
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@ -0,0 +1,10 @@
/dts-v1/;
#include "sa8195p.dtsi"
#include "sa8195p-adp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR";
compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", "qcom,adp-air";
qcom,board-id = <0x02010019 0>;
};

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@ -0,0 +1 @@
#include "sa8195p-adp-common.dtsi"

10
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@ -0,0 +1,10 @@
/dts-v1/;
#include "sa8195p.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195P AU SoC";
compatible = "qcom,sa8195";
qcom,pmic-name = "PM8150";
qcom,board-id = <0 0>;
};

8
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#include "sdmshrike-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195P";
qcom,msm-name = "SA8195P";
qcom,msm-id = <405 0x20000>;
};

198
qcom/scuba-iot.dtsi
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@ -567,6 +567,204 @@ dcc: dcc_v2@1be2000 {
#interrupt-cells = <4>;
cell-index = <0>;
};
tcsr_mutex_block: syscon@00340000 {
compatible = "syscon";
reg = <0x340000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 3>;
};
rpm_msg_ram: memory@045f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x45f0000 0x7000>;
};
apcs_glb: mailbox@0f111000 {
compatible = "qcom,scuba-apcs-hmss-global";
reg = <0xF111000 0x1000>;
#mbox-cells = <1>;
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
qcom,rpm_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_adsp>;
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&apcs_glb 12>;
mbox-names = "mpss_smem";
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 2>;
};
qcom,modem_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>;
};
};
glink_adsp: adsp {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&apcs_glb 8>;
mbox-names = "adsp_smem";
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>;
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
slim_aud: slim@a5c0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0xa5c0000 0x2c000>,
<0xa584000 0x20000>, <0xa66e000 0x2000>;
reg-names = "slimbus_physical",
"slimbus_bam_physical","slimbus_lpass_mem";
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x360>;
status = "ok"
};
};
#include "pm2250.dtsi"

5155
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10
qcom/sdmshrike-v2.dts Normal file
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@ -0,0 +1,10 @@
/dts-v1/;
#include "sdmshrike-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195 v2 SoC";
compatible = "qcom,sa8195";
qcom,pmic-name = "PM8150";
qcom,board-id = <0 0>;
};

8
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@ -0,0 +1,8 @@
#include "sdmshrike.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA8195 V2";
qcom,msm-name = "SA8195 V2";
qcom,msm-id = <340 0x20000>;
};

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qcom/sdmshrike.dts Normal file
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@ -0,0 +1,10 @@
/dts-v1/;
#include "sdmshrike.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC";
compatible = "qcom,sdmshrike";
qcom,pmic-name = "PM8150";
qcom,board-id = <0 0>;
};

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@ -0,0 +1,656 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
model = "Qualcomm Technologies, Inc. SDMSHRIKE";
compatible = "qcom,sdmshrike";
qcom,msm-name = "SDMSHRIKE";
qcom,msm-id = <340 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
aliases {
serial0 = &uart2;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x400000>;
cache-level = <3>;
};
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_200: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_200: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_300: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_300: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_400: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_400: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_500: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_500: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_600: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_600: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_700: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_700: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
chosen {
stdout-path = "serial0:115200n8";
};
firmware: firmware {
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_mem@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
no-map;
reg = <0x0 0x85e00000 0x0 0x140000>;
};
flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
no-map;
reg = <0x0 0x85ffd000 0x0 0x3000>;
};
smem_region: smem@86000000 {
no-map;
reg = <0x0 0x86000000 0x0 0x200000>;
};
removed_regions: removed_regions@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x5500000>;
};
pil_camera_mem: camera_region@8b700000 {
no-map;
reg = <0x0 0x8b700000 0x0 0x500000>;
};
pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
no-map;
reg = <0x0 0x8bc00000 0x0 0x180000>;
};
pil_npu_mem: pil_npu_region@0x8bd80000 {
no-map;
reg = <0x0 0x8bd80000 0x0 0x80000>;
};
pil_adsp_mem: pil_adsp_region@0x8be00000 {
no-map;
reg = <0x0 0x8be00000 0x0 0x1a00000>;
};
pil_modem_mem: modem_region@0x8d800000 {
no-map;
reg = <0x0 0x8d800000 0x0 0x9600000>;
};
pil_video_mem: pil_video_region@0x96e00000 {
no-map;
reg = <0x0 0x96e00000 0x0 0x500000>;
};
pil_slpi_mem: pil_slpi_region@0x97300000 {
no-map;
reg = <0x0 0x97300000 0x0 0x1400000>;
};
pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 {
no-map;
reg = <0x0 0x98700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 {
no-map;
reg = <0x0 0x98710000 0x0 0x5000>;
};
pil_gpu_mem: pil_gpu_region@0x98715000 {
no-map;
reg = <0x0 0x98715000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@0x98800000 {
no-map;
reg = <0x0 0x98800000 0x0 0x100000>;
};
pil_cdsp_mem: cdsp_regions@0x98900000 {
no-map;
reg = <0x0 0x98900000 0x0 0x1400000>;
};
qseecom_mem: qseecom_region@0x9e400000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x9e400000 0x0 0x1400000>;
};
cont_splash_memory: cont_splash_region@0x9c000000 {
reg = <0x0 0x9c000000 0x0 0x02400000>;
label = "cont_splash_region";
};
disp_rdump_memory: disp_rdump_region@0x9c000000 {
reg = <0x0 0x9c000000 0x0 0x02400000>;
label = "disp_rdump_region";
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA000000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
reusable;
size = <0 0x2400000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2800000>;
linux,cma-default;
};
};
vendor: vendor {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
interrupt-parent = <&intc>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@0x17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@0x17c21000 {
frame-number = <0>;
interrupts = <0 7 0x4>,
<0 6 0x4>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <0 8 0x4>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <0 9 0x4>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <0 10 0x4>;
reg = <0x17c26000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <0 11 0x4>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <0 12 0x4>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <0 13 0x4>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x00ac0000 0x6000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "ok"
};
};
};
#include "sdmshrike-pinctrl.dtsi"

9
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@ -0,0 +1,9 @@
#include "sdxlemur-512mb.dtsi"
&mpss_adsp_mem {
reg = <0x90800000 0x10000000>;
};
&access_control_mem {
reg = <0x8fd80000 0x80000>;
};

53
qcom/sdxlemur-512mb.dtsi Normal file
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@ -0,0 +1,53 @@
&reserved_memory {
mpss_adsp_mem: mpss_adsp_region@90800000 {
no-map;
reg = <0x90800000 0xF800000>;
};
tz_mem: tz_mem_region@8ff00000 {
no-map;
reg = <0x8ff00000 0x600000>;
};
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x8fee0000 0x20000>;
};
smem_mem: smem_region@8fe20000 {
no-map;
reg = <0x8fe20000 0xc0000>;
label = "smem_mem";
};
aop_mem: aop_regions@0x8fe00000 {
no-map;
reg = <0x8fe00000 0x20000>;
};
access_control_mem: access_control_region@8fd80000 {
no-map;
reg = <0x8fd80000 0x40000>;
};
hyp_mem: hyp_region@8fd00000 {
no-map;
reg = <0x8fd00000 0x80000>;
};
secdata_mem: secdata_region@0x8fcfd000 {
no-map;
reg = <0x8fcfd000 0x1000>;
};
ipa_fw_mem: ipa_fw_region@0x8fced000 {
no-map;
reg = <0x8fced000 0x10000>;
};
mpss_dsm: mpss_dsm_region@8c400000 {
no-map;
reg = <0x8c400000 0x3200000>;
};
};

2
qcom/sdxlemur-cdp.dts
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@ -2,7 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-cdp.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR CDP";
compatible = "qcom,sdxlemur-cdp",

22
qcom/sdxlemur-cdp.dtsi
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@ -8,6 +8,28 @@
status = "ok"
};
&sdhc_1 {
status = "ok"
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&vreg_vddpx_2>;
qcom,vdd-io-voltage-level = <1800000 2850000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
};
&usb {
extcon = <&vbus_detect>;
};
&pcie0 {
qcom,boot-option = <0x1>;
};

1
qcom/sdxlemur-mtp-cpe.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-cpe.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE";

1
qcom/sdxlemur-mtp-cpe.dtsi
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@ -1,3 +1,4 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {

1
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE";

1
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
View file

@ -1,3 +1,4 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {

1
qcom/sdxlemur-mtp-mbb-pcie-ep.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-pcie-ep.dtsi"
#include "sdxlemur-512mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP";

1
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi"
#include "sdxlemur-512mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP";

1
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi
View file

@ -1,3 +1,4 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {

1
qcom/sdxlemur-mtp-mbb.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp-mbb.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB";

38
qcom/sdxlemur-mtp-mbb.dtsi
View file

@ -1,5 +1,43 @@
#include "sdxlemur-pmic-overlay.dtsi"
#include "pm7250b.dtsi"
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
};
&soc {
};
&pcie0 {
qcom,boot-option = <0x1>;
};
&sdhc_1 {
reg = <0x08804000 0x1000>, <0x08805000 0x1000>;
reg-names = "hc_mem", "cqhci_mem";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
bus-width = <8>;
non-removable;
supports-cqe;
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L6B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
status = "ok"
};

1
qcom/sdxlemur-mtp.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-mtp.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR MTP";

18
qcom/sdxlemur-mtp.dtsi
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@ -8,6 +8,24 @@
status = "ok"
};
&sdhc_1 {
status = "ok"
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&vreg_vddpx_2>;
qcom,vdd-io-voltage-level = <1800000 2850000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
};
&usb {
extcon = <&vbus_detect>;
};

3
qcom/sdxlemur-pcie.dtsi
View file

@ -91,8 +91,7 @@
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
<0x100 &apps_smmu 0x0201 0x1>;
qcom,boot-option = <0x1>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <17>; /* 16.6 MHz */
qcom,slv-addr-space-size = <0x40000000>;
qcom,ep-latency = <10>;

92
qcom/sdxlemur-pinctrl.dtsi
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@ -40,6 +40,98 @@
};
};
sdc1_on: sdc1_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc1_off: sdc1_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_on: sdc2_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio99";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_off: sdc2_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sd-cd {
pins = "gpio99";
bias-disable;
drive-strength = <2>;
};
};
pcie0 {
pcie0_clkreq_default: pcie0_clkreq_default {
mux {

1
qcom/sdxlemur-rcm-pcie-ep.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-rcm-pcie-ep.dtsi"
#include "sdxlemur-512mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP";

1
qcom/sdxlemur-rcm-pcie-ep.dtsi
View file

@ -1,3 +1,4 @@
#include "sdxlemur-pmic-overlay.dtsi"
&soc {

1
qcom/sdxlemur-rcm-rc.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-rcm-rc.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex";

10
qcom/sdxlemur-rcm-rc.dtsi
View file

@ -1,5 +1,15 @@
#include "sdxlemur-pmic-overlay.dtsi"
#include "pm7250b.dtsi"
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
};
&soc {
};
&pcie0 {
qcom,boot-option = <0x1>;
};

1
qcom/sdxlemur-rumi.dts
View file

@ -2,6 +2,7 @@
#include "sdxlemur.dtsi"
#include "sdxlemur-rumi.dtsi"
#include "sdxlemur-1024mb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDXLEMUR RUMI";

155
qcom/sdxlemur-thermal.dtsi Normal file
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@ -0,0 +1,155 @@
&soc {
tsens0: tsens@c222000 {
compatible = "qcom,tsens24xx";
reg = <0xc222000 0x152>,
<0xc263000 0x1ff>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tsens-upper-lower", "tsens-critical";
#thermal-sensor-cells = <1>;
};
};
&thermal_zones {
aoss-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
cpuss-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmq6-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-0-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 3>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-1-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 4>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-2-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 5>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
mdmss-3-usr {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "user_space";
thermal-sensors = <&tsens0 6>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
};
};
};

31
qcom/sdxlemur-usb.dtsi
View file

@ -7,7 +7,7 @@
reg-names = "core_base";
iommus = <&apps_smmu 0x1a0 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
#address-cells = <1>;
#size-cells = <1>;
@ -63,6 +63,35 @@
dr_mode = "otg";
snps,xhci-imod-value = <4000>;
};
qcom,usbbam@a704000 {
compatible = "qcom,usb-bam-msm";
reg = <0xa704000 0x17000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
qcom,usb-bam-fifo-baseaddr = <0x1468b000>;
qcom,usb-bam-num-pipes = <4>;
qcom,disable-clk-gating;
qcom,usb-bam-override-threshold = <0x4001>;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,reset-bam-on-connect;
qcom,pipe0 {
label = "ssusb-qdss-in-0";
qcom,usb-bam-mem-type = <2>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <0>;
qcom,peer-bam-physical-address = <0x6064000>;
qcom,src-bam-pipe-index = <0>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x0>;
qcom,data-fifo-size = <0x1800>;
qcom,descriptor-fifo-offset = <0x1800>;
qcom,descriptor-fifo-size = <0x800>;
};
};
};
usb_nop_phy: usb_nop_phy {

74
qcom/sdxlemur.dtsi
View file

@ -32,48 +32,6 @@
#size-cells = <1>;
ranges;
cmd_db: reserved-memory@8fee0000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x8fee0000 0x20000>;
};
mpss_adsp_mem: mpss_adsp_region@90800000 {
no-map;
reg = <0x90800000 0x10000000>;
};
tz_mem: tz_mem_region@8ff00000 {
no-map;
reg = <0x8ff00000 0x600000>;
};
smem_mem: smem_region@8fe40000 {
no-map;
reg = <0x8fe40000 0xc0000>;
label = "smem_mem";
};
peripheral_mem: peripheral_region@8fd00000 {
no-map;
reg = <0x8fd00000 0x140000>;
};
/*
* The exact size of this region may vary based on DDR size.
* 0x100000 will be valid for all DDR sizes at the cost of
* slightly reducing the memory available for HLOS.
*/
peripheral_mem2: peripheral_region2@8fb00000 {
no-map;
reg = <0x8fb00000 0x100000>;
};
mpss_dsm: mpss_dsm_region@8c400000 {
no-map;
reg = <0x8c400000 0x3200000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x00000000 0xffffffff>;
@ -474,6 +432,34 @@
status = "disabled";
};
sdhc_1: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
bus-width = <4>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 200000000>;
status = "disabled";
qos0 {
mask = <0x1>;
vote = <44>;
};
};
apsscc: clock-controller@17808100 {
compatible = "qcom,sdxlemur-apsscc";
clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>;
@ -854,7 +840,6 @@
qcom,additional-mapping =
/* modem tables in IMEM */
<0x14688000 0x14688000 0x3000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
@ -862,7 +847,6 @@
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x5E1 0x0>;
dma-coherent;
qcom,iommu-dma = "atomic";
};
@ -876,7 +860,6 @@
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x5E3 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
@ -935,3 +918,4 @@
#include "sdxlemur-pcie.dtsi"
#include "sdxlemur-blsp.dtsi"
#include "sdxlemur-audio.dtsi"
#include "sdxlemur-thermal.dtsi"

5
qcom/shima-audio-overlay.dtsi
View file

@ -69,6 +69,11 @@
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <1>;
qcom,swr-phy-dev-addr = <0x0D 0x01170223>,
<0x08 0x58350223>,
<0x08 0x58350222>,
<0x08 0x58350221>,
<0x08 0x58350220>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
wcd938x_tx_slave: wcd938x-tx-slave {

8
qcom/shima-coresight.dtsi
View file

@ -107,7 +107,9 @@
coresight-name = "coresight-tmc-etf";
coresight-csr = <&swao_csr>;
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0_swao &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <1>;
clocks = <&aopcc QDSS_CLK>;
clock-names = "apb_pclk";
@ -154,7 +156,9 @@
qcom,sw-usb;
coresight-name = "coresight-tmc-etr";
coresight-ctis = <&cti0 &cti6>;
coresight-ctis = <&cti0 &cti3_swao>;
cti-reset-trig-num = <0>;
cti-flush-trig-num = <3>;
coresight-csr = <&csr>;
clocks = <&aopcc QDSS_CLK>;

25
qcom/shima-idp.dtsi
View file

@ -189,7 +189,9 @@
&dsi_r66451_amoled_video
&dsi_r66451_amoled_60hz_video
&dsi_r66451_amoled_60hz_cmd
&dsi_r66451_amoled_144hz_cmd>;
&dsi_r66451_amoled_144hz_cmd
&dsi_r66451_amoled_video_cphy
&dsi_r66451_amoled_cmd_cphy>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
@ -197,6 +199,27 @@
focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
atmel_mxt_ts@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&tlmm>;
interrupts = <23 0x2008>;
avdd-supply = <&L3C>;
vdd-supply = <&L8C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
atmel,xy_switch;
atmel,inverty;
atmel,invertx;
reset-gpios = <&tlmm 22 0x00>;
irq-gpios = <&tlmm 23 0x2008>;
atmel,panel-coords = <0 0 479 799>;
atmel,display-coords = <0 0 339 729>;
panel = <&dsi_sharp_qhd_plus_dsc_cmd>;
};
};
&dai_mi2s2 {

13
qcom/shima-pcie.dtsi
View file

@ -33,7 +33,7 @@
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0_msi_snps>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 94 0>;
wake-gpio = <&tlmm 96 0>;
@ -67,7 +67,7 @@
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
@ -194,15 +194,6 @@
};
};
pcie0_msi_snps: qcom,pcie0_msi@a0000000 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0xa0000000 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
qcom,snps;
};
pcie0_msi: qcom,pcie0_msi@17a10040 {
compatible = "qcom,pci-msi";
msi-controller;

4
qcom/shima-pm.dtsi
View file

@ -44,8 +44,8 @@
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
arm,psci-suspend-param = <0x2240>;
qcom,psci-mode = <0x224>;
arm,psci-suspend-param = <0x2340>;
qcom,psci-mode = <0x234>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;

93
qcom/shima-qrd.dtsi
View file

@ -197,6 +197,99 @@
qcom,wireless-fw-name = "idt9412.bin";
};
&thermal_zones {
quiet-therm-step {
polling-delay-passive = <2000>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>;
trips {
quiet_gpu_trip: quiet-gpu-trip {
temperature = <45000>;
hysteresis = <0>;
type = "passive";
};
quiet_cpu4_trip: quiet-cpu4-trip {
temperature = <46000>;
hysteresis = <0>;
type = "passive";
};
quiet_cpu7_trip: quiet-cpu7-trip {
temperature = <48000>;
hysteresis = <0>;
type = "passive";
};
quiet_cpu0_trip: quiet-cpu0-trip {
temperature = <50000>;
hysteresis = <0>;
type = "passive";
};
quiet_cx_trip: quiet-cx-trip {
temperature = <55000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
gpu-cdev0 {
trip = <&quiet_gpu_trip>;
/* throttle to 443000000Hz */
cooling-device = <&msm_gpu THERMAL_NO_LIMIT
(THERMAL_MAX_LIMIT-1)>;
};
gpu-cdev1 {
trip = <&quiet_cx_trip>;
/* throttle to 285000000Hz */
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
cpufreq0-cdev {
trip = <&quiet_cpu0_trip>;
/* throttle to 1516800KHz */
cooling-device = <&CPU0 THERMAL_NO_LIMIT
(THERMAL_MAX_LIMIT-7)>;
};
cpufreq4-cdev {
trip = <&quiet_cpu4_trip>;
/* throttle to 1651200KHz */
cooling-device = <&CPU4 THERMAL_NO_LIMIT
(THERMAL_MAX_LIMIT-5)>;
};
cpufreq7-cdev {
trip = <&quiet_cpu7_trip>;
/* throttle to 1862400KHz */
cooling-device = <&CPU7 THERMAL_NO_LIMIT
(THERMAL_MAX_LIMIT-5)>;
};
cdsp-cdev {
trip = <&quiet_cx_trip>;
cooling-device = <&cdsp_sw 5 5>;
};
modem-pa-cdev {
trip = <&quiet_cx_trip>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&quiet_cx_trip>;
cooling-device = <&modem_tj 3 3>;
};
};
};
};
&qupv3_se10_i2c {
#address-cells = <1>;
#size-cells = <0>;

6
qcom/shima-qupv3.dtsi
View file

@ -29,7 +29,8 @@
<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
<MASTER_QUP_0 SLAVE_EBI1>;
iommus = <&apps_smmu 0x4c3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
};
@ -362,7 +363,8 @@
<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
<MASTER_QUP_1 SLAVE_EBI1>;
iommus = <&apps_smmu 0x43 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
};

4
qcom/shima-regulators.dtsi
View file

@ -382,9 +382,9 @@
pm8350c_s2: regulator-pm8350c-s2 {
regulator-name = "pm8350c_s2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <722000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
qcom,init-voltage = <722000>;
qcom,init-voltage = <550000>;
};
};

257
qcom/shima-thermal.dtsi
View file

@ -64,6 +64,44 @@
"msm_skin_therm";
};
};
mx_sdpm@0x00636000 {
compatible = "qcom,sdpm";
reg = <0x00636000 0x1000>;
clock-names = "cam_cc_ipe", "video_cc_mvs0";
clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>;
video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>;
csr-id = <1 3>;
};
cx_sdpm@0x00634000 {
compatible = "qcom,sdpm";
reg = <0x00634000 0x1000>;
clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp";
clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>;
video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>;
disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>;
csr-id = <0 2 5>;
};
mx_pe: mx_rdpm_pe@0x00637000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00637000 0x1000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
};
cx_pe: cx_rdpm_pe@0x00635000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00635000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
};
};
&cpufreq_hw {
@ -153,6 +191,14 @@
};
};
qcom,limits-dcvs {
compatible = "qcom,msm-hw-limits";
isens_vref_0p8-supply = <&pm8350c_l10_ao>;
isens-vref-0p8-settings = <880000 880000 30000>;
isens_vref_1p8-supply = <&pm8350c_l1_ao>;
isens-vref-1p8-settings = <1800000 1800000 20000>;
};
qcom,cpu-voltage-cdev {
compatible = "qcom,cc-cooling-devices";
apc1_cluster: qcom,apc1-cluster {
@ -1254,18 +1300,12 @@
};
nspss-0-step {
polling-delay-passive = <10>;
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 3>;
trips {
nspss0_trip0: nspss0-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss0_trip1: nspss0-trip1 {
nspss0_trip: nspss0-trip {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
@ -1273,49 +1313,37 @@
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss0_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss0_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
cdsp-cdev {
trip = <&nspss0_trip>;
cooling-device = <&cdsp_sw 5 5>;
};
gpu_cdev {
trip = <&nspss0_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
trip = <&nspss0_trip>;
/* throttle to 285000000Hz */
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
modem-pa-cdev {
trip = <&nspss0_trip1>;
trip = <&nspss0_trip>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss0_trip1>;
trip = <&nspss0_trip>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-1-step {
polling-delay-passive = <10>;
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 4>;
trips {
nspss1_trip0: nspss1-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss1_trip1: nspss1-trip1 {
nspss1_trip: nspss1-trip {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
@ -1323,49 +1351,37 @@
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss1_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss1_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
cdsp-cdev {
trip = <&nspss1_trip>;
cooling-device = <&cdsp_sw 5 5>;
};
gpu_cdev {
trip = <&nspss1_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
trip = <&nspss1_trip>;
/* throttle to 285000000Hz */
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
modem-pa-cdev {
trip = <&nspss1_trip1>;
trip = <&nspss1_trip>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss1_trip1>;
trip = <&nspss1_trip>;
cooling-device = <&modem_tj 3 3>;
};
};
};
nspss-2-step {
polling-delay-passive = <10>;
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&tsens1 5>;
trips {
nspss2_trip0: nspss2-trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
nspss2_trip1: nspss2-trip1 {
nspss2_trip: nspss2-trip {
temperature = <100000>;
hysteresis = <5000>;
type = "passive";
@ -1373,34 +1389,135 @@
};
cooling-maps {
cdsp-cdev0 {
trip = <&nspss2_trip0>;
cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
cdsp-cdev1 {
trip = <&nspss2_trip1>;
cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
cdsp-cdev {
trip = <&nspss2_trip>;
cooling-device = <&cdsp_sw 5 5>;
};
gpu_cdev {
trip = <&nspss2_trip1>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
(THERMAL_MAX_LIMIT-1)>;
trip = <&nspss2_trip>;
/* throttle to 285000000Hz */
cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
THERMAL_MAX_LIMIT>;
};
modem-pa-cdev {
trip = <&nspss2_trip1>;
trip = <&nspss2_trip>;
cooling-device = <&modem_pa 3 3>;
};
modem-tj-cdev {
trip = <&nspss2_trip1>;
trip = <&nspss2_trip>;
cooling-device = <&modem_tj 3 3>;
};
};
};
};
mx-pe-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&mx_pe>;
thermal-governor = "step_wise";
trips {
mx_pe_config1: mx-pe-config1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
mx_pe_config2: mx-pe-config2 {
temperature = <2>;
hysteresis = <1>;
type = "passive";
};
mx_pe_config3: mx-pe-config3 {
temperature = <3>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
mx_pe_cdev_1 {
trip = <&mx_pe_config1>;
cooling-device = <&cdsp_sw 0 0>;
};
mx_pe_cdev_2 {
trip = <&mx_pe_config2>;
cooling-device = <&msm_gpu 0 0>;
};
mx_pe_cdev_3 {
trip = <&mx_pe_config3>;
cooling-device = <&modem_tj 0 0>;
};
};
};
cx-pe-step {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&cx_pe>;
thermal-governor = "step_wise";
trips {
cx_pe_config1: cx-pe-config1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config2: cx-pe-config2 {
temperature = <2>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config3: cx-pe-config3 {
temperature = <3>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config4: cx-pe-config4 {
temperature = <4>;
hysteresis = <1>;
type = "passive";
};
cx_pe_config5: cx-pe-config5 {
temperature = <5>;
hysteresis = <2>;
type = "passive";
};
};
cooling-maps {
cx_pe_cdev_1 {
trip = <&cx_pe_config1>;
cooling-device = <&cdsp_sw 0 0>;
};
cx_pe_cdev_2 {
trip = <&cx_pe_config2>;
cooling-device = <&cdsp_sw 0 0>;
};
cx_pe_cdev_3 {
trip = <&cx_pe_config3>;
cooling-device = <&cdsp_sw 0 0>;
};
cx_pe_cdev_4 {
trip = <&cx_pe_config4>;
cooling-device = <&modem_tj 0 0>;
};
cx_pe_cdev_5 {
trip = <&cx_pe_config5>;
cooling-device = <&cdsp_sw 0 0>;
};
};
};
};

32
qcom/shima.dtsi
View file

@ -537,7 +537,8 @@
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x3d0>;
iommus = <&apps_smmu 0x2026 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
@ -2373,6 +2374,16 @@
&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
};
cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "compute";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
@ -2549,6 +2560,15 @@
qcom,core-dev-table = <&cpu7_cpu_l3_tbl>;
};
cpu7_l3_computemon: qcom,cpu7-l3-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_latfloor>;
qcom,core-dev-table =
< 2169600 300000000 >,
< 2707200 1420800000 >;
};
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
@ -3484,8 +3504,9 @@
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
reg = <0xb0000000 0x10000>,
<0xb2e5510 0x690>;
reg-names = "smmu_iova_ipa", "tcs_cmd";
wlan-en-gpio = <&tlmm 64 0>;
qcom,bt-en-gpio = <&tlmm 65 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
@ -3494,6 +3515,9 @@
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x420000>;
qcom,wlan-cbc-enabled;
/* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */
qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>;
cnss-enable-self-recovery;
vdd-wlan-aon-supply = <&S2C>;
qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
@ -3738,8 +3762,6 @@
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
qcom,tx-wrapper-cache-max-size = <400>;
/* Entry will be removed once shadow stack changes checked-in */
qcom,ipa-wan-aggr-pkt-cnt = <2>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;

14
qcom/sm8150-cdp-overlay.dts
View file

@ -1,14 +0,0 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sm8150-cdp.dtsi"
/ {
model = "CDP";
compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp";
qcom,board-id = <1 0>;
};

10
qcom/sm8150-cdp.dts
View file

@ -1,10 +0,0 @@
/dts-v1/;
#include "sm8150.dtsi"
#include "sm8150-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8150 CDP";
compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp";
qcom,board-id = <1 0>;
};

2
qcom/sm8150-cdp.dtsi
View file

@ -1,2 +0,0 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

20
qcom/yupik-ion.dtsi Normal file
View file

@ -0,0 +1,20 @@
#include <dt-bindings/arm/msm/msm_ion_ids.h>
&soc {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
system_heap: qcom,ion-heap@25 {
reg = <ION_SYSTEM_HEAP_ID>;
qcom,ion-heap-type = "MSM_SYSTEM";
};
system_secure_heap: qcom,ion-heap@9 {
reg = <ION_SECURE_HEAP_ID>;
qcom,ion-heap-type = "SYSTEM_SECURE";
};
};
};

28
qcom/yupik-pinctrl.dtsi
View file

@ -8,5 +8,33 @@
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qupv3_se5_2uart_pins: qupv3_se5_2uart_pins {
qupv3_se5_2uart_active: qupv3_se5_2uart_active {
mux {
pins = "gpio22", "gpio23";
function = "qup05";
};
config {
pins = "gpio22", "gpio23";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep {
mux {
pins = "gpio22", "gpio23";
function = "gpio";
};
config {
pins = "gpio22", "gpio23";
drive-strength = <2>;
bias-pull-down;
};
};
};
};
};

12
qcom/yupik-pm.dtsi
View file

@ -37,15 +37,15 @@
qcom,min-child-idx = <2>;
};
CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */
CX_RET: qcom,pm-cluster-level@2 { /* Cx Ret */
reg = <2>;
compatible = "arm,idle-state";
idle-state-name = "cx-off";
idle-state-name = "cx-ret";
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
arm,psci-suspend-param = <0x2240>;
qcom,psci-mode = <0x224>;
arm,psci-suspend-param = <0x1340>;
qcom,psci-mode = <0x134>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;
@ -58,8 +58,8 @@
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9826>;
arm,psci-suspend-param = <0xc340>;
qcom,psci-mode = <0xc34>;
arm,psci-suspend-param = <0xb340>;
qcom,psci-mode = <0xb34>;
qcom,is-reset;
qcom,notify-rpm;
qcom,min-child-idx = <2>;

35
qcom/yupik-qupv3.dtsi Normal file
View file

@ -0,0 +1,35 @@
#include <dt-bindings/interconnect/qcom,yupik.h>
&soc {
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9c0000 0x2000>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
<MASTER_QUP_0 SLAVE_EBI1>;
iommus = <&apps_smmu 0x123 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
};
/* Debug UART Instance */
qupv3_se5_2uart: qcom,qup_uart@994000 {
compatible = "qcom,msm-geni-console";
reg = <0x994000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_2uart_active>;
pinctrl-1 = <&qupv3_se5_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok"
};
};

5
qcom/yupik-rumi.dtsi
View file

@ -70,3 +70,8 @@
status = "ok"
};
/* Debug UART console */
&qupv3_se5_2uart {
qcom,rumi_platform;
};

314
qcom/yupik.dtsi
View file

@ -335,7 +335,9 @@
soc: soc { };
chosen { };
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
};
&soc {
@ -837,6 +839,313 @@
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-nsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-wpss {
compatible = "qcom,smp2p";
qcom,smem = <617>, <616>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <13>;
wpss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wpss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
qcom,modem_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_wpss>;
};
};
glink_adsp: adsp {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_cdsp>,
<&glink_wpss>;
};
};
glink_cdsp: cdsp {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "dsps_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,cdsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_wpss>;
};
};
glink_wpss: wpss {
qcom,remote-pid = <13>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "wpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "wpss";
qcom,glink-label = "wpss";
qcom,wpss_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,wpss_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_adsp>,
<&glink_cdsp>;
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "aop_qmp";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0xc300000 0x400>;
reg-names = "msgram";
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
};
};
#include "shima-gdsc.dtsi"
@ -961,3 +1270,6 @@
};
#include "yupik-usb.dtsi"
#include "yupik-ion.dtsi"
#include "msm-arm-smmu-yupik.dtsi"
#include "yupik-qupv3.dtsi"