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Merge "ARM: dts: msm: add MX entries to qcom,bw-scale for PCIe on shima"

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This commit is contained in:
qctecmdr 2020-11-23 23:23:26 -08:00 • committed by Gerrit - the friendly Code Review server
commit f4da5787aa
3 changed files with 60 additions and 17 deletions
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29
bindings/pci/pci-msm.txt
View file

@ -123,6 +123,7 @@ Main node
- "vreg-1.8-supply" power supply for PCIe PHY
- "vreg-0.9-supply" power supply for PCIe PHY
- "vreg-cx-supply" power supply for PCIe core
- "vreg-mx-supply" power supply for PCIe core/PHY
- "vreg-3.3-supply" (opt) power supply for PCIe endpoint
- qcom,<supply-name>-voltage-level:
@ -134,8 +135,10 @@ Main node
- qcom,bw-scale:
Usage: optional
Value type: <prop-encoded-array>
Definition: List of CX voltage corner and rate change clock frequency
pair for each PCIe GEN speed
Definition: Tuple consisting of CX and MX voltage corners, and rate
change clock frequencies for each supported PCIe Gen speed.
ex:
<[min CX voltage] [min MX voltage] [Rate change clk frequency]>
interconnect-names:
Usage: optional
@ -474,14 +477,30 @@ Example
vreg-1.8-supply = <&pm8150l_l3>;
vreg-0.9-supply = <&pm8150_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
vreg-3.3-supply = <&pm8150_l1>;
qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000
/* Gen4 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

32
qcom/lahaina-pcie.dtsi
View file

@ -53,10 +53,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
@ -284,10 +292,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;

16
qcom/shima-pcie.dtsi
View file

@ -53,10 +53,18 @@
qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale =
<RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;