Add "dynamic-power-coefficient" property to all cores.
The "capacity-dmips-mhz" and "dynamic-power-coefficient"
are used to build Energy Model which in turn used by EAS to
take placement decisions.
Change-Id: I56f0f7bd6a623dcfd2cbf2dca370681011aa876b
Add "dynamic-power-coefficient" property to all cores.
The "capacity-dmips-mhz" and "dynamic-power-coefficient"
are used to build Energy Model which in turn used by EAS to
take placement decisions.
Change-Id: I9cc9f97116b5aa9cdf9f3b6e250b30a170db910c
Accumulative cycle counters are not supported, cycle counter needs
to be read from the core-0 of the frequency domain.
Add property to indicate the same.
Change-Id: I503c4470824d29ee95a3c39a172ec716be77c61b
Enlarge the minidump cma area due to a number of new DTSI nodes
(mainly related to CPU cache minidumps) have been added, which
require more space.
Change-Id: I8826f367433c6a26c5f1538166c4edc592996eb3
When unmapping memory, the SMMU driver must access the GPU SMMU's
register space, so it must vote for power resources to access the TLB
invalidation registers. When the GPU is in slumber, there aren't votes
for the GPU SMMU's power resources, so the SMMU driver constantly ends
up enabling/disabling the power resources, which takes a considerable
amount of time. When paired with the suboptimal IOMMU page table
management code, this leads to performance issues where the time taken
to unmap memory is large.
Thus, for all targets that support GKI, add the qcom,power-always-on
property for the GPU SMMUs of these targets, to remove the latency
incurred by having to enable/disable power resources in the GKI
configuration.
Change-Id: I403c9864705c50f7ce8b1118c3c75902708e647b
If there is a switch connected to PCIe root complex, the
devicetree hierarchy needs to correctly reflect the physical
connection. Add pci DT nodes for each switch device such as
switch upstream and downstream ports for sdxlemur CPE.
Change-Id: I04ddd33adc67f0ec689d014cd00ed5fa26d02a89
Additional BDF to SID mappings are needed if a switch and
mutliple endpoints are connected to PCIe root complex. Expand
iommu-map for PCIe on sdxprarie CPE to support such a usecase.
Change-Id: Id7643ab574b1472649bb70121da70a40f31c806c
Replace deprecated PCIe DT entry for PCIe AUX clock controller
setting with the correct entry and value. PCIe core controller
requires AUX clock to be 19.2MHz.
Change-Id: Ia670d8e75f75939c2798d795e21771402d83569c
