Add support for encoder complexity handling.
Enable lowpower mode if the complexity is 0.
Change-Id: Ife290b377c844e5b1d3be93b2509c787f8e05c59
Signed-off-by: Santhosh Behara <santhoshbehara@codeaurora.org>
Division(/) and modulus(%) are failed to link on 32-bit kernel.
To resolve the linker error, use API for division and modulus which
are available for both 32bit and 64bit architecture.
Change-Id: Ib45b993c5ec4eee45d5f50e0d7b6d4831c256d8c
refbufs should be destroyed in vidc close.
CRs-Fixed: 2846268
Change-Id: Ic36b7ac824a6c46524b0c4f0ca364e9c87f015ba
Signed-off-by: Laisheng Hu <laisheng@codeaurora.org>
While accepting a video session, keep a check
for frame height w.r.t maximum capability.
CRs-Fixed: 2883699
Change-Id: I068dd9af868093dbdddf0301d8d40a95643314e0
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Release the existing scratch buffers instead of reuse,
provided the new buffer requirements is of size zero.
For ex, scratch buffer for interlace clips is zero.
Change-Id: Ic540839f1b5f8063ae5a1e4eda6df90b60b49af5
For HLG HDR recording, client won't set HDR10 SEI,
and driver shouldn't set this info to firmware either.
Otherwise some applications may have wrong behavior
when HDR10 SEI is present in HLG clips.
Change-Id: I7a054ded39e3b9309d823e97da039f0de1bcde9d
Signed-off-by: Qiwei Liu <qiweil@codeaurora.org>
Automation scripts expects work_mode and low_latency config
related debug prints to evaluate testcase pass/fail. So
added debug prints for holi.
Change-Id: I8ab051e0efbb8c8e78a9085e2fc79e7fe43e9c99
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
Increase 10-bit enc bistream buffer size for <=360p.
For 8-bit YUV size : w x h x 1.5
For 10-bit YUV size : w x h x 1.5 x 2
Change-Id: I6fddcf960b8b06fe6edbe4b8262374303a045530
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
For DCVS, there are mainly 3 buffer count watermarks
i.e low, normal, high. When the buffers held with firmware
goes above high or below low, DCVS changes the clock to
high or low respectively.
At this state, to come back to normal clock, it needs the buffer
in firmware to come back to normal count. For cases, when DCVS
decides to decrease the clock, the clock remains lowered till
the buffer count in firmware is back to normal. During this
phase, the clock remains low and impacts performance. Since
encode usecase always desire more clock, keeping low for them
leads to measurable impact.
The fix considers a case for encoder to bring back to normal
clock when the buffer count is more than low watermark.
CRs-Fixed: 2845570
Change-Id: I426a17f7b16db544ea09ec072c77e95198634c84
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Update offset from 14 to 21 for yupik fmax fuse.
IRIS_PLL_FMAX: Limits the enc/dec capability to
4k@30.
Change-Id: I60dc110e85a5aa7d4427424b401b759e49d345ac
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
Update clock data frame rate to client's set value
for mbps calculation so as to reject sessions out of
mbps capability.
Change-Id: I62559172b71fb4d2e911c16be7f07110e53f23a1
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
[1] num_ref for hierp has to be calculated only if
max_layer value is > 1. Since max_layer value
0/1 indicates absence of layer encoding.
[2] Fix hybrid_hp num_ref calculation inline with
FW calc.
Change-Id: I507d58c33529e5976974cc2d5a6e2d3fd8c55026
Limit auto frame rate to [1,platform frame rate capability]
before sending to firmware.
Change-Id: I96dc4b8d76b7752a76f6c15dcb6b20817857372f
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
While processing the response from video hardware, video
driver is accessing a register which does not exist. It
is even not needed for functionality purpose. Removing
the access for the same.
Change-Id: Ib4fec718d2f057860878bf8928b96fb46be47b13
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
