DCS commands triggered right after timing engine enable can conflict
with blanking period causing command transfer failures. Right after
timing engine enable poll for frame start and line count reaching
active region of display before any DCS commands.
Change-Id: Ia3967e01c3bb5bc82aa3549c300fa8335e00210c
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.So remove clearing cur_master in
encoder enable function to avoid the race condition between modeset
and irq callback.
Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Canceling delayed_off_work in encoder pre_modeset might not be
executed in all cases, but the following encoder enable might
initialize the work.
This will lead to list corruption as delayed_off work list node
is reinitialized before removing from linked list.
Move canceling delayed_off_work to start of encoder mode_set to
ensure work is canceled before reinitialization.
Change-Id: I38687604f2eedced308ea02019c162022725534e
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
During DMS, when tear check registers are updated near
rd_ptr line count, it was resulting in a spurious
rd_ptr_irq to which frame is getting latched and causing
tearing on the screen. This change updates
TEAR_SYNC_WRCOUNT register before disabling the vsync
counter and adds a spinlock to avoid pre-emption.
Change-Id: I986dc3ce6fb3da5fed758c2f50562df44f2ab557
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change updates the single buffer tear check registers
when vsync_in is disabled. It allows mode switch frame
trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change removes tx_wait during DMS for targets which have
dsc_hw_rev_2. For targets with dsc_hw_rev_1, during DMS the
tx_wait is needed since DSC registers are not double buffered
and frame trigger needs to be serialized to avoid pp_timeout
issues.
Change-Id: I46479ed8713602d167e57c9d9d0f800f544607f2
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Avoid irq enable/disable during modeset and trigger
frame as posted start frame. This saves mode_set time
and also avoids unbalanced vblank_irq in this usecase.
Change-Id: I06958da5e52bc2aca0ddc60d2783615f80a839a4
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently RSC timer register programming is optimized for updating
only during timing param changes and not during RSC state changes
with same timing. Static wakeup time computation should consider
panel jitter for RSC clk state too, else it can result in RSC hang.
This change also removes extra logic for video mode prefil lines
computation for rsc config as video mode does not enable RSC solver.
Current issue scenario exposing the hang is in dual dsi display scenario
where RSC is in clock state and static wakeup time is programmed by
not considering panel jitter, after suspend/pmsuspend while waking up
if RSC switches to command state if primary enabled first and vsync
may arrive much early based on the panel jitter. RSC hw can not handle
if TE arrives earlier than static wakeup time causing RSC hang.
Change-Id: I1434fdd71eb04fdbe22b3601500493c818e9126d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The DMA buffer allocation for DSI happens during the first
command transfer. This change moves this allocation to happen during
bind.
Change-Id: I7969a019a8b84282e8a153f5393c9a3de5a28043
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.
Change-Id: I9e31dc00b3b79c12b0bcf51da21eb216746794a6
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Add HW recommended programming sequence when PHY
is allowed to turn off during idle state.
Change-Id: Icdd50d5ebc338842a6629ec08fc0ef35453e1052
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
In case of broadcast, for master controller, DMA_DONE bit gets
cleared in dsi_ctrl_isr and for slave controller it gets cleared
in clear_slave_dma_status. Current implementation checks
DSI_CTRL_CMD_BROADCAST_MASTER flag to decide if it's slave or not.
But, in the case of unicast, this flag is not set, leading to
the unnecessary poll for clear_slave_dma_status for all unicast
command transfers.
Add a check to call clear_slave_dma_status only when the current
command is broadcast on slave controller.
Change-Id: I7156f8c12ec779b41dafc8fc67639814957ee51b
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
This change depends on HAL change which sets CONNECTOR_SET_CRTC
property to null for cwb conn, if cwb is enabled during power off commit.
This causes power off commit crtc_state's active_changed and
connectors_changed set to true, which is causing seamless_crtc
to true during msm_disable_outputs and this leads to invalid crtc
state. This change modifies the seamless_crtc condition and
the msm_crtc_set_mode callback is early returned during such cases
to power off crtc.
Without this change, during power on commit crtc_duplicate_state
is causing cwb to turn on and the release fence is being created with
+2 offset in such case, leading to late release fence signalling and
further GPU fence timeouts.
Change-Id: Ibe87a8c0e8083d619ee6f502b2a946e1e8ef5553
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
During the sde_irq_update, the sde irq may not be active, the enable
or disable will be nonsence. set the irq_num init value to negtive, if
this value change, means sde irq_num has been initial.
Change-Id: I7b23c662ccc9db0b38550897adb939305d941e6a
Signed-off-by: longzhao <longzhao@codeaurora.org>
In ASYNC wait mode, next command kickoff can happen before previous
command ISR execution is completed in below sequence:
ASYNC command A -> triggered
dsi_ctrl_isr for command A -> fired and executed
atomic_set(&dsi_ctrl->dma_irq_trig, 1);
wait_for_done for command A -> returns early as
dsi_ctrl->dma_irq_trig is 1
ASYNC Command B -> triggered
wait_for_done for command B -> waiting for cmd_dma_done
dsi_ctrl_isr for command A -> executes
complete_all(&dsi_ctrl->irq_info.cmd_dma_done);
wait_for_done for command B -> returns success incorrectly based on
complete_all of previous command isr and disable_status_interrupt()
is not called.
This leads to refcount of dma_done going wrong and dsi_ctrl_isr is not
enabled on suspend resume.
To fix this issue, mark command transfer successful only based on
complete_all(cmd_dma_done). This way disable_status_interrupt() will be
always called either from dsi_ctrl_isr or wait_for_done().
Change-Id: I0379ea7ff82a1e077b95f6996d11d1722de00936
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Skip backlight updates and panel off commands
during twm entry.
Change-Id: I7656fa0d513a8a3e82d9bbbf5c3f85c1b84ee9da
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
Add sysfs node on connector to get twm enable
state. This node is used by the HAL to notify TWM
entry and exit.
Change-Id: I56a844076014c2e12075756f6b1bc42b91b48ad1
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
Add sysfs node on connecter to get the panel power state.
This node is used by the HAL to read display power state.
Change-Id: I717e4b87513a845c867871f93876fc7c88ff7b2f
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
During suspend commit, crtc_commit thread is blocked waiting
for touch response in drm_panel_notifier_call_chain and
rsvp_nxt pointer clear in drm_atomic_state_put is pending
(>100ms wait) which was allocated in atomic_check. When
resume commit is triggered early, RM poll timeouts are seen
due to rsvp_nxt pointer is not cleared and thus causing
power on commit failures. This change avoids RM reserve
during atomic_check of suspend commit as msm_crtc_set_mode
returns early and rsvp_nxt is not used elsewhere in commit path.
Change-Id: I4e7bb41d38f5b88ee75f63007dc4403b6b903265
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
This change removes ubwc formats from input and output
for the holi and blair target which do not support
ubwc for offline roation.
Change-Id: I34f8f3e6db5e7f8f63bb3948c69f810342b7c0ea
Signed-off-by: Mahadevan <mahap@codeaurora.org>
This change parses new dt property CWB_MIXER_MASK, which signifies
the compatible mixer_mask for the corresponding CWB block.
During mixer allocation for CWB usecase, we use this cwb_mixer_mask
to decide compatible mixers for built-in primary and secondary displays.
In the current issue case, mixer allocation is as below in
multi display usecase:
primary: LM0
secondary: LM1
external: LM2
RM loops through available mixers and tries to allocate LM3 when
CWB is triggered on primary display. But from HW perspective,
LM0 is not muxed to LM3 causing wb timeouts. With current change
LM3 gets skipped and LM4 gets allocated.
Change-Id: I95ce16a083c9b9976a9dff309d7754085ee08958
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Avoid pr_err and use SDEROT macros for console
logging.
Change-Id: I4c0c6cf1d482a55f82c73572b1327695b85c5501
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Do not call devm_clk_put() if devm_clk_get() was failed for
a given clk. The devm_clk_put() does not check for the validity
of the input clk argumnet, and can cause NULL pointer dereference
or some other errors if called with invalid clk argument.
Change-Id: Ie626a5afed52a146ebd1a2092c7d9db9226dbfe0
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Add changes to disable CWB crop params as part of writeback
disable.
Change-Id: I18582ceb502e759ec4b67568562ac95ff3f0d359
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
On rotator commit failure resync timeline will
happen which gives continuous warning logs in
console leads to cpu throttling. To resolve this
the warning message is removed from spin_lock.
Change-Id: I5ce66413556518668769cad3bc6a900f9bdada4b
Signed-off-by: Mahadevan <mahap@codeaurora.org>
Access file private data structures inside the
mutex lock only to avoid use-after-free issues.
Change-Id: If70731f517bcb47d4515f131fecafe702064cb45
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
During lp2 state the load on the panel and
controller regulators can be reduced. Configure ldos
in optimum mode during this state.
Change-Id: I75c180f28f636ebb23ecbe9679ba89c00977fe0f
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
In dual display usecase when both displays comes out of
idle following scenario will cause wr_ptr timeout.
1. Both displays goes to idle and RSCC enters Mode-2.
2. Primary display exit idle upon DRM commit N RSC
enters Solver State.
3. Secondary display exits idle upon DRM commit M and
waits on input fence after CTL_1_PREPARE is set.
RSC is still in CMD state.
4. Primary Commit N frame transfer got successful and
commit N+1 is queued in primary display when RSC
in solver state which leads to timeout in primary.
This is because RSCC will not generate a wakeup in sync with
primary timelines leading to timeout. This is because RSCC
still sees idle low thinking frame transfer is taking long
time. This change will switch the rsc state to AMC mode
before CTL_PREPARE is set which resolves such issue.
Change-Id: Ic32e48b4febbbcc54d94876194d38fe6ef3d0981
Signed-off-by: Mahadevan <mahap@codeaurora.org>
This change adds required checks to avoid accessing null pointer
where debug bus is not initialised and dumping the debug bus points.
Change-Id: Ia46a4b95706f05e37be660f006c04b1e2e9f6848
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Currently, disabled timing child nodes or power supply nodes are
not skipped because of which status = "disabled" entry does not
work for child nodes. Use of_get_next_available_child to skip
disabled child nodes.
Change-Id: Ib6e4b655f83dd0ee3ffddd496976c34030fa3dc0
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
