Configure the IPCC summary IRQ as wakeup capable interrupt.
IPCC interrupt needs to wake up the device from low power
modes when wakeup capable event is generated from remote
subsystem.
Change-Id: Iaffefc6ef68743c7de11062c39e2b1453c58b9a1
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
[eberman@codeaurora.org: Resolve merge conflicts]
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
Add check of trace unit power property to enable/disable that
keep the trace unit powered.
Change-Id: I66dbfee16df63480c9309092e61ee39b8b0cd6e8
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Since the tcs_in_use flag is authoritative enough to determine the
idleness of the TCS, avoid reading the register redundantly.
Change-Id: Ic7737e60ca0029b3cf9d1cc9e613435608be7bc8
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
For RSCs that have sleep & wake TCS but no dedicated active TCS, wake
TCS can be re-purposed to send active requests. Once the active requests
are sent and response is received, the active mode configuration needs
to be cleared so that controller can use wake TCS for sending wake
requests in 'solver' state while executing low power modes.
Change-Id: I0d15c290db48d08158fdbff2cd91505563dc3fd5
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware and as such are not
available for sending active votes. Device driver may notify RPMH API
that the controller is in solver mode and when in such mode, disallow
requests from platform drivers for state change using the RSC.
Change-Id: I6dccfabdf230d927b945b0bd1840233e69064c9d
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
When triggering a TCS to send its contents, reading back the trigger
value may return an incorrect value. That is because, writing the
trigger may raise an interrupt which could be handled immediately and
the trigger value could be reset in the interrupt handler.
A write_tcs_reg_sync() would read back the value that is written and try
to match it to the value written to ensure that the value is written,
but if that value is different, we are stuck in loop forever.
Change-Id: I54866b9b9d85fa79c8df84aecd502764b9f9158a
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Add support to new register memory map, fix loop offset and
dynamic number of link list.
Change-Id: Ibadfa723842dae80cdd50bf08018d86c2ef30b94
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Add dt binding head file for dcc driver. It's used by device tree
to define dcc link list.
Change-Id: Iacbfeeb2cf2763608f075f2828a8d47d662fa88f
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Add qseecom.h, qcedev.h, fips_status.h for Lahaina bring up
Change-Id: I21c1747e7ce9fab1d190b8ea54ac2d54c11bd44f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
If the clock rate is set previously to hlos and enable
safe config is true. In that case we need to check the
rcg source to make sure recalc will return correct rate.
Rate calculation is done based on selected source rather
than 19.2 MHZ. Also, we are setting correct src value for
XO based on the parent map of a particular clock.
Change-Id: Id6d2923136a0848d55cff37fb5ef2e3b092af27a
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
There could be cases where a simultaneous clk_disable and clk_set_rate on
the same rcg could result in a wrong recalc rate. So for shared rcgs
get the pre_div value based on the current frequency from the frequency
table.
Change-Id: Ia5730e43965b2d0ba19da05fca47825514f98865
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has
additional KHz of frequency. Due to this additional frequency, the
source is wrongly selected. Truncate the additional KHz using the
DIV_ROUND_CLOSEST_ULL.
Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Add null pointer checks for the parent clock pointers returned
by clk_hw_get_parent() and clk_hw_get_parent_by_index() in
several qcom clock drivers.
Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97
Signed-off-by: David Collins <collinsd@codeaurora.org>
Move reading of MN counter mode register earlier to source sel
to fix overwrite of MN counter mode variable.
Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Update the DEFINE_RCG_DFS() macro to avoid the potential clock
struct name aliasing.
This modification originally came from:
commit c88b8062898c ("clk: qcom: Add cdiv clocks for gcc, video
and camera cc driver for KONA").
Change-Id: I5a8b694b5b8a8b5169639a3e09b1ab4c1936e010
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add clock ops for taking care of a dependent clock when the actual
clock requests are made.
Change-Id: I52691ef9f183da035ddf9c05fb73811f48fef74c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Fix certain functions with potential for a NULL
pointer de-reference.
Change-Id: I855ef1d883a22616db7086bd5d47ee1f8e54694a
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add new RCG clock ops specific for the DP clock source.
Change-Id: I2ec5ddcfd47af8362f76d76d153e30d4e2f45370
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some RCGs could have sources with dynamic frequencies and fixed sources
where if the RCG has the flag of CLK_SET_RATE_PARENT set, it would try to
propagate the clock rate to the fixed source PLLs too. To identify sources
of the RCGs where the rate should propagate to parent PLL, add a member in
freq_tbl to represent source frequency. This would be used by the
_freq_tbl_determine_rate to set its parent frequency on the PLL.
Change-Id: I7f1c0d9d84607821893a1e5d17934dae5acef5f4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, it is desirable for an RCG to be turned on
explicitly instead of just relying on the enable signal from
its branch clock(s). Add support for this.
Change-Id: I2b0b81bddfe7cc7543c313e4ed13a332fb1a0fcb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, an RCG might be prone to being enabled even
though the overlying software thinks that it disabled the RCG.
In order to avoid letting the RCG go into an invalid state, support
parking it at a safe frequency during clk_disable() and deferring
all the RCG configuration updates to be done during clk_enable(),
if a scaling request comes in whilst the clock is disabled.
Change-Id: I55f1d1d346182a2b480127c57d6659fc9a63331b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The sequence for alpha_pll_lucid_prepare is checking an incorrect bit
to determine whether or not a lucid PLL has calibrated successfully.
The bit in the status register is not observable unless pll_test_ctl[69]
is set and user_ctl[43:37] is 0 which should only be used as a fallback
option. Use the correct PCAL_DONE bit from the mode register to properly
determine PLL calibration status.
Change-Id: If952c30cacacd68c07e8d7dfd622069dbb70c909
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some instances of the Zonda PLL do not lock correctly
in high L-VAL regions. In such cases, CFA mode
can be configured via test_ctl_val to use an alternative
locking mechanism. Add support for CFA mode by
polling FREQ_LOCK_DET instead of PLL_DET_LOCK
whenever CFA mode has been configured.
Change-Id: Ief31592250ea9f329a34ffdbc4b17cfce431677d
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
