When switch mode with etr being enabled more than one time, it needs
to reset all the etr settings for previous mode instead of return busy.
Change-Id: I243a6d910bb3dd8ac9ca30dadbd1c6ab3cefd00f
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Agera PLL print registers are required to get the PLL values
from the debugfs, thus add support for the same.
Change-Id: I4b708958e1125ce7e8eab945a3c15113739230d4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Agera PLL is required to be supported from HLOS clock controller, thus
add support for agera pll ops.
Change-Id: I77b2a741667accf9bd0eecfcd0dabfaf7596345f
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Legacy FSM Mode is required to be set when the Fabia PLL needs to be
used in non-FSM mode, thus add support for same.
Change-Id: I23d491cb33391dce1eb21d9ced298001da9ef907
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Burst size must be printed in perf builds as it is a major
characteristic of the system.
Change-Id: I7e6013751333bb487e2d9422726e41b1050aca43
Signed-off-by: Gidon Studinski <gidons@codeaurora.org>
Signed-off-by: Alexei Avshalom Lazar <ailizaro@codeaurora.org>
Update snapshot register list to add CP_APRIV_CNTL and CP_SMMU_STREAM_ID
registers. This is needed to capture complete CP state required for
debugging.
Change-Id: Icb8c35481de12dde43aab666f0ecad2240dcaa35
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
MHI reset is triggered as part of EP shutdown. Shutdown
is blocked until MHI RESET bit is cleared in MHI CTRL reg.
There is a possibility of PCIe link going down during this
time. Since MHI RESET bit never gets cleared after 2 sec
wait_event_timeout reads the MHI CTRL reg and this results
into a memory abort. Fix this issue by using a boolean flag
as condition in wait_event_timeout. This flag is set when
MHI reset is triggered and cleared when reset is done.
Change-Id: I5b1831518255a38cde5b60406b5b9e9386b5477e
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Depending on timing there is a chance the channel initialization will
happen at different intervals. When this happens, the first channel
wakeup will be cleared by the init loop and never be set again by the
channel init. This leads to a stall in init because both channels
will never have both their wakeups set to signal channel init done.
Change-Id: I435e78c3e4b83cf6b827d3827f35d1e6a1b297fa
Acked-by: Chris Henroid <chenroid@qti.qualcomm.com>
Signed-off-by: Chris Lew <clew@codeaurora.org>
This change allows kernel modules to make calls to register external
display interfaces and deregister them.
Change-Id: Ia7236bd458565bbbdec4a8355c40a1c5a1bcab86
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
mhi_reg_write_enqueue API stores reg, val and valid which can go
out of order. In case valid is set to true before val is set,
offload worker running on another core ends up writing stale value
to register. Another possibility is valid being set to true but not
visible to other cores. When offload worker gets a chance to run,
this results into skipping register write. Fix these issues by
adding smp_wmb() between stores of val and valid and another after
valid is set.
Change-Id: I3b930e7fad4252d34386de525491f94997b34f36
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Add new GPU chip id and required code to
Support A619 GPU.
Change-Id: I9b4e8b35e536486c63661b050a2242538d873c2d
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
CVP SSR crashed when derefencing the pointer to a
shared memory buffer descriptor.
Change-Id: I3f7b690d90496efdf0451b5500578fee636f81fe
Signed-off-by: George Shen <sqiao@codeaurora.org>
Add support for locktorture and rcutorture test modules on Lahaina.
Change-Id: Ib903fab01f8ed84707d5717980f0467d41e67374
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
